Frequency synthesis circuit, satellite signal receiving device and terminal

By introducing a phase-locked loop and a frequency jump detection circuit into the satellite signal receiver, frequency jumps are detected and the signal tracking loop bandwidth is adjusted, thus solving the receiver lockout problem caused by frequency jumps in the reference oscillator and ensuring the stability and performance of the receiver.

CN224178158UActive Publication Date: 2026-04-28UNICORE COMM INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
UNICORE COMM INC
Filing Date
2025-03-31
Publication Date
2026-04-28

AI Technical Summary

Technical Problem

When the reference oscillator of a satellite signal receiver is affected by temperature changes, the frequency jump causes the receiver to lose lock. Existing technologies to improve the accuracy of the reference oscillator are costly and not suitable for widespread use.

Method used

Design a frequency synthesis circuit that includes a phase-locked loop sub-circuit and a frequency transition detection sub-circuit. By detecting frequency transitions and notifying the signal tracking loop to adjust the bandwidth, the receiver performance is ensured to be stable.

Benefits of technology

This ensures that the stability and performance of the signal tracking loop remain unaffected by frequency jumps in the reference oscillator, reducing the probability of loss of lock and improving the reliability of the satellite signal receiving device.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a frequency synthesis circuit, a satellite signal receiving device and a terminal.The frequency synthesis circuit comprises a phase-locked loop sub-circuit, and the phase-locked loop sub-circuit comprises a phase discriminator, a loop filter, a charge pump, a voltage-controlled oscillator and a frequency divider; and the hopping signal detection sub-circuit is used for carrying out hopping detection on the output signal of the phase discriminator, so that the performance of the receiver can still be ensured not to be influenced under the condition that the frequency hopping of the reference oscillation circuit occurs.
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Description

Technical Field

[0001] This utility model relates to signal processing circuits, and more specifically, to a frequency synthesis circuit, a satellite signal receiving device, and a terminal. Background Technology

[0002] Common structures of satellite signal receivers include: Figure 1 As shown, the accuracy of the reference oscillator has a significant impact on the receiver's performance. If the reference oscillator is sensitive to temperature changes, it will experience random frequency micro-jumps when the temperature of its operating environment changes. This may cause subsequent circuits to be unable to lock onto the jumping frequency, resulting in frequency lockout in the receiver.

[0003] To address this issue, the accuracy of the reference oscillator can be improved, and its sensitivity to temperature changes can be reduced. However, this also increases the price of the reference oscillator, making it unsuitable for widespread use. Utility Model Content

[0004] This utility model provides a frequency synthesis circuit, a satellite signal receiving device, and a terminal that can ensure the receiver's performance remains unaffected even when the reference oscillation circuit experiences a frequency jump.

[0005] The frequency synthesis circuit provided in this embodiment of the utility model includes:

[0006] A phase-locked loop circuit, comprising: a phase detector, a loop filter, a charge pump, a voltage-controlled oscillator, and a frequency divider;

[0007] And a transition signal detection sub-circuit configured to detect transitions in the phase detector output signal.

[0008] This utility model provides a satellite signal receiving device, comprising:

[0009] The radio frequency front-end processing circuit includes a frequency synthesis circuit, the baseband digital signal processing circuit includes a signal tracking loop circuit, and the positioning and navigation calculation circuit.

[0010] The frequency synthesis circuit includes: a phase-locked loop sub-circuit and a transition signal detection sub-circuit;

[0011] The phase-locked loop sub-circuit includes: a phase detector, a loop filter, a charge pump, a voltage-controlled oscillator, and a frequency divider;

[0012] The transition signal detection sub-circuit is configured to perform transition detection on the phase detector output signal.

[0013] The signal tracking loop circuit is configured to adjust the loop bandwidth based on the transition detection result.

[0014] The terminal provided in this embodiment of the present invention includes a satellite signal receiving device as described in any of the preceding embodiments.

[0015] The solution provided by this utility model embodiment can detect transition signals, and then use the frequency synthesis circuit to notify the subsequent signal tracking loop of the transition signal detection result, so that the signal tracking loop can adjust the bandwidth according to the detection result of the transition signal, thus providing support for the subsequent signal tracking loop to track the transition.

[0016] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solution of this utility model and do not constitute a limitation on the technical solution of this utility model.

[0018] Figure 1 This is a schematic diagram of a common structure of satellite signal receivers in the prior art;

[0019] Figure 2 A frequency synthesis circuit structure diagram provided in an embodiment of this application;

[0020] Figure 3 A schematic diagram of a phase-locked loop sub-circuit including micromolecular circuits provided for an embodiment of this application;

[0021] Figure 4 A schematic diagram of a phase-locked loop sub-circuit including a comparator sub-circuit provided for an embodiment of this application;

[0022] Figure 5 A schematic diagram of a phase-locked loop sub-circuit including a micro-molecule circuit and a comparator circuit, provided for an embodiment of this application;

[0023] Figure 6 A structural diagram of a satellite signal receiving device provided in an embodiment of this application;

[0024] Figure 7 This is a schematic diagram of an embodiment of a satellite signal receiving device provided in this application.

[0025] Figure 8 This is a terminal configuration diagram provided in an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0027] This study found that when the system clock source (i.e., the reference oscillator circuit) of a satellite receiver generates a random frequency jump, the phase-locked loop (PLL) in the frequency synthesizer can track this jump. However, after this jump is digitally quantized and transmitted to the signal tracking loop in the baseband digital signal processing circuit, if the bandwidth of the signal tracking loop is set too narrow, it cannot track this jump, i.e., a loss of lock occurs. However, the bandwidth of the signal tracking loop is usually adjustable. If the bandwidth of the signal tracking loop can be adjusted in a timely manner when a frequency jump occurs in the reference oscillator circuit, the probability of a loss of lock can be reduced.

[0028] Based on the results of the above research, this application provides a frequency synthesis circuit, such as... Figure 2 As shown, the frequency synthesis circuit includes:

[0029] Phase-locked loop circuit 200; the phase-locked loop circuit 200 includes: phase detector 2001, charge pump 2002, loop filter 2003, voltage-controlled oscillator 2004 and frequency divider 2005;

[0030] And a transition signal detection sub-circuit 201 configured to detect transitions in the output signal of the phase detector 2001.

[0031] The frequency synthesis circuit provided in this embodiment can detect transition signals, and then use the frequency synthesis circuit to notify the subsequent signal tracking loop of the transition signal detection result, so that the signal tracking loop can adjust the bandwidth according to the detection result of the transition signal, thus providing support for the subsequent signal tracking loop to track the transition.

[0032] The phase frequency detector (PFD) 2001 is configured to detect the difference (including phase difference and frequency difference) between the input reference signal and the feedback signal, and to output a control signal proportional to the difference. For example, if the phase detector detects a phase difference of Δϕ between the input reference signal and the feedback signal, the amplitude of the output control signal will be proportional to Δϕ; if the phase detector detects a frequency difference of Δf between the input reference signal and the feedback signal, the amplitude of the output control signal will be proportional to Δf.

[0033] The charge pump (CP) 2002 is configured to convert the control signal output by the phase detector (PFD) 2001 into a current signal, thereby controlling the charging and discharging of the loop filter (LF) 2003.

[0034] The loop filter (LF) 2003 is configured to filter out high-frequency components and noise in the output signal of the phase detector (PFD) 2001 and convert the current signal into a stable voltage signal.

[0035] The voltage-controlled oscillator (VCO) 2004 is configured to generate an output signal of a corresponding frequency based on the input voltage signal.

[0036] The divider 2005 is configured to adjust the frequency of the output signal of the voltage-controlled oscillator (VCO) 2004 for comparison with the input reference signal, such as dividing the high-frequency output signal of the VCO to reduce its frequency to a level comparable to the input signal.

[0037] In an exemplary embodiment, the transition signal detection sub-circuit 201 may include a micro-molecule circuit 2011. The micro-molecule circuit refers to a circuit capable of performing differentiation. Common micro-molecule circuits include: an RC differentiator circuit consisting of a resistor R and a capacitor C; an operational amplifier differentiator circuit constructed from an operational amplifier (Op-Amp); and a digital differentiator implemented based on a digital signal processor (DSP) or a microcontroller (MCU).

[0038] Figure 3 A schematic diagram of a transition signal detection sub-circuit 201 including a micro-molecular circuit 2011 is provided. The input terminal of the micro-molecular circuit 2011 is connected to the output terminal of the phase detector 2001, and the signal output from the output terminal of the micro-molecular circuit 2011 serves as the transition detection result. When a transition occurs in the signal at the input terminal of the micro-molecular circuit 2011, the signal output from the output terminal of the micro-molecular circuit 2011 is set to a high level; when the transition disappears, the signal output from the output terminal of the micro-molecular circuit 2011 is set to a low level.

[0039] When the system clock source is working normally, the phase-locked loop circuit 200 reaches a stable tracking state. At this time, the output signal of the phase detector 2001 is small and stable, and the output signal of the micro-molecule circuit 2011 is set to low level.

[0040] When a frequency jump occurs in the system clock source, the phase detector 2001 detects this jump and outputs a proportional control signal to the loop filter 2003 and the micro-molecular circuit 2011. The loop filter 2003, with its relatively wide bandwidth, can stably track this frequency jump. After filtering, it transmits the signal to the voltage-controlled oscillator 2004 for frequency control, ensuring that the output frequency tracks the input frequency jump. Upon receiving the control signal containing the jump information, the micro-molecular circuit 2011 sets its output signal to a high level, which can be used to notify subsequent circuits that a frequency jump has occurred in the current frequency synthesis circuit output.

[0041] When the frequency jump of the system clock source disappears, the phase-locked loop circuit 200 returns to a stable tracking state. At this time, the output signal of the phase detector 2001 returns to a small and stable state, and the output signal of the micro-molecule circuit 2011 is set to a low level.

[0042] In another exemplary embodiment, the transition signal detection sub-circuit 201 includes a comparison sub-circuit 2012. The comparison sub-circuit 2012 refers to a circuit capable of performing signal comparison. The comparison sub-circuit can be composed of a comparator, or the comparison function can be implemented using other electronic components (such as operational amplifiers, resistors, capacitors, etc.).

[0043] Figure 4 A schematic diagram of a transition signal detection subcircuit 201 including a comparator subcircuit 2012 is provided. The input terminal of the comparator subcircuit 2012 is connected to the output terminal of the loop filter 2003 or the output terminal of the charge pump 2002 (in these two connection methods, when the input terminal of the comparator subcircuit 2012 is connected to the output terminal of the loop filter 2003, the accuracy of the output result of the comparator subcircuit can be improved because the loop filter 2003 can filter out noise). The signal output from the output terminal of the comparator subcircuit 2012 is used as the transition detection result; wherein, when the signal at the input terminal of the comparator subcircuit 2012 transitions, the signal output from the output terminal of the comparator subcircuit 2012 is set to a high level. When the signal transition at the input terminal of the comparator subcircuit 2012 disappears, the signal output from the output terminal of the comparator subcircuit 2012 is set to a low level.

[0044] When the system clock source is working normally, the phase-locked loop sub-circuit 200 reaches a stable tracking state. At this time, the output signal of the phase detector 2001 is small and stable, and the output signal of the comparator sub-circuit 2012 is set to low level.

[0045] When a frequency jump occurs in the system clock source, the phase detector 2001 detects the jump and outputs a control signal proportionally to the loop filter 2003. The loop filter 2003 has a relatively wide bandwidth and can stably track this frequency jump. After filtering, it outputs a signal containing the jump information to the voltage-controlled oscillator 2004. The output signal of the comparator circuit 2012, which receives the output signal from the loop filter 2003 or the charge pump 2002, is set to a high level to notify subsequent circuits that a frequency jump has occurred in the current frequency synthesis circuit output.

[0046] When the frequency jump of the system clock source disappears, the phase-locked loop sub-circuit 200 returns to a stable tracking state. At this time, the output signal of the phase detector 2001 returns to a small and stable state, and the output signal of the comparator sub-circuit 2012 is set to a low level.

[0047] In another exemplary embodiment, the transition signal detection sub-circuit 201 includes: a micro-molecule circuit 2011 and a comparison sub-circuit 2012;

[0048] Figure 5 A schematic diagram of a phase-locked loop sub-circuit 200 including a micro-molecule circuit 2011 and a comparator circuit 2012 is given.

[0049] The input terminal of the micromolecular circuit 2011 is connected to the output terminal of the phase detector 2001, and the signal output by the output terminal of the micromolecular circuit 2011 is used as the first transition detection result; wherein, when the signal at the input terminal of the micromolecular circuit 2011 transitions, the signal output by the output terminal of the micromolecular circuit 2011 is set to a high level, and when the signal transition at the input terminal of the micromolecular circuit 2011 disappears, the signal output by the output terminal of the micromolecular circuit 2011 is set to a low level.

[0050] The input terminal of the comparator circuit 2012 is connected to the output terminal of the micromolecular circuit 2011. The signal output by the comparator circuit 2012 serves as the second transition detection result. Specifically, when the first transition detection result is high, the second transition detection result output by the comparator circuit 2012 is also high. When the first transition detection result is low, since the output low level is less than the reference voltage of the comparator circuit 2012, the second transition detection result output by the comparator circuit 2012 is low.

[0051] This application also provides a satellite signal receiving device, such as... Figure 6 As shown, the satellite signal receiving device includes:

[0052] The circuit includes a radio frequency front-end processing circuit 601 with a frequency synthesis circuit 6010, a baseband digital signal processing circuit 602 with a signal tracking loop circuit 6020, and a positioning and navigation calculation circuit 603.

[0053] The frequency synthesis circuit 6010 in this embodiment can be the frequency synthesis circuit described in any of the previous embodiments;

[0054] The signal tracking loop circuit 6020 is configured to adjust the loop bandwidth according to the transition detection result output by the frequency synthesis circuit 6010.

[0055] The satellite signal receiving device provided in this embodiment can detect transition signals and adjust the bandwidth of the signal tracking loop circuit according to the detection results of the transition signals, thereby avoiding the phenomenon of loss of lock-up in the signal tracking loop circuit when the signal transitions, and ensuring the stable performance of the satellite signal receiving device.

[0056] Figure 7 A schematic diagram of a satellite signal receiving device is provided. The transition detection result output from the frequency synthesis circuit is sent to a digital signal processor, which then sends the transition detection result to the signal tracking loop circuit. The signal tracking loop circuit adjusts its loop bandwidth based on the transition detection result.

[0057] In one exemplary embodiment, the signal tracking loop circuit is configured to increase the loop bandwidth when a transition is detected, and to decrease the loop bandwidth when the transition disappears.

[0058] This embodiment improves the transient response capability of the signal tracking loop circuit by dynamically adjusting the loop bandwidth, avoids signal tracking loop circuit lockout, and ensures the performance of the satellite signal receiving device.

[0059] This application also provides a terminal, such as... Figure 8 As shown, the terminal includes a satellite signal receiving device 801 as described in any of the previous embodiments.

[0060] In one exemplary embodiment, the terminal may be one or more of a vehicle-mounted terminal and a handheld terminal.

[0061] In the description of this utility model, it should be noted that the terms "upper", "lower", "one side", "the other side", "one end", "the other end", "side", "opposite", "four corners", "periphery", "'mouth' structure", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the structure referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0062] In the description of the embodiments of this utility model, unless otherwise expressly specified and limited, the terms "connection," "direct connection," "indirect connection," "fixed connection," "installation," and "assembly" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection. The terms "installation," "connection," and "fixed connection" can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal communication between two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0063] Although the embodiments disclosed in this utility model are as described above, the content described is only for the purpose of facilitating understanding of this utility model and is not intended to limit this utility model. Any person skilled in the art to which this utility model pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this utility model, but the patent protection scope of this utility model shall still be defined by the appended claims.

Claims

1. A frequency synthesis circuit, characterized in that, The circuit includes: A phase-locked loop sub-circuit, comprising: a phase detector, a loop filter, a charge pump, a voltage-controlled oscillator, and a frequency divider connected in sequence to form a closed loop; And a transition signal detection sub-circuit configured to detect transitions in the phase detector output signal; The transition signal detection subcircuit includes a micro-molecule circuit, the input of which is connected to the output of the phase detector; or, the transition signal detection subcircuit includes a comparator subcircuit, the input of which is connected to the output of the loop filter or the output of the charge pump; or, the transition signal detection subcircuit includes both a micro-molecule circuit and a comparator subcircuit, the input of which is connected to the output of the phase detector, and the input of which is connected to the output of the micro-molecule circuit.

2. The frequency synthesis circuit according to claim 1, characterized in that, In the case where the transition signal detection sub-circuit includes a micro-molecular circuit: The signal output from the output terminal of the micromolecular circuit serves as the transition detection result; wherein, when the signal at the input terminal of the micromolecular circuit undergoes a transition, the signal output from the output terminal of the micromolecular circuit is set to a high level.

3. The frequency synthesis circuit according to claim 1, characterized in that, In the case where the transition signal detection subcircuit includes a comparison subcircuit: The signal output from the output terminal of the comparator circuit is used as the transition detection result; wherein, when the signal at the input terminal of the comparator circuit transitions, the signal output from the output terminal of the comparator circuit is set to a high level.

4. The frequency synthesis circuit according to claim 1, characterized in that, In the case where the transition signal detection sub-circuit includes: a micro-molecule circuit and a comparator sub-circuit: The signal output from the output terminal of the micro-molecule circuit is used as the first transition detection result; wherein, when the signal at the input terminal of the micro-molecule circuit undergoes a transition, the signal output from the output terminal of the micro-molecule circuit is set to a high level; The signal output from the output terminal of the comparator circuit is used as the second transition detection result; wherein, when the first transition detection result is high level, the signal output from the output terminal of the comparator circuit is set to high level.

5. A satellite signal receiving device, characterized in that, The satellite signal receiving device includes: The radio frequency front-end processing circuit includes a frequency synthesis circuit, the baseband digital signal processing circuit includes a signal tracking loop circuit, and the positioning and navigation calculation circuit. The frequency synthesis circuit includes: a phase-locked loop sub-circuit and a transition signal detection sub-circuit; The phase-locked loop sub-circuit includes: a phase detector, a loop filter, a charge pump, a voltage-controlled oscillator, and a frequency divider; The transition signal detection sub-circuit is configured to perform transition detection on the phase detector output signal. The signal tracking loop circuit is configured to adjust the loop bandwidth based on the transition detection result.

6. The satellite signal receiving device according to claim 5, characterized in that, The transition signal detection sub-circuit includes: a micro-molecular circuit; The input terminal of the micro-molecule circuit is connected to the output terminal of the phase detector, and the signal output by the output terminal of the micro-molecule circuit serves as the transition detection result; wherein, when the signal at the input terminal of the micro-molecule circuit undergoes a transition, the signal output by the output terminal of the micro-molecule circuit is set to a high level.

7. The satellite signal receiving device according to claim 5, characterized in that, The transition signal detection sub-circuit includes: a comparison sub-circuit; The input terminal of the comparator circuit is connected to the output terminal of the loop filter or the output terminal of the charge pump, and the signal output by the output terminal of the comparator circuit is used as the transition detection result; wherein, when the signal at the input terminal of the comparator circuit transitions, the signal output by the output terminal of the comparator circuit is set to a high level.

8. The satellite signal receiving device according to claim 5, characterized in that, The transition signal detection sub-circuit includes: a micro-molecule circuit and a comparator sub-circuit; The input terminal of the micro-molecule circuit is connected to the output terminal of the phase detector, and the signal output by the output terminal of the micro-molecule circuit is used as the first transition detection result; wherein, when the signal at the input terminal of the micro-molecule circuit transitions, the signal output by the output terminal of the micro-molecule circuit is set to a high level; The input terminal of the comparator circuit is connected to the output terminal of the micromolecule circuit, and the signal output by the output terminal of the comparator circuit is used as the second transition detection result; wherein, when the first transition detection result is high level, the signal output by the output terminal of the comparator circuit is set to high level.

9. The satellite signal receiving device according to claim 5, characterized in that, The signal tracking loop circuit is configured to increase the loop bandwidth when a transition is detected, and to decrease the loop bandwidth when the transition disappears.

10. A terminal, characterized in that, The terminal includes a satellite signal receiving device as described in any one of claims 5-9.