800G bit error tester supporting multiple rates
The 800G bit error rate tester, which integrates the bit error rate tester and the test board into one unit, solves the problem of high outsourcing costs for bit error rate testing equipment in optical module production, simplifies the production environment, reduces expansion costs, and improves production efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- YIGU OPTOELECTRONICS TECHNOLOGY (HUNAN) CO LTD
- Filing Date
- 2025-04-16
- Publication Date
- 2026-04-28
AI Technical Summary
In current optical module production, the cost of purchasing error testing equipment is high, and the setup environment is complex and time-consuming, resulting in high production line expansion costs and long batch production times.
Design an 800G bit error rate tester that supports multiple rates, integrating the bit error rate tester and test board into one unit, for use in the production of high-speed modules in QSFP112-DD and OSFP112 packages, simplifying the production environment and improving efficiency.
The integrated design simplifies the manufacturing environment, reduces costs, and improves production efficiency.
Smart Images
Figure CN224178166U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of optical module tuning and testing technology, specifically an 800G bit error rate meter that supports multiple rates. Background Technology
[0002] With the rapid development of artificial intelligence (AI) technology, the computing power and data transmission requirements of AI clusters are constantly increasing. Currently, major global cloud vendors have deployed 200G / 400G optical modules in batches within data centers. As AI applications are gradually implemented, the demand for high computing power is catalyzing the demand for higher-speed 800G / 1.6T optical modules, and a new round of upgrades for optical modules has begun. LightCounting predicts that 200G / 400G / 800G optical module products are expected to continue to iterate, and the shipment volume of high-speed optical modules is expected to increase significantly. The global shipment volume of 800G Ethernet optical modules may reach 110,000, 390,000, and 1.19 million units in 2022, 2023, and 2024, respectively. By the end of 2025, 800G optical modules will begin to dominate this market segment.
[0003] To meet this demand, optical module manufacturers need to expand their production capacity with a large number of bit error rate testing equipment and QSFP112-DD and OSFP112 test boards at different rates. However, purchasing bit error rate testing equipment is expensive, and the bit error rate testing equipment and QSFP112-DD and OSFP112 test boards need to be connected to each other using high-speed cables. This results in a complex and time-consuming setup environment, leading to high production expansion costs and long batch production times. Utility Model Content
[0004] The purpose of this invention is to provide an 800G bit error rate tester that supports multiple rates. By combining the bit error rate tester and the test board into one, it meets the requirements for the production and manufacturing of high-speed modules in QSFP112-DD and OSFP112 packages, and solves the problems of complex and time-consuming setup environment, resulting in high production line expansion costs and long batch production time.
[0005] To achieve the above objectives, this utility model provides the following technical solution: an 800G bit error rate tester supporting multiple rates, comprising a bit error rate tester body, wherein the bit error rate tester body includes a first connector, a second connector, a signal output interface, a power management unit, a code transmission and detection unit, a microcontroller unit, a power interface and a USB interface, wherein the power interface is connected to the power management unit, and the power management unit is interconnected with the first connector and the code transmission and detection unit, and the signal output interface is a Trigger signal output interface;
[0006] The USB interface is connected to the microcontroller unit, which is interconnected with the code generation and detection unit, the first connector, and the second connector. The code generation and detection unit, the first connector, the second connector, and the Trigger signal output interface are also interconnected.
[0007] Preferably, the first connector is a QSFP112-DD connector, and the first and second connectors, together with the code transmission and detection unit, output external power to power the module and the code transmission and detection unit. The QSFP112-DD connector enables the microcontroller unit to perform module IIC communication, low-speed logic signal control and detection, and code transmission and detection control according to the received commands.
[0008] Preferably, the second connector is an OSFP112 connector. The first and second connectors output a Trigger signal, which is transmitted to the Trigger signal output interface for use by external devices.
[0009] Preferably, the microcontroller unit is configured to be connected to the code generation and detection unit, and is tested in conjunction with the 200G / 400G / 800G module packaged with the first connector and the second connector, and outputs a Trigger signal to an external device to assist in realizing the module's optical eye diagram test function.
[0010] Preferably, the microcontroller unit works in conjunction with the 200G / 400G / 800G modules packaged with the first and second connectors for signal control and detection, enabling IIC communication and low-speed logic signal control and detection of the 200G / 400G / 800G modules packaged with QSFP112-DD and OSFP112.
[0011] Preferably, the main body of the bit error rate tester includes a test board, and is integrated with the test board, which simultaneously meets the requirements for the production and manufacturing of high-speed modules packaged with QSFP112-DD connectors and OSFP112 connectors, simplifying the production environment, improving production efficiency, and reducing production costs.
[0012] Preferably, the main body of the bit error rate tester is connected to and interacts with external automation software via a USB interface, the bit generation and detection unit is controlled by the external automation software, and the bit detection result data can be uploaded to the external automation software to realize the automation of module debugging and testing.
[0013] The present invention provides an 800G bit error rate meter that supports multiple rates, which has at least the following beneficial effects:
[0014] This multi-rate 800G bit error rate tester integrates the bit error rate tester and test board into one unit by adapting a single bit error rate tester to the production of 200G / 400G / 800G optical modules. It also meets the requirements for the production of high-speed modules in QSFP112-DD and OSFP112 packages, simplifying the production environment and improving production efficiency. Attached Figure Description
[0015] Figure 1 This is a functional block diagram of the 800G bit error rate meter supporting multiple rates according to this utility model;
[0016] Figure 2 This is a schematic diagram of the main structure of the 800G bit error rate tester supporting multiple rates according to this utility model. Detailed Implementation
[0017] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0018] Please see Figure 1-2 The present invention provides an embodiment of an 800G bit error rate tester that supports multiple rates, comprising a bit error rate tester body, the bit error rate tester body comprising a first connector, a second connector, a signal output interface, a power management unit, a code transmission and detection unit, a microcontroller unit, a power interface and a USB interface, the power interface being connected to the power management unit, and the power management unit being interconnected with the first connector and the code transmission and detection unit, the signal output interface being a Trigger signal output interface;
[0019] The USB interface is connected to the microcontroller unit, the microcontroller unit is connected to the code transmission and detection unit, the first connector and the second connector, and the code transmission and detection unit, the first connector and the second connector and the Trigger signal output interface are connected.
[0020] The first connector is a QSFP112-DD connector, and the first and second connectors, together with the code transmission and detection unit, output external power to power the module and the code transmission and detection unit. The QSFP112-DD connector enables the microcontroller unit to perform module IIC communication, low-speed logic signal control and detection, and code transmission and detection control according to the received commands.
[0021] The second connector is an OSFP112 connector. The first and second connectors output Trigger signals, which are then transmitted to the Trigger signal output interface for use by external devices.
[0022] The main body of the bit error rate tester connects to and interacts with external automation software via a USB interface. The code generation and detection unit is controlled by the external automation software, and the detection result data can be uploaded to the external automation software to realize the automation of module debugging and testing.
[0023] In Example 1, a microcontroller unit is configured and connected to a code transmission and detection unit, and is used for testing 200G / 400G / 800G modules packaged with first and second connectors. It outputs a Trigger signal to an external device to assist in the module's optical eye diagram testing function. The microcontroller unit can configure the code transmission and detection unit according to received commands, enabling multi-rate and multi-detection modes. The microcontroller unit coordinates with the 200G / 400G / 800G modules packaged with first and second connectors for signal control and detection, allowing the microcontroller unit to perform IIC communication and low-speed logic signal control and detection on the 200G / 400G / 800G modules packaged with QSFP112-DD and OSFP112 connectors.
[0024] Example 2, as Figure 1-2 As shown, the main body of the bit error rate tester includes a test board, which is integrated with the test board for the production of the packaging modules of the first and second connectors. This multi-rate 800G bit error rate tester can adapt to the production of 200G / 400G / 800G optical modules with one bit error rate tester. By integrating the bit error rate tester and the test board into one, it can meet the production and manufacturing needs of both QSFP112-DD and OSFP112 packaged high-speed modules, simplifying the production environment and improving production efficiency.
[0025] Working principle: This 800G bit error rate tester supports multiple rates;
[0026] This multi-rate 800G bit error rate meter includes a first connector for the QSFP112-DD and a second connector for the OSFP112. By using domestically produced connectors and providing a module connection interface, it utilizes domestically produced connectors to provide Trigger signals to external devices through the Trigger signal output interface, thereby assisting in the measurement of eye diagram signals of optical modules, and offers higher cost-effectiveness.
[0027] By using domestically produced connectors for the power input interface and providing a device power input interface, using domestically produced connectors for the USB interface and providing a device communication interface, the power management unit is composed of domestically produced power chips, which are more cost-effective and complete the power control and protection functions. The code transmission and detection unit is composed of DSP code transmission and detection chips, which provides code transmission and detection functions for module testing, while the microcontroller unit is composed of microcontroller chips, which provides control and communication interaction functions for the bit error rate tester.
[0028] This bit error rate tester enables a single tester to be used in the production of 200G / 400G / 800G optical modules, combining the bit error rate tester and test board into one unit. It can also meet the requirements of QSFP112-DD and OSFP112 packaged high-speed modules, simplifying the production environment and improving production efficiency.
[0029] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0030] In the description of this utility model, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly, for example, they can refer to a fixed connection or a detachable connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.
Claims
1. An 800G bit error rate tester supporting multiple rates, comprising a main body of the bit error rate tester, characterized in that: The main body of the bit error rate tester includes a first connector, a second connector, a signal output interface, a power management unit, a code transmission and detection unit, a microcontroller unit, a power interface, and a USB interface. The power interface is connected to the power management unit, and the power management unit is interconnected with the first connector and the code transmission and detection unit. The signal output interface is a Trigger signal output interface. The USB interface is connected to the microcontroller unit, which is interconnected with the code generation and detection unit, the first connector, and the second connector. The code generation and detection unit, the first connector, the second connector, and the Trigger signal output interface are also interconnected.
2. The 800G bit error rate tester supporting multiple rates according to claim 1, characterized in that: The first connector is a QSFP112-DD connector, and the first and second connectors are connected to the code generation and detection unit and output external power to power the module and the code generation and detection unit.
3. The 800G bit error rate tester supporting multiple rates according to claim 1, characterized in that: The second connector is an OSFP112 connector. The first and second connectors output a Trigger signal, which is then transmitted to the Trigger signal output interface.
4. The 800G bit error rate tester supporting multiple rates according to claim 1, characterized in that: The microcontroller unit is configured to be connected to the code transmission and detection unit, and is tested and cooperated with the 200G / 400G / 800G module that is adapted to the first connector and the second connector.
5. The 800G bit error rate tester supporting multiple rates according to claim 4, characterized in that: The microcontroller unit works in conjunction with the 200G / 400G / 800G modules packaged in the first and second connectors for signal control and detection.
6. The 800G bit error rate tester supporting multiple rates according to claim 1, characterized in that: The main body of the bit error rate tester includes a test board, and the main body of the bit error rate tester and the test board are integrated into one unit.
7. The 800G bit error rate tester supporting multiple rates according to claim 1, characterized in that: The main body of the bit error rate tester is connected to and interacts with external automation software via a USB interface, and the code generation and detection unit is controlled by the external automation software.