Capacitor chip structure

Abstract

The embodiment of the utility model provides a capacitor chip structure. The structure comprises a glass substrate which comprises a first surface and a second surface which are oppositely arranged; the second conductive layer is located on the side, away from the first conductive layer, of the capacitor dielectric layer; the boundary of the second conductive layer shrinks inwards towards the center of the capacitor chip structure relative to the boundary of the first conductive layer; the insulating layer is positioned on one side, far away from the capacitor dielectric layer, of the second conductive layer; the first electrical connection structure sequentially comprises a first UBM layer, a first copper-tin alloy layer and a first tin layer; the second electrical connection structure sequentially comprises a second UBM layer, a second copper-tin alloy layer and a second tin layer; the thickness of the first UBM layer is greater than the thickness of the first copper-tin alloy layer and greater than the thickness of the first tin layer; the thickness of the second UBM layer is greater than the thickness of the second copper-tin alloy layer and greater than the thickness of the second tin layer.

Description

A capacitor chip structure Technical Field

[0001] The embodiments disclosed herein relate to the field of capacitor technology, and more particularly to a capacitor chip structure and manufacturing method. Background Technology

[0002] Multi-layer ceramic capacitors (MLCCs) are ceramic dielectric films with printed electrodes (internal electrodes) stacked in a staggered manner, sintered at high temperature in a single process to form a ceramic chip, and then sealed with metal layers (external electrodes) at both ends of the chip, thus forming a monolithic structure, hence the name monolith capacitor.

[0003] Currently, silicon substrates are mostly used as substrates for the capacitor chip structure in multilayer ceramic chip capacitors. However, silicon substrates do not provide sufficient support strength, so the capacitor chip structure needs to be repackaged before it can be used. Summary of the Invention

[0004] In view of this, the present disclosure provides a capacitor chip structure to improve the support strength of the substrate in the capacitor chip structure and reduce the packaging difficulty.

[0005] This disclosure provides a capacitor chip structure, including:

[0006] A glass substrate, including a first surface and a second surface disposed opposite to each other;

[0007] A first conductive layer is located on a first surface of the glass substrate;

[0008] A capacitor dielectric layer is located on the side of the first conductive layer away from the glass substrate; the capacitor dielectric layer also covers the sidewall of the first conductive layer, and the capacitor dielectric layer is provided with a first through hole, the first through hole penetrating the capacitor dielectric layer and exposing a portion of the surface of the first conductive layer.

[0009] The second conductive layer is located on the side of the capacitor dielectric layer away from the first conductive layer; the boundary of the second conductive layer is recessed towards the center of the capacitor chip structure relative to the boundary of the first conductive layer.

[0010] An insulating layer is located on the side of the second conductive layer away from the capacitor dielectric layer. The insulating layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer, and the sidewall of the first through hole. The insulating layer is provided with a second through hole and a third through hole that penetrate the insulating layer. The second through hole exposes a portion of the surface of the second conductive layer.

[0011] The first electrical connection structure includes, in sequence, a first UBM layer, a first copper-tin alloy layer, and a first tin layer; the first tin layer encapsulates the first copper-tin alloy layer, and the first copper-tin alloy layer encapsulates the first UBM layer; the central portion of the first UBM layer is located within the second via and electrically connected to the second conductive layer, and the edge portion of the first UBM layer is located on the surface of the insulating layer away from the glass substrate.

[0012] The second electrical connection structure includes, in sequence, a second UBM layer, a second copper-tin alloy layer, and a second tin layer; the second tin layer encapsulates the second copper-tin alloy layer, and the second copper-tin alloy layer encapsulates the second UBM layer; the central portion of the second UBM layer is located in the third via and passes through the first via and is electrically connected to the first conductive layer; the edge portion of the second UBM layer is located on the surface of the insulating layer away from the glass substrate.

[0013] The thickness of the first UBM layer is greater than the thickness of the first copper-tin alloy layer, and the thickness of the first UBM layer is greater than the thickness of the first tin layer.

[0014] The thickness of the second UBM layer is greater than the thickness of the second copper-tin alloy layer, and the thickness of the second UBM layer is greater than the thickness of the second tin layer.

[0015] Optionally, the thickness of the first UBM layer is greater than or equal to 3.0 micrometers and less than or equal to 30 micrometers;

[0016] The thickness of the first copper-tin alloy layer is greater than or equal to 0.2 micrometers and less than or equal to 2.0 micrometers;

[0017] The thickness of the first tin layer is greater than or equal to 0.5 micrometers and less than or equal to 3.0 micrometers.

[0018] Optionally, the thickness of the second UBM layer is greater than or equal to 3.0 micrometers and less than or equal to 30 micrometers;

[0019] The thickness of the second copper-tin alloy layer is greater than or equal to 0.2 micrometers and less than or equal to 2.0 micrometers;

[0020] The thickness of the second tin layer is greater than or equal to 0.5 micrometers and less than or equal to 3.0 micrometers.

[0021] Optionally, the first UBM layer sequentially includes a first bottom metal layer, a first intermediate alloy layer, and a first outer anti-oxidation layer, wherein the first bottom metal layer and the second conductive layer are in contact;

[0022] And / or, the second UBM layer sequentially includes a second bottom metal layer, a second intermediate alloy layer, and a second outer anti-oxidation layer, wherein the second bottom metal layer and the first conductive layer are in contact.

[0023] Optionally, a third conductive layer may also be included, wherein the third conductive layer and the second conductive layer are disposed in the same layer;

[0024] The third conductive layer and the second conductive layer are insulated from each other by the insulating layer;

[0025] The central portion of the third conductive layer is located in the first through hole and is electrically connected to the first conductive layer, and the edge portion of the third conductive layer is located on the side of the capacitor dielectric layer away from the first conductive layer.

[0026] The central portion of the second electrical connection structure is located in the third through hole and is electrically connected to the first conductive layer through the third conductive layer.

[0027] Optionally, the insulating layer includes a passivation layer;

[0028] The passivation layer is located on the side of the second conductive layer away from the capacitor dielectric layer. The passivation layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer, and the sidewall of the first via.

[0029] Optionally, the insulating layer further includes a buffer layer located on the side of the passivation layer away from the second conductive layer, and the buffer layer also covers the sidewall of the passivation layer within the second via and the third via.

[0030] Optionally, the insulating layer includes a passivation layer;

[0031] The passivation layer is located on the side of the second conductive layer away from the capacitor dielectric layer, and the passivation layer is also located on the side of the third conductive layer away from the first conductive layer;

[0032] The passivation layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer, and a portion of the surface of the third conductive layer away from the first conductive layer.

[0033] The third conductive layer and the second conductive layer are insulated from each other by the passivation layer.

[0034] Optionally, the insulating layer further includes a buffer layer located on the side of the passivation layer away from the second conductive layer and the third conductive layer, and the buffer layer also covers the sidewall of the passivation layer within the second via and the third via.

[0035] Optionally, the capacitor chip structure, in a cross-sectional shape parallel to the first surface, includes two oppositely arranged first long sides and two oppositely arranged first short sides, the first long sides and the first short sides being perpendicularly arranged, and the length of the first long side being greater than the length of the first short side.

[0036] The second through hole is located at the first end of the capacitor chip structure, and the third through hole is located at the second end of the capacitor chip structure. The direction from the first end of the capacitor chip structure to the second end of the capacitor chip structure is parallel to the first long side.

[0037] Optionally, the cross-sectional pattern of the first tin layer on the first surface includes two oppositely arranged second long sides and two oppositely arranged second short sides, the second long sides and the first short sides are parallel to each other, the second short sides and the first long sides are parallel to each other, and the length of the second long side is greater than the length of the second short side.

[0038] The length of the second shorter side is less than one-third of the length of the first longer side.

[0039] Optionally, the length of the second short side is greater than or equal to 10% of the length of the first long side, and less than or equal to 30% of the length of the first long side;

[0040] And / or, the length of the second longer side is greater than or equal to 40% of the length of the first shorter side, and less than or equal to 90% of the length of the first shorter side.

[0041] Optionally, on one side of the first end of the capacitor chip structure, the distance between the second long side and the first short side near the first end of the capacitor chip structure is greater than or equal to 15 micrometers and less than or equal to 40 micrometers.

[0042] And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the second short side and the first long side is greater than or equal to 15 micrometers and less than or equal to 40 micrometers.

[0043] Optionally, the cross-sectional pattern of the second tin layer on the first surface includes two oppositely arranged third long sides and two oppositely arranged third short sides. The third long sides and the first short sides are arranged parallel to each other, and the third short sides and the first long sides are arranged parallel to each other. The length of the third long side is greater than the length of the third short side, and the length of the third short side is less than one-third of the length of the first long side.

[0044] Optionally, the length of the third short side is greater than or equal to 10% of the length of the first long side, and less than or equal to 30% of the length of the first long side;

[0045] And / or, the length of the third long side is greater than or equal to 40% of the length of the first short side, and less than or equal to 90% of the length of the first short side.

[0046] Optionally, on one side of the second end of the capacitor chip structure, the distance between the third long side and the first short side near the second end of the capacitor chip structure is greater than or equal to 15 micrometers and less than or equal to 40 micrometers.

[0047] And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the third short side and the first long side is greater than or equal to 15 micrometers and less than or equal to 40 micrometers.

[0048] Optionally, the boundary of the second conductive layer is recessed inwards from the boundary of the first conductive layer towards the center of the capacitor chip structure by a value greater than or equal to 3 micrometers. The capacitor chip structure provided in this disclosure has the first electrical connection structure and the second electrical connection structure located on the same surface of the capacitor chip structure, reducing the mounting difficulty of the capacitor chip structure and facilitating electrical connection with other electrical components. The first electrical connection structure sequentially includes a first UBM layer, a first copper-tin alloy layer, and a first tin layer; the second electrical connection structure sequentially includes a second UBM layer, a second copper-tin alloy layer, and a second tin layer. In the first electrical connection structure, the thickness of the first UBM layer is greater than the thickness of the first copper-tin alloy layer, and the thickness of the first UBM layer is greater than the thickness of the first tin layer, increasing the thickness, current carrying capacity, and heat dissipation capacity of the first electrical connection structure. In the second electrical connection structure, the thickness of the second UBM layer is greater than the thickness of the second copper-tin alloy layer, and the thickness of the second UBM layer is greater than the thickness of the first tin layer, increasing the thickness, current carrying capacity, and heat dissipation capacity of the second electrical connection structure. Furthermore, the layered structure in both the first and second electrical connection structures, where a tin layer encapsulates a copper-tin alloy layer, and the copper-tin alloy layer encapsulates a UBM layer, reduces leakage current and increases the area of ​​the copper-tin alloy layer and the tin layer, thereby improving heat dissipation. The use of a glass substrate provides greater structural strength compared to a silicon substrate, eliminating the need for secondary packaging to enhance structural strength, reducing packaging complexity, and resulting in a better quality factor (Q value) for the capacitor chip. The capacitor dielectric layer insulates the first and second conductive layers. The first conductive layer serves as the first electrode of the capacitor, receiving electrical signals through the second electrical connection structure; the second conductive layer serves as the second electrode, receiving electrical signals through the first electrical connection structure. The boundary of the second conductive layer is recessed towards the center of the capacitor chip structure relative to the boundary of the first conductive layer, allowing the dielectric layer to cover the surface and sidewalls of the non-electrically connected portions of the first and second conductive layers, achieving better electrical isolation. The insulating layer covers the surface and sidewalls of the capacitor dielectric layer that are not covered by the second conductive layer. The insulating layer also covers the surface and sidewalls of the non-electrically connected portion of the second conductive layer and the first electrical connection structure, as well as the surface of the non-electrically connected portion of the first conductive layer and the second electrical connection structure. The capacitor dielectric layer and the insulating layer serve as an insulating encapsulation for the capacitor chip structure.

[0049] It should be noted that the above description of the structure and manufacturing method of the surface acoustic wave filter chip and the related descriptions to be presented below are merely exemplary and explanatory, and are not intended to limit this application. Attached Figure Description

[0050] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of each embodiment will be described in detail below. It should be specifically noted that the drawings described below only relate to the embodiments of this disclosure and are not intended to limit this disclosure. It must also be pointed out that the various features shown in the drawings are not drawn to scale. In fact, for clarity of explanation, arbitrarily increasing or decreasing the size of various features is sometimes necessary.

[0051] Figure 1: A plan view of a capacitor chip structure.

[0052] Figure 2: A schematic cross-sectional view of a capacitor chip structure, which is the AA′ section of the top plan view shown in Figure 1.

[0053] Figure 3: A plan view of a capacitor structure.

[0054] Figure 4: A cross-sectional schematic diagram of a capacitor chip structure, which is the AA′ section of the top plan view shown in Figure 3.

[0055] Figure 5 shows a schematic diagram of the process steps related to a disclosed embodiment of a method for manufacturing a capacitor chip structure.

[0056] Figures 6 to 12 are schematic cross-sectional views of various process steps related to the manufacturing method of the capacitor chip structure of this disclosure.

[0057] Figure 13 is a schematic diagram of the process steps related to a disclosed embodiment of a method for manufacturing a capacitor chip structure.

[0058] Figures 14 to 18 are schematic cross-sectional views of each process step in the manufacturing method of the capacitor chip structure of this disclosure.

[0059] The reference numerals in Figures 1 to 18 are as follows:

[0060] 100: Glass substrate; 110: First conductive layer; 120: Capacitor dielectric layer; 130: Second conductive layer; 145: Insulating layer; 135: Passivation layer; 140: Buffer layer; 400: First via; 150: Second via; 160: Third via; 170: First UBM layer; 180: Second UBM layer; 190: First copper-tin alloy layer; 200: Second copper-tin alloy layer; 210: First tin layer; 220: Second tin layer; L1: Length of the first long side; W1: Length of the first short side; L2: Length of the second short side; W2: Length of the second long side; L3: Length of the third short side; W3: Length of the third long side; 130b: Third conductive layer. Detailed Implementation

[0061] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings. It should also be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.

[0062] To improve the support strength of the substrate in the capacitor chip structure and reduce the packaging difficulty, the embodiments of this disclosure provide the following technical solutions:

[0063] Figure 1 shows a plan view of a capacitor chip structure, with the location of section AA′ marked. Figure 2 is a cross-sectional schematic diagram of a capacitor chip structure.

[0064] The structural features of the capacitor chip structure of the present disclosure (Embodiment 1) are described in detail below with reference to Figures 1 and 2.

[0065] The capacitor chip structure includes: a glass substrate 100, including a first surface and a second surface disposed opposite to each other; a first conductive layer 110, the first conductive layer 110 being located on the first surface of the glass substrate 100; a capacitor dielectric layer 120, the capacitor dielectric layer 120 being located on the side of the first conductive layer 110 away from the glass substrate 100; the capacitor dielectric layer 120 also covers the sidewall of the first conductive layer 110, and the capacitor dielectric layer 120 is provided with a first through-hole 400, the first through-hole 400 penetrating the capacitor dielectric layer 120 and exposing a portion of the surface of the first conductive layer 110; a second conductive layer 120; and a second conductive layer 120. Electrical layer 130, the second conductive layer 130 is located on the side of capacitor dielectric layer 120 away from the first conductive layer 110; the boundary of the second conductive layer 130 is recessed towards the center of the capacitor chip structure relative to the boundary of the first conductive layer 110; insulating layer 145 is located on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the insulating layer 145 also covers the sidewall of the second conductive layer 130, the side of capacitor dielectric layer 120 away from the first conductive layer 110, the sidewall of capacitor dielectric layer 120, and the sidewall of the first via 400; insulating layer 145 A second through-hole 150 and a third through-hole 160 are provided, penetrating the insulating layer 145. The second through-hole 150 exposes a portion of the surface of the second conductive layer 130. A first electrical connection structure sequentially includes a first UBM layer 170, a first copper-tin alloy layer 190, and a first tin layer 210. The first tin layer 210 encloses the first copper-tin alloy layer 190, and the first copper-tin alloy layer 190 encloses the first UBM layer 170. The central portion of the first UBM layer 170 is located within the second through-hole 150 and electrically connected to the second conductive layer 130. The edge portion of the first UBM layer 170... Located on the surface of insulating layer 145 away from glass substrate 100; a second electrical connection structure, sequentially including a second UBM layer 180, a second copper-tin alloy layer 200, and a second tin layer 220; the second tin layer 220 encloses the second copper-tin alloy layer 200, and the second copper-tin alloy layer 200 encloses the second UBM layer 180; the central portion of the second UBM layer 180 is located in the third via 160 and passes through the first via 400 and is electrically connected to the first conductive layer 110, and the edge portion of the second UBM layer 180 is located on the surface of insulating layer 145 away from glass substrate 100. The thickness of the first UBM layer 170 is greater than the thickness of the first copper-tin alloy layer 190, and the thickness of the first UBM layer 170 is greater than the thickness of the first tin layer 210; the thickness of the second UBM layer 180 is greater than the thickness of the second copper-tin alloy layer 200, and the thickness of the second UBM layer 180 is greater than the thickness of the first tin layer 220.

[0066] The capacitor chip structure provided in this disclosure has a first electrical connection structure and a second electrical connection structure located on the same surface of the capacitor chip structure, reducing the mounting difficulty of the capacitor chip structure and facilitating electrical connection with other electrical components. The first electrical connection structure sequentially includes a first UBM layer 170, a first copper-tin alloy layer 190, and a first tin layer 210; the second electrical connection structure sequentially includes a second UBM layer 180, a second copper-tin alloy layer 200, and a second tin layer 220. In the first electrical connection structure, the thickness of the first UBM layer 170 is greater than the thickness of the first copper-tin alloy layer 190, and the thickness of the first UBM layer 170 is greater than the thickness of the first tin layer 210, increasing the thickness, current carrying capacity, and heat dissipation capacity of the first electrical connection structure. In the second electrical connection structure, the thickness of the second UBM layer 180 is greater than the thickness of the second copper-tin alloy layer 200, and the thickness of the second UBM layer 180 is greater than the thickness of the first tin layer 220, increasing the thickness, current carrying capacity, and heat dissipation capacity of the second electrical connection structure. Furthermore, in both the first and second electrical connection structures, the layered structure of the tin layer enclosing the copper-tin alloy layer, and the copper-tin alloy layer enclosing the UBM layer, can reduce leakage current on the one hand, and increase the area of ​​the copper-tin alloy layer and the tin layer on the other hand, thereby improving heat dissipation capacity.

[0067] In this design, a glass substrate 100 is selected as the substrate, which provides greater structural strength compared to a silicon substrate. This eliminates the need for secondary packaging to enhance the structural strength of the capacitor chip, reducing packaging complexity and resulting in a better quality factor (Q value) for the capacitor chip structure. The capacitor dielectric layer 120 insulates the first conductive layer 110 and the second conductive layer 130. The first conductive layer 110 serves as the first electrode of the capacitor, acquiring electrical signals through the second electrical connection structure; the second conductive layer 130 serves as the second electrode of the capacitor, acquiring electrical signals through the first electrical connection structure. The boundary of the second conductive layer 130 is recessed towards the center of the capacitor chip structure relative to the boundary of the first conductive layer 110, so that the capacitor dielectric layer 120 covers the surface and sidewalls of the non-electrically connected portion of the first conductive layer 110 and the second electrical connection structure, achieving better electrical isolation between the first conductive layer 110 and the second conductive layer 130. The insulating layer 145 covers the surface and sidewalls of the capacitor dielectric layer 120 that are not covered by the second conductive layer 130. The insulating layer 145 also covers the surface and sidewalls of the non-electrically connected portion of the second conductive layer 130 and the first electrical connection structure, as well as the surface of the non-electrically connected portion of the first conductive layer 110 and the second electrical connection structure. The capacitor dielectric layer 120 and the insulating layer 145 serve as insulating encapsulation for the capacitor chip structure.

[0068] Optionally, the first conductive layer 110 comprises any one of polycrystalline silicon, Ti, Al, Cu, Cr, Mo, W, and TiW, or a stack of two or more of them. The capacitor dielectric layer 120 comprises any one of silicon oxide and silicon nitride, or a combination thereof. The second conductive layer 130 comprises any one of Ti, Al, Cu, Cr, Mo, W, and TiW, or a stack of two or more of them. Preferably, the surface material of the second conductive layer 130 is any one of Ti, Cr, and TiW, or a stack of two or more of them, which gives its surface good adhesion, facilitating good adhesion to materials attached to its surface and increasing the reliability of the structure.

[0069] Optionally, as shown in Figure 2, the thickness of the first UBM layer 170 is greater than or equal to 3.0 micrometers and less than or equal to 30 micrometers; the thickness of the first copper-tin alloy layer 190 is greater than or equal to 0.2 micrometers and less than or equal to 2.0 micrometers; and the thickness of the first tin layer 210 is greater than or equal to 0.5 micrometers and less than or equal to 3.0 micrometers. Specifically, the thickness of the first UBM layer 170 is greater than or equal to 3.0 micrometers and less than or equal to 30 micrometers, which is greater than the thickness of the first copper-tin alloy layer 190 and the first tin layer 210, giving it high current carrying capacity and heat dissipation capacity.

[0070] Optionally, as shown in Figure 2, the thickness of the second UBM layer 180 is greater than or equal to 3.0 micrometers and less than or equal to 30 micrometers; the thickness of the second copper-tin alloy layer 200 is greater than or equal to 0.2 micrometers and less than or equal to 2.0 micrometers; and the thickness of the second tin layer 220 is greater than or equal to 0.5 micrometers and less than or equal to 3.0 micrometers.

[0071] Specifically, the thickness of the second UBM layer 180 is greater than or equal to 3.0 micrometers and less than or equal to 30 micrometers, which is greater than the thickness of the second copper-tin alloy layer 200 and the second tin layer 220, giving it high current carrying capacity and heat dissipation capacity.

[0072] Optionally, as shown in Figure 2, the first UBM layer 170 sequentially includes a first bottom metal layer, a first intermediate alloy layer, and a first outer anti-oxidation layer, with the first bottom metal layer and the second conductive layer in contact; and / or, the second UBM layer 180 sequentially includes a second bottom metal layer, a second intermediate alloy layer, and a second outer anti-oxidation layer, with the second bottom metal layer and the first conductive layer in contact.

[0073] In this embodiment, both the first UBM layer 170 and the second UBM layer 180 comprise three layers. The first bottom metal layer enhances the adhesion between the first UBM layer 170 and the second conductive layer 130. The first intermediate alloy layer, made of Ni, Cu, Mo, or Pt, allows for complete adhesion to solder balls during high-temperature reflow. The first outer anti-oxidation layer protects the Ni, Cu, and other materials from oxidation. In the second UBM layer 180, the second bottom metal layer enhances the adhesion between the second UBM layer 180 and the first conductive layer 110. The second intermediate alloy layer, also made of Ni, Cu, Mo, or Pt, allows for complete adhesion to solder balls during high-temperature reflow. The second outer anti-oxidation layer protects the Ni, Cu, and other materials from oxidation.

[0074] Optionally, as shown in FIG2, the insulating layer 145 includes a passivation layer 135; the passivation layer 135 is located on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the passivation layer 135 also covers the sidewall of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110, the sidewall of the capacitor dielectric layer 120, and the sidewall of the first through hole 300.

[0075] Specifically, the passivation layer 135 covers the surface and sidewalls of the capacitor dielectric layer 120 that are not covered by the second conductive layer 130. The passivation layer 135 also covers the surface and sidewalls of the non-electrically connected portion of the second conductive layer 130 and the first electrical connection structure 302, as well as the surface of the non-electrically connected portion of the first conductive layer 110 and the second electrical connection structure 303. The capacitor dielectric layer 120 and the passivation layer 135 serve as insulating encapsulation for the capacitor chip structure. The passivation layer 135 comprises any one or a combination of silicon oxide and silicon nitride.

[0076] Optionally, as shown in Figure 2, the insulating layer 145 further includes a buffer layer 140. The buffer layer 140 is located on the side of the passivation layer 135 away from the second conductive layer 130. The buffer layer 140 also covers the sidewalls of the passivation layer 135 within the second via 150 and the third via 160, so that the capacitor dielectric layer 120, the passivation layer 135, and the buffer layer 140 provide insulating encapsulation for the capacitor chip structure. Furthermore, the buffer layer 140 can provide stress buffering during the use of the capacitor chip structure, thereby improving the reliability of the capacitor chip structure. Optionally, the buffer layer 140 includes organic materials such as polyimide.

[0077] The passivation layer 135 has a sub-via 300, exposing the second conductive layer 130. The passivation layer 135 also has a sub-via, which is connected to the first through-hole 400, exposing the first conductive layer 110.

[0078] Optionally, as shown in Figure 1, the cross-sectional shape of the capacitor chip structure parallel to the first surface includes two oppositely arranged first long sides and two oppositely arranged first short sides, the first long sides and the first short sides are arranged perpendicularly, and the length L1 of the first long side is greater than the length W1 of the first short side; as shown in Figure 2, the second through hole 150 is located at the first end of the capacitor chip structure, the third through hole 160 is located at the second end of the capacitor chip structure, and the direction from the first end of the capacitor chip structure to the second end of the capacitor chip structure is parallel to the first long side.

[0079] Specifically, the second through hole 150 and the third through hole 160 are located at both ends of the capacitor chip structure along the direction of the first long side, so that the first electrical connection structure and the second electrical connection structure are located at both ends of the capacitor chip structure along the direction of the first long side. This allows the distance between the first electrical connection structure and the second electrical connection structure to be set further, thereby better achieving electrical isolation between the first electrical connection structure and the second electrical connection structure.

[0080] Optionally, as shown in Figure 1, the cross-sectional shape of the first tin layer 210 on the first surface includes two oppositely arranged second long sides and two oppositely arranged second short sides. The second long sides and the first short sides are arranged in parallel, and the second short sides and the first long sides are arranged in parallel. The length W2 of the second long side is greater than the length L2 of the second short side; the length L2 of the second short side is less than one-third of the length L1 of the first long side, so as to maximize the area of ​​the first tin layer 210, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0081] Optionally, as shown in Figure 1, the length W2 of the second short side is greater than or equal to 10% of the length L1 of the first long side and less than or equal to 30% of the length L1 of the first long side; and / or, the length W2 of the second long side is greater than or equal to 40% of the length W1 of the first short side and less than or equal to 90% of the length W1 of the first short side, so as to maximize the area of ​​the first tin layer 210, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0082] Optionally, as shown in Figure 1, on one side of the first end of the capacitor chip structure, the distance d1 between the second long side and the first short side near the first end of the capacitor chip structure is greater than or equal to 15 micrometers and less than or equal to 40 micrometers; and / or, on one side of the first end of the capacitor chip structure, the shortest distance d2 between the second short side and the first long side is greater than or equal to 15 micrometers and less than or equal to 40 micrometers, so as to maximize the area of ​​the first tin layer 210, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0083] Optionally, as shown in Figure 1, the cross-sectional pattern of the second tin layer 220 on the first surface includes two oppositely arranged third long sides and two oppositely arranged third short sides. The third long sides and the first short sides are arranged in parallel, and the third short sides and the first long sides are arranged in parallel. The length W3 of the third long side is greater than the length L3 of the third short side, and the length L3 of the third short side is less than one-third of the length L1 of the first long side, so as to maximize the area of ​​the second tin layer 220, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0084] Optionally, as shown in Figure 1, the length of the third short side is greater than or equal to 10% of the length of the first long side and less than or equal to 30% of the length of the first long side; and / or, the length W3 of the third long side is greater than or equal to 40% of the length L3 of the first short side and less than or equal to 90% of the length of the first short side, so as to maximize the area of ​​the second tin layer 220, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0085] Optionally, as shown in Figure 1, on one side of the second end of the capacitor chip structure, the distance d3 between the third long side and the first short side near the second end of the capacitor chip structure is greater than or equal to 15 micrometers and less than or equal to 40 micrometers; and / or, on one side of the first end of the capacitor chip structure, the shortest distance d4 between the third short side and the first long side is greater than or equal to 15 micrometers and less than or equal to 40 micrometers, so as to maximize the area of ​​the second tin layer 220, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0086] Optionally, as shown in Figure 2, the boundary of the second conductive layer 130 is recessed inward from the boundary of the first conductive layer 110 toward the center of the capacitor chip structure by a value greater than or equal to 3 micrometers.

[0087] The boundary of the second conductive layer 130 is recessed inwards from the boundary of the first conductive layer 110 toward the center of the capacitor chip structure by a value greater than or equal to 3 micrometers. This provides more space for the insulating layer 145 covering the surface of the capacitor dielectric layer 120, so that the capacitor dielectric layer 120 can cover the surface and sidewalls of the non-electrically connected portion of the first conductive layer 110 and the second electrical connection structure, thereby achieving better electrical isolation between the first conductive layer 110 and the second conductive layer 130.

[0088] Figure 3 shows a plan view of a capacitor chip structure, with the location of section AA′ marked. Figure 4 is a cross-sectional schematic diagram of a capacitor chip structure.

[0089] The structural features of the capacitor chip structure of the present disclosure embodiment (Embodiment 2) are described in detail below with reference to Figures 3 and 4.

[0090] The differences between the capacitor chip structure of Embodiment 2 shown in Figures 3 and 4 and that of Embodiment 1 shown in Figures 1 and 2 are as follows:

[0091] 1) The capacitor chip structure also includes a third conductive layer 130b, which is disposed in the same layer as the second conductive layer 130; the third conductive layer 130b and the second conductive layer 130 are insulated from each other by an insulating layer 145; the central portion of the third conductive layer 130b is located in the first through hole 400 and is electrically connected to the first conductive layer 110, and the edge portion of the third conductive layer 130b is located on the side of the capacitor dielectric layer 120 away from the first conductive layer 110; the central portion of the second electrical connection structure is located in the third through hole 160 and is electrically connected to the first conductive layer 110 through the third conductive layer 130b.

[0092] The meaning of the third conductive layer 130b and the second conductive layer 130 being set in the same layer is that the third conductive layer 130b and the second conductive layer 130 are the same metal layer completed by an etching process.

[0093] 2) The insulating layer 145 includes a passivation layer 135; the passivation layer 135 is located on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the passivation layer 135 is also located on the side of the third conductive layer 130b away from the first conductive layer 110; the passivation layer 135 also covers the sidewall of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110, and a portion of the surface of the third conductive layer 130b away from the first conductive layer 110; the third conductive layer 130b and the second conductive layer 130 are insulated from each other by the passivation layer 135.

[0094] 3) The insulating layer 145 also includes a buffer layer 140, which is located on the side of the passivation layer 135 away from the second conductive layer 130 and the third conductive layer 130b. The buffer layer 140 also covers the sidewall of the passivation layer 135 in the second through hole 150 and the third through hole 160.

[0095] Figure 5 illustrates the process steps related to a disclosed embodiment of a capacitor chip structure manufacturing method, referred to as Embodiment 3. The manufacturing method of the capacitor chip structure shown in Figure 5 pertains to the capacitor chip structures shown in Figures 1 and 2. This manufacturing method includes:

[0096] S11: Obtain the glass substrate.

[0097] S12: Deposit the first conductive layer and pattern it by etching to form the lower electrode of the capacitor.

[0098] S13: Deposition medium layer.

[0099] S14: Deposit the second conductive layer and pattern it by etching to form the upper electrode of the capacitor.

[0100] S15: Deposit a passivation layer covering the surface of the second conductive layer and the surface of the dielectric layer; pattern the passivation layer and the dielectric layer, wherein the etching of the insulating layer forms a second via, exposing the second conductive layer at the bottom; etch the stack of the passivation layer and the dielectric layer to form a first via, exposing the first conductive layer at the bottom.

[0101] S16: Organic buffer layer pattern is formed by photolithography.

[0102] S17: A first UBM layer and a second UBM layer are formed above the third and fourth through holes using an electroplating process.

[0103] S18: A copper-tin alloy layer is formed on all exposed surfaces of the UBM layer, and a tin layer is formed on all exposed surfaces of the copper-tin alloy layer.

[0104] Figures 6 to 12 are schematic cross-sectional views of the various process steps related to the manufacturing method of the capacitor chip structure of this disclosure (Example 3). The following description, in conjunction with the accompanying drawings, provides a detailed explanation of each relevant process step.

[0105] As shown in Figure 6, glass substrate 100 is obtained.

[0106] As shown in Figure 7, a first conductive layer 110 is deposited and patterned by etching to form the lower electrode of the capacitor. The material can be selected from Ti, Al, Cu, Cr, Mo, W, and TiW or a stack of two or more of them.

[0107] As shown in Figure 8, the deposited dielectric layer 120 is a stack of any one or at least two of the following materials: silicon oxide, silicon nitride, strontium zirconate, barium titanate, and barium strontium titanate.

[0108] As shown in Figure 9, a second conductive layer 130 is deposited and patterned by etching to form the upper electrode of the capacitor. The material can be selected from Ti, Al, Cu, Cr, Mo, W, TiW, or a stack of two or more of these materials; preferably, the surface material of the second conductive layer 130 is Ti, Cr, or TiW, which have good adhesion to other materials, facilitating good adhesion with materials attached to its surface and increasing reliability.

[0109] As shown in Figure 10, a passivation layer 135 is deposited, which covers the surface of the second conductive layer 130 and the surface of the capacitor dielectric layer 120. The passivation layer 135 and the capacitor dielectric layer 120 are patterned and etched, wherein the etched insulating layer 135 forms a second via 300, exposing the second conductive layer 130 at the bottom. The stack of the passivation layer 135 and the capacitor dielectric layer 120 is etched to form a first via 400, exposing the first conductive layer 110 at the bottom. The material of the passivation layer 135 is silicon oxide, silicon nitride, or a combination of both.

[0110] It should be noted that the deposition of passivation layer 135 is an optional solution. Without passivation layer 135, the capacitor dielectric layer 120 is directly patterned and etched to form the first via 400, while the second via 300 does not exist.

[0111] As shown in Figure 11, an organic buffer layer 140 pattern is formed by photolithography. The material of the organic buffer layer is a photosensitive polyimide material that can be photolithographically processed. A third through-hole 150 and a fourth through-hole 160 are patterned above the first through-hole 400 and the second through-hole 300, and the second conductive layer 130 and the first conductive layer 110 are exposed at the bottom, respectively.

[0112] As shown in Figure 12, an electroplating process is used to form a first UBM layer 170 and a second UBM layer 180 above the third via 150 and the fourth via 160. The detailed process steps include: depositing an electroplated seed layer, the material of which is a Ti / Cu stack, using a PVD or vapor deposition process; photolithography to form the area pattern to be electroplated to form the UBM layer, the area to be electroplated is covered by photoresist, and the area not to be electroplated is covered by photoresist; electroplating Cu (stacked together with the electroplated seed layer, collectively referred to as UBM layers 170 and 180); removing the electroplated photoresist; and removing the electroplated seed layer outside the UBM area.

[0113] As shown in Figure 2, the process also includes forming a copper-tin alloy layer and a tin layer. Specifically, a first tin layer 210 encloses a first copper-tin alloy layer 190, and the first copper-tin alloy layer 190 encloses a first UBM layer 170. A second tin layer 220 encloses a second copper-tin alloy layer 200, and the second copper-tin alloy layer 200 encloses a second UBM layer 180.

[0114] Figure 13 illustrates the process steps related to a disclosed embodiment of a capacitor chip structure manufacturing method, referred to as Embodiment Four. The manufacturing method of the capacitor chip structure shown in Figure 13 pertains to the capacitor chip structures shown in Figures 3 and 4. This manufacturing method includes:

[0115] S21: Obtain the glass substrate.

[0116] S22: Deposit the first conductive layer and pattern it by etching to form the lower electrode of the capacitor.

[0117] S23: Deposit a dielectric layer and pattern it by etching to form a first via, exposing a first conductive layer at the bottom of the first via.

[0118] S24: Deposit the second and third conductive layers.

[0119] S25: Deposit a passivation layer covering the second conductive layer, the surface of the dielectric layer, and the surface of the dielectric layer; pattern the passivation layer to form two sub-vias, the first sub-via exposing the second conductive layer; the passivation layer is also provided with a second sub-via communicating with the first via, exposing the first conductive layer.

[0120] S26: An organic buffer layer pattern is formed through photolithography.

[0121] S27: A first UBM layer and a second UBM layer are formed above the third and fourth through holes using an electroplating process.

[0122] S28: A copper-tin alloy layer is formed on all exposed surfaces of the UBM layer, and a tin layer is formed on all exposed surfaces of the copper-tin alloy layer.

[0123] The capacitor chip structure shown in Figure 13 is manufactured based on the capacitor chip structures shown in Figures 3 and 4. The difference between the capacitor chip structure shown in Figure 5 and the capacitor chip structure shown in Figures 1 and 2 is that:

[0124] 1) The capacitor chip structure also includes a third conductive layer 130b, which is disposed in the same layer as the second conductive layer 130; the third conductive layer 130b and the second conductive layer 130 are insulated from each other by an insulating layer 145; the central portion of the third conductive layer 130b is located in the first through hole 400 and is electrically connected to the first conductive layer 110, and the edge portion of the third conductive layer 130b is located on the side of the capacitor dielectric layer 120 away from the first conductive layer 110; the central portion of the second electrical connection structure is located in the third through hole 160 and is electrically connected to the first conductive layer 110 through the third conductive layer 130b.

[0125] The meaning of the third conductive layer 130b and the second conductive layer 130 being set in the same layer is that the third conductive layer 130b and the second conductive layer 130 are the same metal layer completed by an etching process.

[0126] 2) The insulating layer 145 includes a passivation layer 135; the passivation layer 135 is located on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the passivation layer 135 is also located on the side of the third conductive layer 130b away from the first conductive layer 110; the passivation layer 135 also covers the sidewall of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110, and a portion of the surface of the third conductive layer 130b away from the first conductive layer 110; the third conductive layer 130b and the second conductive layer 130 are insulated from each other by the passivation layer 135.

[0127] 3) The insulating layer 145 also includes a buffer layer 140, which is located on the side of the passivation layer 135 away from the second conductive layer 130 and the third conductive layer 130b. The buffer layer 140 also covers the sidewall of the passivation layer 135 in the second through hole 150 and the third through hole 160.

[0128] Figures 14 to 18 show schematic cross-sectional views of the various process steps related to S23-S28 in the manufacturing method of the capacitor chip structure of this disclosure (Example 4). The following description, in conjunction with the accompanying drawings, details each of the relevant process steps. S21-S22 can be referenced to the schematic cross-sectional views of the various process steps related to S11-S12.

[0129] As shown in Figure 14, a dielectric layer 120 is deposited and patterned by etching to form a first via 400, and a first conductive layer 110 is exposed at the bottom of the first via 400. The dielectric layer 120 is made of any one or a combination of at least two of silicon oxide, silicon nitride, strontium zirconate, barium titanate, and barium strontium titanate.

[0130] As shown in Figure 15, a second conductive layer 130 and a third conductive layer 130b are deposited. The second conductive layer 130 and the third conductive layer 130b are two parts of the same conductive layer after patterning. The second conductive layer 130 is the upper electrode of the capacitor; the third conductive layer 130b is connected to the first conductive layer 110 through the first through-hole 400 and is part of the electrical connection of the lower electrode of the capacitor to the outside. The material of the second conductive layer can be Ti, Al, Cu, Cr, Mo, W, TiW, or a stack of two or more of them; preferably, the surface material of the second conductive layer is Ti, Cr, or TiW, which have good adhesion to other materials, which is beneficial to the good adhesion of the material attached to its surface and increases reliability.

[0131] As shown in Figure 16, a passivation layer 135 is deposited, covering the surface of the second conductive layer 130 and the surface of the dielectric layer 120. The passivation layer 135 is patterned and etched to form two sub-vias. The first sub-via 300 exposes the second conductive layer 130. The passivation layer 135 also has a second sub-via 300b, which communicates with the first via 400, exposing the first conductive layer 110.

[0132] It should be noted that the deposition of passivation layer 135 is optional. Without passivation layer 135, this process step does not exist, and the two sub-vias of passivation layer 135 also do not exist.

[0133] As shown in Figure 17, an organic buffer layer 140 pattern is formed by photolithography. The material of the organic buffer layer is a photosensitive polyimide material that can be photolithographically processed. The pattern forms a third through-hole 150 and a fourth through-hole 160, and the bottom exposes a first portion 130a of the second conductive layer 130 and a portion of the third conductive layer 130b, respectively.

[0134] As shown in Figure 18, an electroplating process is used to form a first UBM layer 170 and a second UBM layer 180 above the third via 150 and the fourth via 160. The detailed process steps include: depositing an electroplated seed layer, the material of which is a Ti / Cu stack, using a PVD or vapor deposition process; photolithography to form the area pattern to be electroplated to form the UBM layer, the area to be electroplated is covered by photoresist, and the area not to be electroplated is covered by photoresist; electroplating Cu (stacked together with the electroplated seed layer, collectively referred to as UBM layers 170 and 180); removing the electroplated photoresist; and removing the electroplated seed layer outside the UBM area.

[0135] As shown in Figure 4, the process also includes forming a copper-tin alloy layer and a tin layer. Specifically, a first tin layer 210 encloses a first copper-tin alloy layer 190, and the first copper-tin alloy layer 190 encloses a first UBM layer 170. A second tin layer 220 encloses a second copper-tin alloy layer 200, and the second copper-tin alloy layer 200 encloses a second UBM layer 180.

[0136] Optionally, in this embodiment of the disclosure, the glass substrate 100 is a mother plate of the glass substrate.

[0137] The planar dimensions of the glass substrate motherboard include any one of 550*650mm, 680*880mm, 730*920mm, 1100*1300mm, and 1300*1500mm. These planar dimensions are used in display panel manufacturing. Specifically, 550*650mm represents the planar dimension of a 3rd generation display panel production line, 680*880mm represents a 3.5th generation line, 730*920mm represents a 4th or 4.5th generation line, 1100*1300mm represents a 5th generation line, and 1300*1500mm represents a 5.5th generation line.

[0138] Optionally, the mother plate of the glass substrate is cut from the dicing channel to cut into N glass substrates 100, where the number of N is greater than or equal to 4.02 million and less than or equal to 21.94 million. Specifically, the planar dimensions of the display panel are as follows: 550*650mm is the planar dimension of the 3rd generation line, and the glass substrate mother plate is cut from the cutting channel to form 4.02 million glass substrates 100; 680*880mm is the planar dimension of the display panel 3.5th generation line, and the glass substrate mother plate is cut from the cutting channel to form 6.73 million glass substrates 100; 730*920mm is the planar dimension of the display panel 4th or 4.5th generation line, and the glass substrate mother plate is cut from the cutting channel to form 7.56 million glass substrates 100; 1100*1300mm is the planar dimension of the display panel 5th generation line, and the glass substrate mother plate is cut from the cutting channel to form 16.09 million glass substrates 100; 1300*1500mm is the planar dimension of the display panel 5.5th generation line, and the glass substrate mother plate is cut from the cutting channel to form 21.94 million glass substrates 100.

[0139] A first conductive layer 110 is deposited on the first surface of a glass substrate, and multiple spaced first conductive layers 110 are formed by a patterned etching process. The first conductive layer 110 serves as the lower electrode of the capacitor. Multiple spaced first conductive layers 110 are formed on the first surface of the glass substrate, and a dicing line is formed between two adjacent first conductive layers 110.

[0140] The mother plate of the glass substrate is cut from the dicing channel to form multiple glass substrates 100. In this step, the large-area glass substrate mother plate is cut into several small-area glass substrates 100 so that subsequent electroplating processes can be carried out on the small-area glass substrates 100. The cut small-area glass substrates 100 can be rectangular, square, or circular, and their size can be determined according to the size requirements of the electroplating process production line for the glass substrates 100.

[0141] The reason for cutting the large-area glass substrate motherboard into smaller glass substrates 100 is that the required electroplating process exists in semiconductor-related wafer fabs, packaging plants, or printed circuit board (PCB) manufacturing plants. These plants typically use substrates much smaller than those used in the display panel industry. While it's possible to customize electroplating equipment suitable for large-area substrates, this would require additional equipment investment and corresponding process development costs. However, a key feature of this case is the use of mature equipment and processes to cut the large-area glass substrate motherboard into smaller glass substrates 100 and then continue processing them until the capacitor manufacturing is complete.

[0142] It should be noted that the above are only specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A capacitor chip structure, characterized in that, include: A glass substrate includes a first surface and a second surface disposed opposite to each other; a first conductive layer is located on the first surface of the glass substrate. A capacitor dielectric layer is located on the side of the first conductive layer away from the glass substrate; the capacitor dielectric layer also covers the sidewall of the first conductive layer, and the capacitor dielectric layer has a first through-hole that penetrates the capacitor dielectric layer and exposes a portion of the surface of the first conductive layer; a second conductive layer is located on the side of the capacitor dielectric layer away from the first conductive layer; the boundary of the second conductive layer is recessed towards the center of the capacitor chip structure relative to the boundary of the first conductive layer; an insulating layer is located on the side of the second conductive layer away from the capacitor dielectric layer, and the insulating layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer, and the sidewall of the first through-hole; the insulating layer has a second through-hole and a third through-hole that penetrate the insulating layer, and the second through-hole exposes a portion of the surface of the second conductive layer; a first electrical connection structure includes, in sequence, a first UBM layer, a first copper-tin alloy layer, and a first tin layer; The first tin layer encapsulates the first copper-tin alloy layer, which in turn encapsulates the first UBM layer. The central portion of the first UBM layer is located within the second via and electrically connected to the second conductive layer. The edge portion of the first UBM layer is located on the surface of the insulating layer away from the glass substrate. A second electrical connection structure sequentially includes a second UBM layer, a second copper-tin alloy layer, and a second tin layer. The second tin layer encapsulates the second copper-tin alloy layer, which in turn encapsulates the second UBM layer. The central portion of the second UBM layer is located within the third via and passes through the first via, connecting to the first conductive layer. The edge portion of the second UBM layer is located on the surface of the insulating layer away from the glass substrate. The thickness of the first UBM layer is greater than the thickness of the first copper-tin alloy layer, and the thickness of the first UBM layer is greater than the thickness of the first tin layer. The thickness of the second UBM layer is greater than the thickness of the second copper-tin alloy layer, and the thickness of the second UBM layer is greater than the thickness of the second tin layer.

2. The capacitor chip structure according to claim 1, characterized in that, The thickness of the first UBM layer is greater than or equal to 3.0 micrometers and less than or equal to 30 micrometers; the thickness of the first copper-tin alloy layer is greater than or equal to 0.2 micrometers and less than or equal to 2.0 micrometers; the thickness of the first tin layer is greater than or equal to 0.5 micrometers and less than or equal to 3.0 micrometers.

3. The capacitor chip structure according to claim 1, characterized in that, The thickness of the second UBM layer is greater than or equal to 3.0 micrometers and less than or equal to 30 micrometers; the thickness of the second copper-tin alloy layer is greater than or equal to 0.2 micrometers and less than or equal to 2.0 micrometers; the thickness of the second tin layer is greater than or equal to 0.5 micrometers and less than or equal to 3.0 micrometers.

4. The capacitor chip structure according to claim 1, characterized in that, The first UBM layer sequentially includes a first bottom metal layer, a first intermediate alloy layer, and a first outer anti-oxidation layer, wherein the first bottom metal layer and the second conductive layer are in contact; and / or, the second UBM layer sequentially includes a second bottom metal layer, a second intermediate alloy layer, and a second outer anti-oxidation layer, wherein the second bottom metal layer and the first conductive layer are in contact.

5. The capacitor chip structure according to claim 1, characterized in that, It also includes a third conductive layer, which is disposed in the same layer as the second conductive layer; the third conductive layer and the second conductive layer are insulated from each other by the insulating layer; the central portion of the third conductive layer is located in the first through hole and is electrically connected to the first conductive layer, and the edge portion of the third conductive layer is located on the side of the capacitor dielectric layer away from the first conductive layer; the central portion of the second electrical connection structure is located in the third through hole and is electrically connected to the first conductive layer through the third conductive layer.

6. The capacitor chip structure according to claim 1, characterized in that, The insulating layer includes a passivation layer; the passivation layer is located on the side of the second conductive layer away from the capacitor dielectric layer, and the passivation layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer, and the sidewall of the first through hole.

7. The capacitor chip structure according to claim 6, characterized in that, The insulating layer further includes a buffer layer located on the side of the passivation layer away from the second conductive layer, and the buffer layer also covers the sidewall of the passivation layer within the second via and the third via.

8. The capacitor chip structure according to claim 5, characterized in that, The insulating layer includes a passivation layer; the passivation layer is located on the side of the second conductive layer away from the capacitor dielectric layer, and the passivation layer is also located on the side of the third conductive layer away from the first conductive layer; the passivation layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer, and a portion of the surface of the third conductive layer away from the first conductive layer; the third conductive layer and the second conductive layer are insulated from each other by the passivation layer.

9. The capacitor chip structure according to claim 8, characterized in that, The insulating layer further includes a buffer layer located on the side of the passivation layer away from the second conductive layer and the third conductive layer, and the buffer layer also covers the sidewall of the passivation layer within the second via and the third via.

10. The capacitor chip structure according to claim 1, characterized in that, The capacitor chip structure has a cross-sectional shape parallel to the first surface, including two oppositely arranged first long sides and two oppositely arranged first short sides, the first long sides and the first short sides are arranged perpendicularly, and the length of the first long side is greater than the length of the first short side; the second through hole is located at the first end of the capacitor chip structure, the third through hole is located at the second end of the capacitor chip structure, and the direction from the first end of the capacitor chip structure to the second end of the capacitor chip structure is parallel to the first long side.

11. The capacitor chip structure according to claim 10, characterized in that, The cross-sectional pattern of the first tin layer on the first surface includes two oppositely arranged second long sides and two oppositely arranged second short sides. The second long sides and the first short sides are parallel to each other, and the second short sides and the first long sides are parallel to each other. The length of the second long side is greater than the length of the second short side, and the length of the second short side is less than one-third of the length of the first long side.

12. The capacitor chip structure according to claim 11, characterized in that, The length of the second short side is greater than or equal to 10% of the length of the first long side and less than or equal to 30% of the length of the first long side; and / or, the length of the second long side is greater than or equal to 40% of the length of the first short side and less than or equal to 90% of the length of the first short side.

13. The capacitor chip structure according to claim 11, characterized in that, On one side of the first end of the capacitor chip structure, the distance between the second long side and the first short side near the first end of the capacitor chip structure is greater than or equal to 15 micrometers and less than or equal to 40 micrometers. And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the second short side and the first long side is greater than or equal to 15 micrometers and less than or equal to 40 micrometers.

14. The capacitor chip structure according to claim 10, characterized in that, The cross-sectional pattern of the second tin layer on the first surface includes two oppositely arranged third long sides and two oppositely arranged third short sides. The third long sides and the first short sides are parallel to each other, and the third short sides and the first long sides are parallel to each other. The length of the third long side is greater than the length of the third short side, and the length of the third short side is less than one-third of the length of the first long side.

15. The capacitor chip structure according to claim 14, characterized in that, The length of the third short side is greater than or equal to 10% of the length of the first long side and less than or equal to 30% of the length of the first long side; and / or, the length of the third long side is greater than or equal to 40% of the length of the first short side and less than or equal to 90% of the length of the first short side.

16. The capacitor chip structure according to claim 14, characterized in that, On one side of the second end of the capacitor chip structure, the distance between the third long side and the first short side near the second end of the capacitor chip structure is greater than or equal to 15 micrometers and less than or equal to 40 micrometers; and / or, on one side of the first end of the capacitor chip structure, the shortest distance between the third short side and the first long side is greater than or equal to 15 micrometers and less than or equal to 40 micrometers.

17. The capacitor chip structure according to claim 1, characterized in that, The boundary of the second conductive layer is recessed inwards from the boundary of the first conductive layer toward the center of the capacitor chip structure by a value greater than or equal to 3 micrometers.

Images