Packaging structure for photoelectric co-packaging of silicon optical chip

Abstract

The utility model relates to the technical field of silicon optical chips, and discloses a packaging structure for photoelectric co-packaging of a silicon optical chip, which comprises a flexible substrate, the silicon optical chip is movably arranged above the flexible substrate, a connecting concave point is fixedly arranged above the flexible substrate, a bendable area is fixedly arranged on the outer side of the flexible substrate, and the bendable area is fixedly connected with the silicon optical chip. A silicon optical chip is fixedly arranged on the flexible substrate, a passivation layer is fixedly arranged on the outer side of the silicon optical chip, heat-conducting silicone grease is fixedly arranged above the silicon optical chip, a cooling fin is movably arranged above the heat-conducting silicone grease, an electromagnetic shielding layer is fixedly arranged above the flexible substrate and the silicon optical chip, and a packaging shell is fixedly arranged on the outer side of the electromagnetic shielding layer. According to the packaging structure for photoelectric co-packaging of the silicon optical chip, the bendable area is arranged, the hollowed-out or wave-shaped structural design is adopted, the bendable angle range is 0-180 degrees, the packaging structure can flexibly adapt to different installation environments and wiring requirements, and the application scene of the silicon optical chip is greatly expanded.

Description

A packaging structure for optoelectronic co-packaging of silicon photonic chips Technical Field

[0001] This utility model relates to the field of silicon photonics chip technology, specifically a packaging structure for optoelectronic co-packaging of silicon photonics chips. Background Technology

[0002] With the rapid development of information technology, silicon photonics chips have been widely used in optical communication, data centers and other fields due to their advantages such as high speed and low power consumption. However, existing silicon photonics chip packaging structures have many problems in practical applications. For example, traditional packaging structures are difficult to adapt to complex and ever-changing installation environments and wiring requirements, which limits the use of silicon photonics chips in some special scenarios; poor heat dissipation performance causes silicon photonics chips to degrade or even be damaged due to excessive temperature during long-term operation; the electromagnetic shielding effect is not ideal, and external electromagnetic interference can easily affect the normal operation of silicon photonics chips; the packaging structure is inconvenient to disassemble and assemble, which is not conducive to later maintenance and repair. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] The purpose of this invention is to provide a packaging structure for optoelectronic co-packaging of silicon photonic chips, so as to solve the problem mentioned in the background art that traditional silicon photonic chip packaging structures are difficult to adapt to complex environments.

[0005] (II) Technical Solution

[0006] To achieve the above objectives, this utility model provides the following technical solution: a packaging structure for optoelectronic co-packaging of silicon photonic chips, comprising a flexible substrate, a silicon photonic chip movably disposed on the top of the flexible substrate, a connection recess fixedly disposed on the top of the flexible substrate, a bendable area fixedly disposed on the outer side of the flexible substrate, a passivation layer fixedly disposed on the outer side of the silicon photonic chip, thermal grease fixedly disposed on the top of the silicon photonic chip, a heat sink movably disposed on the top of the thermal grease, an electromagnetic shielding layer fixedly disposed on the top of the flexible substrate and the silicon photonic chip, a packaging shell fixedly disposed on the outer side of the electromagnetic shielding layer, and heat dissipation holes fixedly disposed on the top and sides of the packaging shell.

[0007] Preferably, the silicon photonics chip is electrically connected to the connection recess area of ​​the flexible substrate by flip-chip bonding with bumps.

[0008] Preferably, the bendable area adopts a hollow or wavy structure design, and its bendable angle range is 0-180 degrees to adapt to different installation environments and wiring requirements.

[0009] Preferably, the passivation layer is made of silicon dioxide or silicon nitride, with a thickness ranging from 0.1 to 1 micrometer, and is used to protect the surface of the silicon photonic chip from external environmental corrosion and electrical interference.

[0010] Preferably, the surface of the heat sink is provided with multiple heat dissipation fins, and the heat sink is in close contact with the thermal grease to enhance the heat dissipation effect of the silicon photonics chip.

[0011] Preferably, the electromagnetic shielding layer is made of metal woven mesh or conductive polymer material, which can effectively shield external electromagnetic interference while allowing heat dissipation airflow to pass through.

[0012] Preferably, the outer casing is made of plastic and is connected to the electromagnetic shielding layer by a snap-fit, making it easy to disassemble and install.

[0013] Compared with the prior art, the beneficial effects of this utility model are:

[0014] 1. The packaging structure for the optoelectronic co-packaging of the silicon photonics chip, by setting a bendable area and adopting a hollow or wave-shaped structure design, has a bendable angle range of 0-180 degrees, which can flexibly adapt to different installation environments and wiring requirements, greatly expanding the application scenarios of silicon photonics chips.

[0015] 2. The packaging structure for the optoelectronic co-packaging of the silicon photonics chip, by placing thermal grease and a heat sink with heat dissipation fins on top of the silicon photonics chip, and with the heat sink and thermal grease in close contact, can quickly and effectively dissipate the heat generated by the silicon photonics chip, significantly enhancing the heat dissipation effect of the silicon photonics chip and ensuring the stability and reliability of the chip under long-term operation.

[0016] 3. The packaging structure for the optoelectronic co-packaging of the silicon photonics chip, by using an electromagnetic shielding layer made of metal braided mesh or conductive polymer material, can effectively shield external electromagnetic interference without affecting the heat dissipation airflow, providing a good electromagnetic environment for the silicon photonics chip, ensuring its normal operation, and improving the accuracy and stability of data transmission.

[0017] 4. The packaging structure for the optoelectronic co-packaging of the silicon photonics chip uses a plastic outer shell and is connected to the electromagnetic shielding layer by a snap-fit, which makes the outer shell easy to disassemble and install, facilitates the maintenance and repair of the silicon photonics chip, reduces maintenance costs, and improves maintenance efficiency. Attached Figure Description

[0018] Figure 1 is a three-dimensional structural schematic diagram of this utility model;

[0019] Figure 2 is a three-dimensional structural schematic diagram of this utility model;

[0020] Figure 3 is a schematic diagram of the three-dimensional structure of the silicon photonics chip of this utility model;

[0021] Figure 4 is a schematic diagram of the three-dimensional structure of the flexible substrate of this utility model.

[0022] In the diagram: 1. Flexible substrate; 2. Silicon photonic chip; 3. Connection recess; 4. Bendable area; 5. Passivation layer; 6. Thermal grease; 7. Heat sink; 8. Electromagnetic shielding layer; 9. Encapsulation shell; 10. Heat dissipation hole. Detailed Implementation

[0023] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0024] Please refer to Figures 1-4. This utility model provides a technical solution: a packaging structure for optoelectronic co-packaging of silicon photonic chips, including a flexible substrate 1, a silicon photonic chip 2 movably disposed on the top of the flexible substrate 1, a connection recess 3 fixedly disposed on the top of the flexible substrate 1, a bendable region 4 fixedly disposed on the outer side of the flexible substrate 1, a passivation layer 5 fixedly disposed on the outer side of the silicon photonic chip 2, a thermally conductive silicone grease 6 fixedly disposed on the top of the silicon photonic chip 2, a heat sink 7 movably disposed on the top of the thermally conductive silicone grease 6, an electromagnetic shielding layer 8 fixedly disposed on the top of the flexible substrate 1 and the silicon photonic chip 2, a packaging shell 9 fixedly disposed on the outer side of the electromagnetic shielding layer 8, and heat dissipation holes 10 fixedly disposed on the top and sides of the packaging shell 9. The silicon photonics chip 2 is flip-chip mounted on the connection recess 3 area of ​​the flexible substrate 1 through bumps, achieving a stable electrical connection and ensuring efficient signal transmission. When it needs to be installed in different environments, the bendable area 4 can be bent from 0 to 180 degrees according to the actual situation to adapt to complex wiring and installation space requirements. The silicon photonics chip 2 generates heat during operation. The thermal grease 6 can quickly conduct the heat generated by the chip to the heat sink 7. The heat dissipation fins on the surface of the heat sink 7 increase the heat dissipation area and accelerate the dissipation of heat. At the same time, the heat dissipation holes 10 on the top and sides of the package shell 9 can promote air circulation and further enhance the heat dissipation effect, ensuring that the silicon photonics chip 2 operates at a suitable temperature.

[0025] The silicon photonic chip 2 is electrically connected to the connection recess 3 area of ​​the flexible substrate 1 via bump flip-chip bonding. The bendable area 4 adopts a hollow or wave-shaped structure design, with a bendable angle range of 0-180 degrees to adapt to different installation environments and wiring requirements. The passivation layer 5 is made of silicon dioxide or silicon nitride, with a thickness ranging from 0.1 to 1 micrometer, used to protect the surface of the silicon photonic chip 2 from external environmental corrosion and electrical interference. The surface of the heat sink 7 is provided with multiple heat dissipation fins, and the heat sink 7 is tightly attached to the thermal grease 6 to enhance the heat dissipation effect of the silicon photonic chip 2. The electromagnetic shielding layer 8 is made of metal braided mesh or conductive polymer material, which can effectively shield external electromagnetic interference while allowing heat dissipation airflow. The encapsulation shell 9 adopts... Made of plastic and connected to the electromagnetic shielding layer via snap-fit, the package 9 is easy to disassemble and install. External electromagnetic interference can affect the operation of the silicon photonic chip 2. The electromagnetic shielding layer 8, made of metal braided mesh or conductive polymer material, can effectively block external electromagnetic interference, creating a stable electromagnetic environment for the silicon photonic chip 2, enabling it to work normally and stably. When maintenance or repair of the silicon photonic chip 2 is required, the package 9 can be easily removed by snap-fit, as it is connected to the electromagnetic shielding layer. This allows for convenient and quick inspection, repair, and replacement of internal components such as the silicon photonic chip 2. After maintenance, the package 9 can be reinstalled via snap-fit. The operation is simple and saves time and labor costs.

[0026] Working Principle: In actual use, the silicon photonics chip 2 is flip-chip mounted on the connection recess 3 area of ​​the flexible substrate 1 through bumps, achieving a stable electrical connection and ensuring efficient signal transmission. When it needs to be installed in different environments, the bendable area 4 can be bent from 0-180 degrees according to the actual situation to adapt to complex wiring and installation space requirements. The silicon photonics chip 2 generates heat during operation. The thermal grease 6 can quickly conduct the heat generated by the chip to the heat sink 7. The heat dissipation fins on the surface of the heat sink 7 increase the heat dissipation area and accelerate heat dissipation. At the same time, the heat dissipation holes 10 on the top and sides of the package shell 9 can promote air circulation and further enhance the heat dissipation effect, ensuring the silicon photonics chip's performance. Chip 2 operates at a suitable temperature. External electromagnetic interference can affect the operation of silicon photonics chip 2. The electromagnetic shielding layer 8, made of metal braided mesh or conductive polymer material, can effectively block external electromagnetic interference, creating a stable electromagnetic environment for silicon photonics chip 2, enabling it to operate normally and stably. When maintenance or repair of silicon photonics chip 2 is required, since the encapsulation shell 9 is connected to the electromagnetic shielding layer by a snap-fit, the encapsulation shell 9 can be easily removed with simple operation, making it convenient and quick to inspect, repair and replace the internal silicon photonics chip 2 and other components. After maintenance, the encapsulation shell 9 can be reinstalled by snap-fit. The operation is simple and saves time and labor costs.

[0027] Finally, it should be noted that the above content is only used to illustrate the technical solution of this utility model, and is not intended to limit the scope of protection of this utility model. Simple modifications or equivalent substitutions made by those skilled in the art to the technical solution of this utility model do not depart from the essence and scope of the technical solution of this utility model.

Claims

1. A packaging structure for opto-electric co-packaging of a silicon photonic chip, comprising a flexible substrate (1), characterized in that: A silicon photonic chip (2) is movably disposed on the top of the flexible substrate (1). A connection recess (3) is fixedly disposed on the top of the flexible substrate (1). A bendable area (4) is fixedly disposed on the outer side of the flexible substrate (1). A passivation layer (5) is fixedly disposed on the outer side of the silicon photonic chip (2). A thermal grease (6) is fixedly disposed on the top of the silicon photonic chip (2). A heat sink (7) is movably disposed on the top of the thermal grease (6). An electromagnetic shielding layer (8) is fixedly disposed on the top of the flexible substrate (1) and the silicon photonic chip (2). An encapsulation shell (9) is fixedly disposed on the outer side of the electromagnetic shielding layer (8). Heat dissipation holes (10) are fixedly disposed on the top and sides of the encapsulation shell (9).

2. The packaging structure for optoelectronic co-packaging of silicon photonic chips according to claim 1, characterized in that: The silicon photonic chip (2) is flip-mounted onto the connection recess (3) region of the flexible substrate (1) via bumps.

3. The packaging structure for optoelectronic co-packaging of silicon photonic chips according to claim 2, characterized in that: The bendable area (4) adopts a hollow or wave-shaped structure design, and its bendable angle range is 0-180 degrees.

4. The packaging structure for optoelectronic co-packaging of silicon photonic chips according to claim 3, wherein: The passivation layer (5) is made of silicon dioxide or silicon nitride and has a thickness ranging from 0.1 to 1 micrometer.

5. The packaging structure for optoelectronic co-packaging of silicon photonic chips according to claim 4, wherein: The surface of the heat sink (7) is provided with multiple heat dissipation fins, and the heat sink (7) is in close contact with the thermal grease (6).

6. The packaging structure for optoelectronic co-packaging of silicon photonic chips according to claim 1, characterized in that: The electromagnetic shielding layer (8) is made of metal woven mesh or conductive polymer material.

7. The packaging structure for optoelectronic co-packaging of silicon photonic chips according to claim 1, wherein: The encapsulation shell (9) is made of plastic and is connected to the electromagnetic shielding layer by a snap fastener.

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