Semiconductor die package

Abstract

In a semiconductor die package, a first integrated circuit die and a second integrated circuit die are directly bonded together in a vertical arrangement. The smaller substantial size of the first integrated circuit die enables a plurality of inactive dies to be placed over the second integrated circuit die in a non-first integrated circuit die footprint. For different attributes of different regions of the second integrated circuit die, a plurality of inactive dies can customize the inactive die and different heat distributions of different regions of the second integrated circuit die are included. In the method, a plurality of inactive dies included in the semiconductor die package may increase thermal stability of the semiconductor die package, which may extend operational lifetime of the integrated circuit die, may reduce failure feasibility of the integrated circuit die, and / or may increase overall reliability of the semiconductor die.

Description

Technical Field

[0001] This disclosure relates to a semiconductor die package. Background Technology

[0002] Semiconductor die packages may include multiple integrated circuit dies that provide various functions. These integrated circuit dies include, for example, system-on-chip (SoC), dynamic random access memory (DRAM) integrated circuit dies, logic integrated circuit dies, and / or high bandwidth memory (HBM) integrated circuit dies. Some semiconductor die packages include through-hole modules that allow the integrated circuit dies to be arranged laterally on the modules. In some semiconductor die packages, the integrated circuit dies are arranged vertically using three-dimensional packaging techniques, such as direct bonding. Utility Model Content

[0003] According to some embodiments disclosed herein, a semiconductor die package includes a first active integrated circuit die, a second active integrated circuit die on a first portion of the first active integrated circuit die, a first passive die on a second portion of the first active integrated circuit die, and a second passive die on a third portion of the first active integrated circuit die. The second active integrated circuit die, the first passive integrated circuit die, and the second passive integrated circuit die are located on the same side of the first integrated circuit die.

[0004] According to some embodiments disclosed herein, a semiconductor package includes a first active integrated circuit die, a second active integrated circuit die laterally adjacent to the first active integrated circuit die, a third active integrated circuit die laterally adjacent to both the first and second active integrated circuit dies, a fourth active integrated circuit die vertically arranged on the first active integrated circuit die, a first non-active die vertically arranged on the second active integrated circuit die, and a second non-active die vertically arranged on the third active integrated circuit die.

[0005] According to some embodiments disclosed herein, a semiconductor die package includes a first active integrated circuit die, a second active integrated circuit die, a third active integrated circuit die, a fourth active integrated circuit die, a first non-active die, and a second non-active die. The second active integrated circuit die is laterally adjacent to the first active integrated circuit die. The third active integrated circuit die is laterally adjacent to the second active integrated circuit die. The fourth active integrated circuit die is vertically arranged on the first active integrated circuit die. The first non-active die is vertically arranged on the second active integrated circuit die, and the second non-active die is vertically arranged on the third active integrated circuit die, wherein a portion of the second non-active die is also located on and vertically arranged on the second active integrated circuit die. Attached Figure Description

[0006] The aspects disclosed herein are well understood by reading the accompanying illustrations in the detailed description that follows. It is worth noting that, in accordance with standard industry practice, most features are not drawn to scale. In fact, for clarity of discussion, the dimensions of most features may be arbitrarily increased or decreased.

[0007] Figures 1A-1C The accompanying drawings are examples of semiconductor die packages described herein;

[0008] Figures 2A-2I The accompanying figure is an example of a top-view layout of a non-active die in a semiconductor die package described herein;

[0009] Figures 3A-3T The accompanying drawings are of an example embodiment of the semiconductor die package described herein;

[0010] Figures 4A-4E The accompanying figure shows an example of a semiconductor die package described herein;

[0011] Figures 5A-5E The accompanying figure shows an example of a semiconductor die package described herein;

[0012] Figures 6A-6F The accompanying figure is an example of a top-view layout of a semiconductor die package described herein;

[0013] Figure 7 This is a flowchart of an example process relating to the formation of the semiconductor die package described herein;

[0014] Figure 8 This is a flowchart of an example process relating to the formation of the semiconductor die package described herein.

[0015] [Symbol Explanation]

[0016] 100,200,202,204,206,208,210,212,214,216,300,400,500,600,612,614,616,618,620: Example

[0017] 102, 402, 502, 602: Semiconductor die package

[0018] 104, 106, 404, 406, 504, 506, 604, 604a, 604b, 604c, 606: Active integrated circuit chips

[0019] 104a, 104b, 104c, 104d: outside

[0020] 108a, 108b, 108c, 408a, 408b, 508a, 508b, 608a, 608b, 608c: Non-active grains

[0021] 110, 610: Gap

[0022] 112,152,302,306,412,452: Bonding layers

[0023] 114a, 114b: Dielectric filling layer

[0024] 116, 118, 120, 122, 124, 142a, 142b, 144a, 144b: Passivation layers

[0025] 126a,126b:Substrate

[0026] 128a, 128b, 134a, 134b: Inner dielectric layers

[0027] 130a, 130b: Integrated circuit devices

[0028] 132a, 132b: Contacts

[0029] 136a, 136b: Etching stop layers

[0030] 138a, 138b: Conductive structure

[0031] 140a, 140b: Sealing ring structure

[0032] 146a, 146b, 148a, 148b: Metal pads

[0033] 150a, 150b, 154, 454a, 454b, 554a: solder pads

[0034] 156: Grain-to-grain incorporation

[0035] 158: Connection Structure

[0036] 160, 162: Partial

[0037] 304: Carrier substrate

[0038] 414a, 414b, 514b: Dielectric filling layer

[0039] 460, 462: Partial

[0040] 464: Semiconductor Structure

[0041] 466,474,566,574: Trench structure

[0042] 468,476,568,576: Channel structure

[0043] 470, 478: Padding

[0044] 472: Dielectric Structure

[0045] 480, 482: Opening

[0046] 700, 800: Process

[0047] Blocks 710, 720, 730, 740, 750, 810, 820, 830, 840, 850, 860:

[0048] D1, D2, D3, D4, D5, D6, D7, D8, D9, D10: Dimensions Detailed Implementation

[0049] The following disclosure provides many different implementations or examples for performing the various main features provided. Specific components and configuration examples are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature on or over a second feature described may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed within the first and second features so that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances. This repetition is for simplification or clarity and does not specify the relationship between the various implementations and / or configurations discussed.

[0050] Furthermore, spatially related terms, such as "below," "lower part," "above," and "upper part," are used here to simply describe the relationship of one element or feature to other elements or features illustrated in the diagram. Spatially related terms are intended to include the orientation of different devices in use or operation. Instruments may have other orientations (rotated 90 degrees or other orientations), and spatially related descriptions used here are subject to interpretation.

[0051] In a semiconductor die package, integrated circuit dies can have different properties, such as different sizes, different materials (or different combinations of materials), different thermal requirements, and / or different structural requirements. Additionally and / or alternatively, integrated circuit dies in a semiconductor die package can have different functional regions (e.g., memory regions, power supply regions, logic regions), each with different properties such as different sizes and / or different thermal requirements. The different properties of different integrated circuit dies in a semiconductor die package and / or different functional regions can lead to placement challenges within the semiconductor die package. For example, the different properties of different functional regions of the die in a semiconductor die package can lead to complex thermal management solutions and / or result in different thermal scaling ratios across the integrated circuit die. Without addressing these challenges, these challenges can shorten the operational lifespan of the integrated circuit dies in the semiconductor die package and / or lead to premature failure of the integrated circuit dies in the semiconductor die package.

[0052] In the various embodiments described herein, a physically smaller first integrated circuit die is directly bonded to a physically larger second integrated circuit die for vertical arrangement within a semiconductor die package. The smaller-sized first integrated circuit allows multiple passive dies to be placed on top of the second integrated circuit die in areas not occupied by the first integrated circuit die. Including multiple passive dies allows for customization of the passive dies to different properties for different regions of the second integrated circuit die. For example, different passive dies can be fabricated with different materials (or different material compositions) to account for different proportions of thermal amplification or reduction in the second die. In this approach, including multiple passive dies in the semiconductor die package can increase the thermal stability of the semiconductor die package, reduce the likelihood of integrated circuit die failure, and / or in other examples increase the overall reliability of the semiconductor die package.

[0053] Figures 1A-1C This is an illustration of Example 100 of the semiconductor die package 102 described herein. The semiconductor die package 102 includes a packaged semiconductor device comprising a plurality of active integrated circuit dies or wafers. The plurality of active integrated circuit dies may be vertically arranged and / or stacked in the semiconductor die package 102 using three-dimensional packaging techniques, such as direct bonding.

[0054] Figure 1A A top view of the semiconductor die package 102 is shown. Figure 1AIn this embodiment, the semiconductor die package 102 includes an active integrated circuit die 104. The active integrated circuit die 104 is an integrated circuit die that includes an active integrated circuit within the semiconductor die package 102, and the integrated circuit die is configured to perform various processing functions of the semiconductor die package 102. Examples of active integrated circuit dies 104 include logic integrated circuit dies, memory integrated circuit dies, high-bandwidth memory (HBM) integrated circuit dies, input / output (I / O) dies, system-on-a-chip (SoC) integrated circuit dies, dynamic random access memory (DRAM) integrated circuit dies, complementary metal-oxide-semiconductor image sensor (CMOS) integrated circuit dies, silicon etched integrated circuit dies, central processing unit (CPU) integrated circuit dies, image processing unit (GPU) integrated circuit dies, digital signal processing (DSP) integrated circuit dies, application-specific integrated circuit (ASIC) integrated circuit dies, and / or another type of active integrated circuit.

[0055] The active integrated circuit die 104 has a plurality of outer edges corresponding to its surroundings. These outer edges may include outer edge 104a, outer edge 104b, outer edge 104c, and outer edge 104d, etc. Figure 1A In this embodiment, the active integrated circuit die 104 may have a generally square or triangular top-view shape. Accordingly, outer edges 104a and 104c may be located on opposite sides of the active integrated circuit die, outer edges 104a and 104b may be generally perpendicular, outer edges 104c and 104d may be generally perpendicular. However, in other embodiments, the active integrated circuit die 104 may be generally annular (or generally circular), hexagonal, or other shapes. Alternatively, the active integrated circuit die 104 may include a non-standard shape or no fixed shape.

[0056] Further as Figure 1A As shown, the semiconductor die package 102 also includes an active integrated circuit die 106. The active integrated circuit die 106 is included on the active integrated circuit die 104, with the active integrated circuit dies 104 and 106 stacked and vertically arranged in the z-direction within the semiconductor die package 102. In some embodiments, the active integrated circuit dies 104 and 106 are of the same type. For example, the active integrated circuit dies 104 and 106 may each be a separate central processing unit die. In some embodiments, the active integrated circuit dies 104 and 106 are of different types. For example, the active integrated circuit die 104 may be a central processing unit die, and the active integrated circuit die 106 may be an input / output die or a high-bandwidth memory die.

[0057] Further as Figure 1A As shown, the top view area of ​​active integrated circuit die 106 is different from the top view area of ​​active integrated circuit die 104. For example, the top view size of active integrated circuit die 104 (such as the size of the xy region occupied by active integrated circuit die 104) may be larger than the top view size of active integrated circuit die 106 (such as the size of the xy region occupied by active integrated circuit die 106). In other examples, the top view shape of active integrated circuit die 106 may be different from the top view shape of active integrated circuit die 104. For example, active integrated circuit die 104 may have a generally square top view area, while active integrated circuit die 106 may have a generally rectangular top view area.

[0058] The different top views of active integrated circuit (IC) die 104 and active IC die 106 result in active IC die 106 occupying a smaller overall top view than active IC die 104. This allows multiple non-active dies 108a and 108b to be included on and / or on the active IC die 104, specifically on a region of active IC die 104 that extends laterally outward from active IC die 106. For example, non-active dies 108a and 108b may be included between the outer edges 104c of active IC die 106 and active IC die 104. Alternatively, one or more non-active dies 108a and / or 108b may be located between another outer edge (such as outer edge 104a, outer edge 104b, outer edge 104d) of active IC die 106 and active IC die 104.

[0059] Each of the passive dies 108a and 108b may include a passive component die and / or a die in the semiconductor die package 102 that does not perform electrical and / or processing functions. Examples of passive dies 108a and 108b include dummy dies, in-system passive device (IPD) dies, dielectric structures (such as thick films), and / or other types of passive dies. A passive die may also refer to another type of die that does not perform electronic and / or processing functions, such as an intercalation die, a filling die, or a die in the semiconductor die package 102. In-system passive device dies may include capacitor dies, resistor dies, inductor dies, or combinations thereof.

[0060] Each of the non-active dies 108a and 108b may be laterally adjacent to one side of the active integrated circuit die 106. In some embodiments, both non-active dies 108a and 108b are laterally adjacent to each other on the same side of the active integrated circuit die 106. In some embodiments, both non-active dies 108a and 108b are laterally adjacent to each other on different sides of the active integrated circuit die 106. The non-active dies 108a and the active integrated circuit die 106 may be substantially in contact (e.g., substantially in mutual contact) or may be spaced apart by a gap 110. In some embodiments, the size of the gap 110 (e.g., as shown in the figure) is... Figure 1A The distance between the passive die 108a and the active integrated circuit die 106 (dimension D1) is within the range of approximately 25 micrometers to 75 micrometers. If the gap 110 is too small, poor gap filling performance can cause the dielectric material in the gap 110 to break when it is filled with dielectric material. If the gap 110 is too large, there is not enough space on the active integrated circuit die 104 to provide for the passive die 108a, resulting in reduced structural integration of the passive die 108a. If the size of the gap 110 is within the range of approximately 25 micrometers to 75 micrometers, sufficient gap filling performance can be achieved when sufficient space is provided for setting the passive die 108a on and / or on the active integrated circuit die 104. However, other values ​​and ranges outside the approximately 25 micrometers to 75 micrometers range are within the scope of this disclosure.

[0061] The non-active die 108b and the active integrated circuit die 106 may be in physical contact (e.g., in physical contact with each other) or may be spaced apart by a gap 110. In some embodiments, the size of the gap 110 (e.g., the distance between the non-active die 108b and the active integrated circuit die 106) is within a certain range. Figure 1A (As indicated by dimension D2), the size is within the range of approximately 25 micrometers to 75 micrometers. If the gap 110 is too small, poor gap filling performance can result in the dielectric material in the gap 110 breaking down. If the gap 110 is too large, there is insufficient space on the active integrated circuit die 104 for the passive die 108b, resulting in reduced structural integration of the passive die 108b. If the size of the gap 110 is within the range of approximately 25 micrometers to 75 micrometers, its sufficient gap filling function can be achieved to provide sufficient space for placing the passive die 108a on and / or on the active integrated circuit die 104. However, other values ​​and ranges outside the approximately 25 micrometers to 75 micrometers range are within the scope of this disclosure.

[0062] In some embodiments, the passive dies 108a and 108b are laterally adjacent and edge-to-edge. In some embodiments, the passive dies 108a and 108b are not laterally adjacent to each other; the passive dies 108a and 108b may substantially touch (e.g., substantially contact each other) or may be spaced apart by a gap 110. In some embodiments, the size of the gap 110 (e.g., the distance between the passive dies 108b and the passive die 108b) is... Figure 1A (Illustrated dimension D3) includes a range of approximately 25 micrometers to 75 micrometers. If the gap 110 is too small, poor gap filling performance may result in the dielectric material in the gap 110 breaking down. If the gap 110 is too large, there is insufficient space on the active integrated circuit die 104 to provide for the inactive dies 108a and / or 108b, resulting in reduced integration of the inactive dies 108a and / or 108b. If the size of the gap 110 is within the range of approximately 25 micrometers to 75 micrometers, its sufficient gap filling function can be achieved to provide sufficient space for placing the inactive die 108a on and / or on the active integrated circuit die 104. However, other values ​​and ranges outside of approximately 25 micrometers to 75 micrometers are within the scope of this disclosure.

[0063] The active integrated circuit (ICC) die 108a and 108b occupy a region, comprising two or more passive dies. Compared to a single passive die, this allows different passive dies to be included in different regions or on the region of the active IC die 104. In particular, this allows different passive dies to be manufactured to optimize the properties of the passive dies for different regions of the active IC die 104. The passive dies 108a and 108b may comprise different materials (or different combinations of materials), and different structural arrangements having layers and / or features may include different combinations and arrangements of devices and / or may have different top-view dimensions and / or shapes, etc.

[0064] For example, the material, size, shape, structural arrangement, and / or another factor of the non-active die 108a can be configured to adjust the heat dissipation characteristics of the non-active die 108a for the region of the active integrated circuit die 104 in the regional heat pipe or below the non-active die 108a and / or achieve a specific coefficient of thermal expansion for the semiconductor die package 102. Similarly, the material, size, shape, structural arrangement, and / or another factor of the passive die 108b can be configured to adjust the heat dissipation characteristics of the passive die 108b for the region of the active integrated circuit die 104 under the passive die 108b and / or achieve a specific coefficient of thermal expansion for the semiconductor die package 102. Therefore, if a greater amount of heat is generated in the region of the passive integrated circuit die 104 under the passive die 108a than in the region of the passive integrated circuit die 104 under the passive die 108b during operation of the semiconductor die package 102, the passive die 108a may be manufactured comprising one or more materials to have a greater thermal conductivity than the material of the passive die 108b. Alternatively, if the region of the active integrated circuit die 104 below the non-active die 108a includes the integrated circuit, the operating performance of the integrated circuit is stable at continuously high temperatures, the non-active die 108a may be manufactured to include one or more materials having a lower thermal conductivity than the material of the non-active die 108b, if the region of the active integrated circuit die 104 below the non-active die 108b includes the integrated circuit, the operating performance of the integrated circuit is reduced at high temperatures.

[0065] Furthermore, the respective top-view dimensions, shapes, and / or positioning of the non-active dies 108a and 108b may also be configured to provide thermal management for specific regions of the active integrated circuit die 104. For example, the top-view dimensions (e.g., the width in the y-direction shown in...) Figure 1A The dimension D4 and / or the width in the x-direction are shown in Figure 1A The dimension D5) and / or the shape of the non-active die 108a can be configured to completely cover the power supply region or the high-volt region of the active integrated circuit die 104 and the top-view dimension (e.g., the width in the y-direction shown in the figure). Figure 1A The dimension D8 and / or the width in the x-direction are shown in Figure 1A The dimension D7) and / or the shape of the non-active die 108b can be configured to fully cover the power supply area or the high-volt area of ​​an active integrated circuit die 104.

[0066] As another example, factors such as material, size, shape, structural arrangement, and / or the non-active die 108a can be configured to adjust the rigidity of the region of the semiconductor die package 102 under the non-active die 108a of the active integrated circuit die 104. Similarly, factors such as material, size, shape, structural arrangement, and / or the non-active die 108a can be configured to adjust the rigidity of the region of the semiconductor die package 102 under the non-active die 108b of the active integrated circuit die 104. Therefore, the region of the active integrated circuit die 104 under the non-active die 108a includes a low-density metallization layer compared to the region of the active integrated circuit die 104 under the non-active die 108b, and the non-active die 108a may include a metallization layer to increase the rigidity of the semiconductor die package 102 in the region of the active integrated circuit die 104 under the non-active die 108a.

[0067] Figure 1B Description in Figure 1A A cross-sectional view along the current AA semiconductor die package 102. Therefore, the description in Figure 1B The cross-sectional view includes an active integrated circuit die 104, an active integrated circuit die 106 on and / or on the active integrated circuit die 104, and a non-active die 108a on and / or on the active integrated circuit die 104, and laterally adjacent to the active integrated circuit die 106. For example... Figure 1B As shown, active integrated circuit dies 104 and 106 are bonded together on a bonding layer (or bonding film) 112. The bonding layer 112 comprises one or more types of materials such as silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)) and / or another type of dielectric bonding material. Active integrated circuit dies 104 and 106 can be directly bonded (e.g., without an intermediate interlayer or other intermediate structure) so that active integrated circuit dies 104 and 106 are stacked and vertically arranged in the z-direction in the semiconductor die package 102.

[0068] Further as Figure 1B As shown, a dielectric filling layer 114a is used to fill the sides of the active integrated circuit die 104. A dielectric filling layer 114b is used to fill the regions (including gaps 110) surrounding the active integrated circuit die 104 and surrounding the sides of the active integrated circuit die 106 and the non-active die 108a. The dielectric filling layer 114b surrounds the active integrated circuit die 106. Each of the dielectric filling layers 114a and 114b may include one or more dielectric materials such as silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)), silicon oxynitride (SiON), and / or another type of dielectric material. The dielectric filling layers 114a and 114b can provide increased stability and electrical insulation for the active integrated circuit dies 104 and 106.

[0069] The semiconductor die package 102 includes a plurality of passivation layers, including passivation layers 116 and 118 on and / or on the bottom side of the semiconductor die package 102, and passivation layers 120, 122, and 124 on and / or on the top side of the semiconductor die package 102. In some embodiments, each of the passivation layers 116, 118, 120, 122, and 124 may comprise various types of electrically insulating materials, such as silicon nitride (Si). x N y Undoped silica glass (USG), silicon oxide (SiO2) x (e.g., silicon dioxide (SiO2)) and / or another type of passivation material.

[0070] Each of the active integrated circuit chips 104 and 106 may include a substrate (e.g., substrate 126a in active integrated circuit chip 104 and substrate 126b in active integrated circuit chip 106). Each of substrates 126a and 126b may include a silicon substrate, the material of which the substrate is formed includes silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), silicon on insulating layer substrate (SOI), or another type of semiconductor substrate.

[0071] Each of the active integrated circuit dies 104 and 106 may include multiple stacked layers, including an inner layer dielectric (ILD) (such as inner layer dielectric 128a on substrate 126a and inner layer dielectric 128b on substrate 126b). Each of the inner layer dielectrics 128a and 128b may include silicon nitride (Si). x N y ), oxides (e.g., silicon oxide (SiO) x (and / or other oxidized materials) and / or another type of dielectric material.

[0072] Each of the active integrated circuit dies 104 and 106 may include an integrated circuit device (e.g., an integrated circuit device 130a in substrate 126a and / or inner dielectric layer 128a, and an integrated circuit device 130b in substrate 126b and / or inner dielectric layer 128b). Integrated circuit devices 130a and 130b may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor structures (finFETs), gate-all-around (GAA) transistor structures), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuitry, and / or other types of front-end semiconductor devices.

[0073] Each of the active integrated circuit dies 104 and 106 may include contacts (e.g., contacts 132a and 132b) electrically coupled to an integrated circuit device. Contact 132a may extend through the inner dielectric layer 128a and be electrically coupled to the integrated circuit device 130a, and contact 132b may extend through the inner dielectric layer 128b and be electrically coupled to the integrated circuit device 130b. Contacts 132a and 132b may include channels, plugs, and / or another type of extended electrically conductive structure. Contacts 132a and 132b may include electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au).

[0074] Each of the active integrated circuit dies 104 and 106 may include multiple dielectric layers arranged alternately in the z-direction within the semiconductor die package 102. For example, the active integrated circuit die 104 may include a plurality of alternating inner dielectric layers 134a and etch stop layers (ESLs) 136a. The active integrated circuit die 104 may include multiple conductive structures 138a in the alternating inner dielectric layers 134a and etch stop layers 136a. The substrate 126a, inner dielectric layers 128a, integrated circuit device 130a, and contact 132a may correspond to the device layer or the line front end region (FEOL) of the active integrated circuit die 104, and the inner dielectric layers 134a, etch stop layers 136a, and conductive structures 138a may correspond to the inner layer or the line back end region (BEOL) of the active integrated circuit die 104.

[0075] Similarly, the active integrated circuit die 106 may include a plurality of alternating inner dielectric layers 134b and etch stop layers 136b. The active integrated circuit die 106 may include a plurality of conductive structures 138b in the alternating inner dielectric layers 134b and etch stop layers 136b. The substrate 126b, inner dielectric layers 128b, integrated circuit device 130b and contact 132b may correspond to a device layer or the line front end region of the active integrated circuit die 106, and the inner dielectric layers 134b, etch stop layers 136b and conductive structures 138b may correspond to an inner layer or the line rear end region of the active integrated circuit die 106.

[0076] Each of the inner dielectric layers 134a and 134b may comprise an oxide (e.g., silicon oxide (SiOx) and / or another oxide material), undoped silicon glass (USG), borosilicate glass (BSG), fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrosilicone hydrochloride (HSQ), and / or other suitable dielectric materials. In some embodiments, the inner dielectric layer 134a or 134b comprises an extremely low dielectric constant (ELK) dielectric material having a dielectric constant less than approximately 2.5. Extremely low dielectric constant dielectric materials include carbon-doped silicon oxide (C-SiO2). xamorphous fluorinated carbon (aC) x F y ), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbonate (SiOC) polymers, porous HSQ, porous methylsilsesquioxane (MSQ), porous polyarylene ether (PAE), and / or porous silica (SiO2) x ), etc. The etch stop layers 136a and 136b may each comprise silicon nitride (Si). x N y ), silicon carbide (SiC), silicon oxynitride (SiON) and / or another suitable dielectric material.

[0077] Conductive structures 138a and 138b provide electrical transmission paths enabling signals and / or power to and / or from integrated circuit devices 130a and / or 130b. Conductive structures 138a and 138b may include combinations of trenches, metallization layers, conductive traces, channels, interconnects, and other types of conductive structures. Each of conductive structures 138a and 138b may include one or more electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof.

[0078] The active integrated circuit die 104 may also include a sealing ring structure 140a surrounding the conductive structure 138a to protect the active integrated circuit die 104 from physical and / or electrical damage during the dicing operation from which the active integrated circuit die 104 is diced from the wafer. The sealing ring structure 140a further provides protection against moisture ingress and other contamination. Similarly, the active integrated circuit die 106 may include a sealing ring structure 140b surrounding the conductive structure 138b to protect the active integrated circuit die 106 from physical and / or electrical damage during the dicing operation from which the active integrated circuit die 106 is diced from the wafer. The sealing ring structure 140b further provides protection against moisture ingress and other contamination.

[0079] The active integrated circuit die 104 may include passivation layers 142a and 144a (e.g., inner dielectric layer 134a and etch stop layer 136a) on or above a plurality of alternating dielectric layers to protect the inner layers of the active integrated circuit die 104. Similarly, the active integrated circuit die 106 may include passivation layers 142b and 144b (e.g., inner dielectric layer 134b and etch stop layer 136b) on or above a plurality of alternating dielectric layers to protect the inner layers of the active integrated circuit die 106.

[0080] Metal pad 146a may include conductive structure 138a on and / or on, and metal pad 148a may be included on and / or on sealing ring structure 140a. Metal pad 146b may be included on and / or on conductive structure 138b, and metal pad 148b may be included on and / or on sealing ring structure 140b. Metal pads 146a, 148a, 146b and 148b may each include aluminum (Al), aluminum-copper (AlCu) and / or another conductive material. Sealing ring structures 140a and 140b may also include solder pads 150a and 150b, respectively. Alternatively, solder pads 150a and / or 150b may be excluded. Each of solder pads 150a and 150b may include examples of electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof.

[0081] The active integrated circuit die 104 also includes a bonding layer 152, which is used in the manufacturing of the semiconductor die package 102 to bond the active integrated circuit die 104 to the carrier substrate. The bonding layer 152 includes one or more types of materials such as silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)) and / or another type of dielectric bonding material.

[0082] The active integrated circuit die 106 may also include pads 154 that enable the active integrated circuit die 106 to bond to a die-to-die inlay 156 of the active integrated circuit die 104. Each pad 154 may include examples of electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof. The die-to-die inlay 156 may include a die-to-die line, a through-silicon via (TSV), or another type of die-to-die inlay. The die-to-die inlay 156 also electrically connects the active integrated circuit dies 104 and 106. In this manner, electrical signals and / or power can be provided through the die-to-die inlay 156 between the active integrated circuit dies 104 and 106. The grain-to-grain inlay 156 includes examples of electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof.

[0083] like Figure 1B As further shown, the topmost conductive structure 138a (e.g., the top metal layer) can be coupled to the connection structure 158 on top of the semiconductor die package 102 (facing downwards). Figure 1BThe connection structure 158 may include solder balls, solder bumps, contact pads (e.g., ground grid array (LGA) pads), contact pins (e.g., pin grid (PGA) pins), under-bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, flip-chip interconnect (C4) bumps with controllable collapse solder height, and / or other types of connection structures that enable the semiconductor die package 102 to be connected to a substrate or socket, etc.

[0084] like Figure 1B As further shown, the non-active die 108a is laterally adjacent to the active integrated circuit die 106 and located above a portion 160 of the active integrated circuit die 104. The non-active die 108a may be located above and / or on (in some embodiments, bonded to) the bonding layer 112. As described above, the non-active die 108a may be fabricated to provide thermal management and / or structural management for a portion 160 of the active integrated circuit die 104, which is located beneath the non-active die 108a, including combinations and / or properties of materials, dimensions, shapes, structural combinations, and / or layers and / or other characteristics. Figure 1B In the example described, portion 160 of the active integrated circuit die 104 may include a high-density integrated circuit device 130a, thus a significant amount of heat can be generated in portion 160 of the active integrated circuit die 104. Therefore, in Figure 1B For example, the non-active die 108a may include one or more materials such as silicon, graphite, or graphene with high thermal conductivity and / or another material with high thermal conductivity. High thermal conductivity enables the non-active die 108a to conduct heat away from a portion 160 of the active integrated circuit die 104, thereby reducing and / or stabilizing the operating temperature of the portion 160 of the active integrated circuit die 104.

[0085] like Figure 1B As further shown, the active integrated circuit die 106 may have a thickness in the z-direction (indicated in...). Figure 1B The dimension D8) and non-active grain 108a can have a z-direction thickness (indicated in Figure 1B (Dimension D9). In some embodiments, the z-direction thicknesses of the active integrated circuit die 106 and the passive die 108a are substantially the same, such that the back side of the substrate 126b and the top of the passive die 108b are substantially coplanar. This provides a planar substrate that can be formed on the passivation layer 120. However, in other embodiments, the z-direction thicknesses of the active integrated circuit die 106 and the passive die 108a may be different. For example, the difference between the z-direction thicknesses of the active integrated circuit die 104 and the passive die 108a may be greater than 0 micrometers to 1 micrometer or larger in some embodiments.

[0086] Figure 1C The semiconductor die package 102 is described along the... Figure 1A The section of line BB. Therefore, this section is described in Figure 1C It includes an active integrated circuit die 104, an active integrated circuit die 106 on and / or on the active integrated circuit die 104, and a non-active die 108b on and / or on the active integrated circuit die 104 and laterally adjacent to the active integrated circuit die 106.

[0087] like Figure 1C As shown, the non-active die 108b is laterally adjacent to the active integrated circuit die 106 and located on a portion 162 of the active integrated circuit die 104. The non-active die 108b may be located above or on the bonding layer 112 (and in some embodiments, bonded to the bonding layer 112). As described above, the non-active die 108b may be fabricated to provide thermal management and / or structural management for the portion 162 of the active integrated circuit die 104 located beneath the non-active die 108b, including combinations and / or properties of materials, dimensions, shapes, structural combinations, and / or layers and / or other characteristics. Figure 1C In the illustrated example, portion 162 of the active integrated circuit die 104 may include a low-density integrated circuit device 130a, thus a small amount of heat can be generated in portion 162 of the active integrated circuit die 104. Therefore, in Figure 1C In the example, the non-active grain 108b may include one or more materials with low thermal conductivity, such as silicon oxide (SiO2). x Such as silicon dioxide), silicon nitride (Si) x N y Materials such as Si3N4, silicon oxynitride (SiON), and / or another material with low thermal conductivity. Low thermal conductivity enables the inactive die 108b to provide structural stability in the semiconductor die package 102, which has minimal expansion and contraction due to heat.

[0088] like Figure 1C Furthermore, as shown, the non-active grain 108b can have a thickness in the z-direction (indicated in...). Figure 1C (Dimension D10 in the original text). In some embodiments, the z-direction thicknesses of the active integrated circuit die 106 (dimension D8) and the non-active die 108b are substantially the same, such that the rear side of the substrate 126b and the top of the non-active die 108b are substantially coplanar. This provides a planar substrate that can be formed on the passivation layer 120. However, in other embodiments, the z-direction thicknesses of the active integrated circuit die 106 and the non-active die 108b may be different. For example, different between the z-direction thicknesses of the active integrated circuit die 104 and the non-active die 108b, in some embodiments, may be greater than 0 micrometers to 1 micrometer or larger.

[0089] As described above, Figures 1A-1C This is provided as an example. Other examples may differ from the one provided. Figures 1A-1C As described.

[0090] Figures 2A-2I The accompanying drawing is a top-view example of a non-active die layout in a semiconductor die package as described herein. Although the non-active die described herein is similar to... Figures 2A-2I The top view example relating to semiconductor die package 102 in the example can be implemented in other semiconductor die packages, including semiconductor packages 402, 502 and / or 602 described herein.

[0091] like Figure 2A As shown, the top-view layout example 200 for a non-active die in a semiconductor die package includes, as... Figure 1A The similar top-view layout is described. Except that the passive dies 108a and 108b are substantially in contact along adjacent edges perpendicular to and adjacent to the active integrated circuit die 106. In this example 200, the passive dies 108a and 108b may include semiconductor dies (e.g., silicon virtual wafers), and the passive die 108a may include a dielectric layer (e.g., a dielectric thick film) deposited beside the passive die 108a, such that the dielectric layer is in contact with the semiconductor die.

[0092] like Figure 2B As shown, Example 202 of the top-view layout of a non-active die in a semiconductor die package includes, as... Figure 1A The described top-view layouts are similar, except that the non-active dies 108a and 108b have different top-view dimensions. The non-active dies 108a and 108b may have different top-view dimensions covering functional regions of different sizes based on the active integrated circuit die 104. In Example 202, the y-direction width (dimension D4) of the non-active die 108a is greater than the y-direction width (dimension D6) of the non-active die 108b.

[0093] like Figure 2C As shown, the top-view layout example 204 for a non-active die in a semiconductor die package includes, as... Figure 1AThe described top-view layouts are similar, except that the non-active dies 108a and 108b have different top-view shapes. Furthermore, the non-active dies 108a and 108b may have non-standard polygonal top-view shapes covering functional areas of different sizes and / or shapes based on the active integrated circuit die 104. Additionally and / or alternatively, the non-active dies 108a and / or 108b may have curved shapes (e.g., curved standard shapes such as circles or ellipses, curved non-standard shapes) or curved portions.

[0094] like Figure 2D As shown, Example 206 of the top-view layout of a non-active die in a semiconductor die package includes, as... Figure 1A The described top-view layout is similar, except that another non-active die 108c is included in a region or portion of the active integrated circuit die 104. Other numbers of non-active dies are also within the scope of this disclosure. Increased numbers of non-active dies, such as in... Figure 2D Example 206 in the example enables increased variability in adjusting the non-active die for different portions or regions of the active integrated circuit die 104, thereby increasing the performance in the heat pipe and / or the structural integration of the semiconductor die package 102.

[0095] like Figure 2E As shown, Example 208 of the top-view layout of a non-active die in a semiconductor die package includes, as... Figure 1A The described similar top-view layouts, except that two or more non-active grains 108a-108c have different top-view dimensions relative to the [missing information - likely referring to a specific configuration or structure]. Figure 2D The approximately the same top view dimensions as in Example 206. For example, the y-direction width and / or x-direction width of the inactive die 108a may be greater than the y-direction width and / or x-direction width of the inactive die 108b. As shown in another example, the y-direction width and / or x-direction width of the inactive die 108b may be greater than the y-direction width and / or x-direction width of the inactive die 108c. As shown in another example, the size of the top view area occupied by the inactive die 108a may be greater than the size of the top view area occupied by the inactive die 108b. As shown in another example, the size of the top view area occupied by the inactive die 108b may be greater than the size of the top view area occupied by the inactive die 108c.

[0096] like Figure 2F As shown, the top-view layout example 210 for a non-active die in a semiconductor die package includes, as... Figure 2EThe described top-view layout is similar, except that the non-active dies 108a and 108b have different top-view shapes. Furthermore, the non-active dies 108a and 108b may have non-standard polygonal top-view shapes covering functional regions of different sizes and / or shapes based on the active integrated circuit die 104. Additionally and / or alternatively, the non-active dies 108a and / or 108b may have curved shapes (e.g., curved standard shapes such as circles or ellipses, curved non-standard shapes) or curved portions. In some embodiments, the non-active dies 108a and 108c have different top-view shapes and / or each has a non-standard shape. In some embodiments, the non-active dies 108b and 108c have different top-view shapes and / or each has a non-standard shape. In some embodiments, the non-active dies 108a-108c have different top-view shapes and / or each has a non-standard shape.

[0097] like Figure 2G As shown, example 212 of the top-view layout of a non-active die in a semiconductor die package includes, as... Figure 2D The described top-view layout, except that two or more non-active grains 108a-108c are arranged in the x-direction relative to the x-direction. Figure 2D Example 206 shows non-active dies 108a-108c arranged in the y-direction. Other combinations of x-direction arrangements and / or y-direction arrangements are within the scope of this disclosure and can increase flexibility to adjust for different portions or regions of the active integrated circuit die 104, thereby increasing thermal management performance and / or structural integration of the semiconductor die package 102.

[0098] like Figure 2H As shown, example 214 of the top-view layout of a non-active die in a semiconductor die package includes, as... Figure 1A The described top-view layout differs only in that the non-active chips 108a and 108b are located on different sides laterally adjacent to the active integrated circuit chip 106. For example, non-active chip 108a may be located laterally between the first side of the active integrated circuit chip 106 and the outer edge 104c of the active integrated circuit chip 104, and non-active chip 108b may be located laterally between the second side of the active integrated circuit chip 106 and the outer edge 104a of the active integrated circuit chip 104. Therefore, in Example 214, non-active chips 108a and 108b are located on opposite sides laterally adjacent to the active integrated circuit chip 106. However, in other examples, non-active chips 108a and 108b may be located laterally adjacent to the vertical side of the active integrated circuit chip 106.

[0099] like Figure 2I As shown, Example 216 of the top-view layout of a non-active die in a semiconductor die package includes, as... Figure 2IThe described similar top-view layout, except that another non-active die 108c includes a side laterally adjacent to the active integrated circuit die 106. For example, the non-active die 108c includes a side laterally adjacent to the active integrated circuit die 106. For example, the non-active die 108a may be located laterally on the first side of the active integrated circuit die and the outer edge 104c of the active integrated circuit die 104, the non-active die 108b may be laterally located between the second side of the active integrated circuit die 106 and the outer edge 104a of the active integrated circuit die 104, and the non-active die 108c may be located laterally between the third side of the active integrated circuit die 106 and the outer edge 104d of the active integrated circuit die 104. Therefore, in Example 216, non-active dies 108a and 108b are located on opposite sides laterally adjacent to the active integrated circuit die 106, and non-active die 108c is located on multiple sides laterally adjacent to the active integrated circuit die 106, adjacent to the width of non-active dies 108a and 108b.

[0100] As indicated above, Figures 2A-2I Provided as an example. Other examples may differ from those regarding... Figures 2A-2I The description.

[0101] Figures 3A-3T The accompanying drawings illustrate an example embodiment 300 of forming a semiconductor die package. Although the process operations of example embodiment 300 are described and illustrated herein in relation to the formation of semiconductor die package 102, the process operations of example embodiment 300 can be performed to form another semiconductor device as described herein, such as... Figures 4A-4E Semiconductor die package 402, Figures 5A-5E Semiconductor die package 502 and / or Figures 6A-6E In some embodiments, semiconductor die package 602, etc., one or more semiconductor process operations are described regarding... Figures 3A-3T It can be used with one or more semiconductor process tools such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or other types of semiconductor process tools.

[0102] Back Figure 3A The substrate 126a provides an active integrated circuit die 104. The substrate 126a can provide for the formation of semiconductor wafers such as silicon wafers, SOI wafers, and / or other types of semiconductor wafers.

[0103] like Figure 3BAs shown, an integrated circuit device 130a may be formed on a substrate 126a, including in a portion 160 of an active integrated circuit die 104 and in a portion 162 (not shown) of an active integrated circuit die 104. One or more semiconductor process tools may be used to form portions of one or more integrated circuit devices 130a. For example, a deposition tool may be used to perform various deposition operations on the deposition structure and / or layers of the integrated circuit device 130a and / or to deposit a photoresist layer for etching portions of the substrate 126a and / or the deposition layer. As shown in another example, an exposure tool may be used to expose the deposited photoresist layer to form a pattern in the photoresist layer. As shown in another example, an etching tool may be used to etch portions of the substrate 126a and / or the deposition layer that have formed the integrated circuit device 130a. As shown in another example, a planarization tool may be used to planarize portions of the integrated circuit device 130a. As shown in another example, an electroplating tool may be used to deposit a metal structure and / or layer of the integrated circuit device 130a.

[0104] like Figure 3B As shown, deposition tools are used to deposit an inner dielectric layer 128a on and / or on a substrate 126a and an inner dielectric layer 128a on and / or on an integrated circuit device 130a. The deposition tools can be used to deposit the inner dielectric layer 128a using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation, and / or other suitable deposition techniques. In some embodiments, planarization tools can be used to perform planarization operations such as chemical mechanical planarization (CMP) after the deposition of the inner dielectric layer 128a to planarize it.

[0105] like Figure 3C As shown, contacts 132a of the integrated circuit device 130a may be formed through the inner dielectric layer 128a. Contacts 132a may be formed in recesses of the inner dielectric layer 128a. In some embodiments, a pattern in the photoresist layer is used to etch the inner dielectric layer 128a to form the recesses. In these embodiments, a deposition tool may be used to form a photoresist layer on the inner dielectric layer 128a. An exposure tool may be used to expose the photoresist layer in a radiation source to etch a pattern onto the photoresist layer. A development tool may be used to develop and remove the exposed patterned portions of the photoresist layer. An etching tool may be used to etch the pattern-based dielectric layer to form the recesses. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, vapor phase etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove residual portions of the photoresist layer (e.g., using a chemical remover, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for etching the inner dielectric layer 128a according to a pattern to form a recess.

[0106] The deposition tool can be used to deposit material for the contact 132a in the recess, using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, and / or other suitable deposition techniques. The material for the contact 132a can be deposited in one or more deposition operations. In some embodiments, a seed layer is formed by the first deposition and the material for the contact 132a is deposited on the seed layer. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize the contact 132a after the contact 132a has been deposited such that the top of the contact 132a is substantially coplanar with the top of the inner dielectric layer 128a.

[0107] like Figure 3C As shown, a first portion of the inner layer of the active integrated circuit die 104 is formed on the inner dielectric layer 128a. One or more deposition tools are used to deposit replacement layers of the inner dielectric layer 134a and the etch stop layer 136a in the first portion of the inner layer of the active integrated circuit die 104. In this method, the inner dielectric layer 134a and the etch stop layer 136a may be arranged in the z-direction of the active integrated circuit die 104. One or more deposition tools may be used to etch the inner dielectric layer 134a and the etch stop layer 136a using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation, and / or another suitable deposition technique. In some embodiments, a planarization tool may be used to planarize the inner dielectric layer 134a and / or the etch stop layer 136a after the inner dielectric layer 134a and / or the etch stop layer 136a have been deposited.

[0108] Further as Figure 3C As shown, deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools can be used to perform various operations to form the conductive structure 138a and the first portion of the sealing ring structure 140a in the first portion of the inner layer of the active integrated circuit die 104. The conductive structure 138a and the first portion of the sealing ring structure 140a may be included in the inner dielectric layer 134a and / or the etch stop layer 136a.

[0109] A first portion of the conductive structure 138a and the sealing ring structure 140a may be formed in a recess in one or more inner dielectric layers 134a and / or etch stop layers 136a. In some embodiments, a pattern in the photoresist layer is used to etch the inner dielectric layer 134a and etch stop layers 136a to form the recess. In some embodiments, a deposition tool may be used to form a photoresist layer on top of the inner dielectric layer 134a. An exposure tool may be used to expose the photoresist layer to a radiation source to etch a pattern in the photoresist layer. A development tool may be used to develop and remove the exposed patterned portions of the photoresist layer. An etching tool may be used to etch the pattern-based inner dielectric layer 134a and etch stop layers 136a to form the recess. In some embodiments, the etching operation includes a dry etching operation (e.g., plasma-based etching, vapor phase etching), a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove residual portions of the photoresist layer (e.g., using a chemical remover, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for etching an inner dielectric layer 134a and an etch stop layer 136a based on a pattern to form a recess.

[0110] A deposition tool can be used to deposit the material of the conductive structure 138a and the first portion of the sealing ring structure 140a in the recess, using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, and / or another suitable deposition technique. The material of the conductive structure 138a and the first portion of the sealing ring structure 140a can be deposited in one or more deposition operations. In some embodiments, a seed layer is the first deposition and the material of the conductive structure 138a and the first portion of the sealing ring structure 140a are deposited on the seed layer. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., a chemical mechanical planarization operation) to planarize the material of the conductive structure 138a and the sealing ring structure 140a.

[0111] like Figure 3DAs shown, a die-to-die inlay 156 forms a first portion through the inlay layer and into the substrate 126a. To form the die-to-die inlay 156, a recess is formed through the first portion of the inlay layer and into the substrate 126a. In some embodiments, the recess is formed by etching the inner dielectric layer 134a and the etch stop layer 136a of the first portion of the inlay layer, the inner dielectric layer 128a, and the substrate 126a in the pattern of the photoresist layer. In these embodiments, a deposition tool can be used to form a photoresist layer on top of the inner dielectric layer 134a. An exposure tool can be used to expose the photoresist layer in a radiation source to etch a pattern on the photoresist layer. A development tool can be used to develop and remove the exposed patterned portion of the photoresist layer. An etching tool is used to etch the inner dielectric layer 134a and the etch stop layer 136a of the first portion of the inner dielectric layer, the inner dielectric layer 128a, and the substrate 126a according to the pattern to form the recess. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching. In some embodiments, a photoresist removal tool may be used to remove residual portions of the photoresist layer (e.g., using a chemical remover, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to form recesses in a pattern-based dielectric layer.

[0112] Deposition tools can be used to deposit grain-to-grain inlines 156 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, and / or other suitable deposition techniques. The grain-to-grain inlines 156 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited and the grain-to-grain inlines 156 are deposited on the seed layer. In some embodiments, one or more pads (e.g., barrier pads, adhesion pads) can be first deposited on the recess and the grain-to-grain inlines 156 can be deposited on one or more pads in the recess. In some embodiments, planarization tools are used to perform planarization operations (e.g., chemical mechanical planarization) to planarize the grain-to-grain inlines 156 after grain-to-grain inlines 156 deposition.

[0113] like Figure 3E As shown, a second portion of the inner layer of the active integrated circuit die 104 may be formed. Forming the second portion of the inner layer includes forming an additional inner dielectric layer 134a, an additional etch stop layer 136a, an additional conductive structure 138a, and / or as described in relation to... Figure 3C An additional portion of the sealing ring structure 140a in a similar method. Further as... Figure 3E As shown, a passivation layer 142a may be deposited, a metal pad 146a may be formed on one or more conductive structures 138a, and one or more metal pads 148a may be formed on a sealing ring structure 140a.

[0114] like Figure 3F As shown, solder pad 150a may be formed on metal pad 148a. In some embodiments, solder pad may also be formed on one or more conductive structures 138a. Furthermore, bonding layer 152 may be formed on passivation layer 142a and another bonding layer 302 may be formed on bonding layer 152. In some embodiments, etch stop layer is deposited on bonding layer 152 and bonding layer 302 is deposited on etch stop layer.

[0115] Deposition tools can be used to deposit solder pads 150a using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, and / or other suitable deposition techniques. Solder pads 150a can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited and solder pads 150a are deposited on the seed layer. In some embodiments, one or more pads (such as barrier pads, adhesion pads) can be first deposited in a recess and solder pads 150a can be deposited on one or more pads in the recess. In some embodiments, planarization tools are used to perform planarization operations (e.g., chemical mechanical planarization) to planarize solder pads 150a after solder pad 150a deposition.

[0116] Deposition tools can be used to deposit bonding layers 152 and 302 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. Bonding layers 152 and 302 can be deposited in one or more deposition operations. In some embodiments, planarization tools can be used to perform planarization operations (e.g., chemical mechanical planarization) to planarize bonding layers 152 and 302 after bonding layers 152 and 302 deposition.

[0117] like Figure 3G As shown, the active integrated circuit die 104 is bonded to a carrier substrate 304, which uses bonding layers 302 and 306. Accordingly, the active integrated circuit die 104 can be inverted or rotated by 108 degrees to bond the active integrated circuit die 104 to the carrier substrate 304. Bonding tools can be used to bond the active integrated circuit die 104 to the carrier substrate 304, using fusion bonding technology and / or another bonding technology.

[0118] like Figure 3H As shown, the region surrounding the active integrated circuit die 104 is filled with a dielectric filling layer 114a. Deposition tools can be used to deposit the dielectric filling layer 114a using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. The dielectric filling layer 114a can be deposited in one or more deposition operations.

[0119] Further as Figure 3H As shown, a planarization tool or wafer polishing tool can be used to perform planarization operations (e.g., chemical mechanical planarization, wafer polishing) to planarize the dielectric filling layer 114a and remove material from and / or over the back side of the substrate 126a to expose the die to the die inlay 156 through the back side of the substrate 126a.

[0120] Further as Figure 3I As shown, a bonding layer 112 is formed on and / or on the back side of the substrate 126a of the active integrated circuit die 104. Deposition tools can be used to deposit the bonding layer 112 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. In some embodiments, planarization tools are used to perform planarization operations (such as chemical mechanical planarization) to planarize the bonding layer 112.

[0121] like Figure 3J and Figure 3K As shown, active integrated circuit die 106 is bonded to active integrated circuit die 104 such that active integrated circuit die 104 and active integrated circuit die 106 are stacked and vertically arranged in semiconductor die package 102. Active integrated circuit die 106 can be formed using similar technologies and processes as those described above. Figures 3A-3I As described.

[0122] In some embodiments, a bonding tool is used to form a dielectric-to-dielectric bonding layer 112 on each of the active integrated circuit die 104 and the active integrated circuit die 106 to bond the active integrated circuit die 104 and the active integrated circuit die 106. In some embodiments, a bonding tool is used to form a metal-to-metal bonding between the die-to-die inlay 156 of the active integrated circuit die 104 and the pad 154 of the active integrated circuit die 106 to bond the active integrated circuit die 104 and the active integrated circuit die 106. In some embodiments, a bonding tool is used to form both dielectric-to-dielectric bonding and metal-to-metal bonding to bond the active integrated circuit die 104 and the active integrated circuit die 106.

[0123] like Figure 3L As shown, non-active dies 108a and 108b can be provided on and / or on one or more sides of the active integrated circuit die 104, such that the non-active dies 108a and 108b are laterally adjacent to one or more sides of the active integrated circuit die 106. Specifically, non-active dies 108a and 108b can be provided on the same side of the active integrated circuit die 104 and / or on the bonded active integrated circuit die 104. Figure 3M As shown, the non-active die 108a can provide a portion 160 above the active integrated circuit die 104. For example... Figure 3NAs shown, the non-active die 108b can be provided on a portion 162 of the active integrated circuit die 104. The non-active dies 108a and 108b can be arranged in one or more configurations illustrated and described herein, such as regarding... Figures 1A-1C , Figures 2A-2I , Figures 4A-4E , Figures 5A-5E and / or Figures 6A-6F In these embodiments, the non-active die 108c is also provided on and / or on the active integrated circuit die 104. In some embodiments, the non-active dies 108a and 108b (and, in some embodiments, the non-active die 108c and / or additional non-active dies) are arranged in another configuration.

[0124] In some embodiments, the inactive die 108a and / or 108b comprises a semiconductor die (e.g., a silicon die) and is bonded to the bonding layer 112. In some embodiments, the inactive die 108a and / or 108b comprises a dielectric layer (e.g., a dielectric thick film) deposited on the active integrated circuit die 104 using a deposition tool. In these embodiments, the inactive die 108a and / or 108b may be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), oxidation techniques, and / or other suitable deposition techniques.

[0125] like Figure 3O and Figure 3P As shown, the dielectric filler layer 114b surrounds the active integrated circuit die 106 region, the inactive die 108a region, and the inactive die 108b region filled by the dielectric filler layer 114b. If the active integrated circuit die 106, the inactive dies 108a, and / or 108b are spaced apart by a gap 110, the gap 110 can be filled with the material of the dielectric filler layer 114b. Deposition tools can be used to deposit the dielectric filler layer 114b using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. The dielectric filler layer 114b can be deposited in one or more deposition operations. Planarization tools can be used to perform planarization operations (e.g., chemical mechanical planarization operations) to planarize the dielectric filling layer 114b, the active integrated circuit die 106, the substrate 126b of the active integrated circuit die 106, and the non-active dies 108a and 108b so that the dielectric filling layer 114b, the active integrated circuit die 106, the substrate 126b of the active integrated circuit die 106, and the non-active dies 108a and 108b are substantially coplanar.

[0126] like Figure 3QAs shown, a passivation layer 120-124 is formed or provided on an active integrated circuit die 106 of a semiconductor die package 102. Deposition tools can be used to deposit the passivation layer 120-124 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation, and / or other suitable deposition techniques. The passivation layer 120-124 may be deposited in one or more deposition operations. In some embodiments, a planarization tool can be used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize the passivation layer 120-124 after the passivation layer 120-124 is deposited. Additionally and / or alternatively, one or more passivation layers 120-124 may be distributed on the active integrated circuit die 104. Additionally and / or alternatively, the semiconductor die package 102 may be placed on and / or on one or more passivation layers 120-124 on a carrier substrate.

[0127] like Figure 3R As shown, the semiconductor die package 102 is inverted and one or more operations are performed to remove the carrier substrate 304 and bonding layers 302 and 306 from the semiconductor die package 102. In some embodiments, the carrier substrate 304 is thermally operated to modify the adhesive properties of the bonding layers 302 and / or 306 to peel off from the semiconductor die package 102. Energy sources such as ultraviolet (UV) lasers, carbon dioxide (CO2) lasers, or infrared (IR) lasers are used to irradiate and incorporate the bonding layers 302 and / or 306 until the adhesive properties of the bonding layers 302 and / or 306 are reduced. The carrier substrate 304 and bonding layers 302 and 306 are then substantially separated and removed from the semiconductor die package 102. Additionally and / or alternatively, the carrier substrate 304, bonding layers 302 and / or bonding layers 306 are removed by etching and / or planarization.

[0128] like Figure 3S and Figure 3T As shown, passivation layers 116 and 118 are formed on the active integrated circuit die 104. Deposition tools can be used to deposit passivation layers 116 and 118 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation, and / or other suitable deposition techniques. Passivation layers 116 and 118 may be deposited in one or more deposition operations. In some embodiments, planarization tools can be used to perform planarization operations (e.g., chemical mechanical planarization) to planarize passivation layers 116 and 118 after passivation layer 116 and 118 deposition. Additionally and / or alternatively, passivation layers 116 and 118 may be distributed on the active integrated circuit die 104. Interconnection structure 158 may also be attached to the semiconductor die package 102.

[0129] As indicated above, Figures 3A-3TThis is provided as an example. Other examples can be found from [link to relevant information]. Figures 3A-3T The difference in description.

[0130] Figures 4A-4E The accompanying drawings illustrate an example 400 of a semiconductor die package 402. The semiconductor die package 402 includes a packaged semiconductor device comprising multiple active integrated circuit (AIC) dies or wafers. The multiple AIC dies may be vertically arranged and / or stacked in the semiconductor die package 402 using three-dimensional packaging techniques, such as direct bonding. Figure 4A The top view of the semiconductor die package 402 is shown. Figure 4B The semiconductor die package 402 is described along the... Figure 4A The cross section of line CC in the middle. Figure 4C The semiconductor die package 402 is described along the... Figure 4A The cross section of line DD in the middle.

[0131] like Figures 4A-4C As shown, the semiconductor die package 402 includes similar combinations and arrangements of layers and / or structures 404-462 as illustrated and described. Figures 1A-1C The layers and / or structures 104-162 of the semiconductor die package 102. The layers and / or structures 404-462 of the semiconductor die package 402 may be formed using similar technologies and / or processes in relation to... Figures 3A-3T Those descriptions.

[0132] However, as Figure 4B and Figure 4C As shown, active integrated circuit dies 404 and 406 are oriented in a mirror configuration such that the inner layers of active integrated circuit dies 404 and 406 face each other. This enables active integrated circuit dies 404 and 406 to be directly bonded in dielectric-to-dielectric bonding, between the respective bonding layers 412 and 452 of active integrated circuit dies 404 and 406, and directly bonded in metal-to-metal bonding, between the respective pads 454a and 454b of active integrated circuit dies 404 and 406.

[0133] Further as Figure 4B As shown, the non-active die 408a also includes a semiconductor structure 464 (e.g., a semiconductor die such as a silicon die) and conductive structures in the semiconductor structure 464, including trench structures 466 and one or more channel structures 468. The non-active die 408a can be manufactured from a semiconductor wafer and is formed in the trench structures 466 and channel structures 468 in the semiconductor structure 464 (which may correspond to a portion of the semiconductor wafer) through multiple processes.

[0134] The trench structure 466 and channel structure 468 may include increased structural rigidity of the non-active die 408a, thereby providing increased structural rigidity for the semiconductor die package 402. Additionally and / or alternatively, the trench structure 466 and channel structure 468 may include providing a heat conduction path for thermal manufacturing in a portion 460 of the active integrated circuit die 404. Additionally and / or alternatively, the orientation of the active integrated circuit dies 404 and 406, combined with the trench structure 466 in the non-active die 408a, enables metal-to-metal bonding to form pads 454a in the trench structure 466 and in the active integrated circuit die 404, thereby enabling direct bonding between the non-active die 408a and the active integrated circuit die 404.

[0135] Each of the trench structure 466 and the channel structure 468 may include other electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au). In the non-active die 408a, the channel structure 468 may be located on one side adjacent to the non-active die 408a, with one side of the non-active die 408a facing away from the active integrated circuit die 406. In some embodiments, one or more pads 470 are included between the semiconductor structure 464, the trench structure 466, and the channel structure 468 of the non-active die 408a. The one or more pads 470 include a tantalum nitride (TaN) barrier layer, a titanium (Ti) or titanium nitride (TiN) barrier layer, and silicon oxide (SiO2). x Such as SiO2) pads and / or another suitable pad.

[0136] Further as Figure 4C As shown, the non-active grain 408b also includes a dielectric structure 472 (e.g., silicon oxide (SiO2)). x A thick film or another type of dielectric thick film) and conductive structures in the dielectric structure 472, including trench structures 474 and one or more channel structures 476. A non-active die 408b may be fabricated on and / or on the active integrated circuit die 404 to deposit the dielectric structure 472 on the active integrated circuit die 404 and then form the trench structures 474 and channel structures 476 in the dielectric structure 472.

[0137] The trench structure 474 and channel structure 476 may include increased structural rigidity of the non-active die 408b, thereby providing increased structural rigidity for the semiconductor die package 402. Additionally and / or alternatively, the trench structure 474 and channel structure 476 may include providing a heat conduction path for thermal manufacturing in a portion 462 of the active integrated circuit die 404. Additionally and / or alternatively, the orientation of the active integrated circuit dies 404 and 406, combined with the trench structure 474 in the non-active die 408b, enables metal-to-metal bonding to form pads 454a in the trench structure 474 and in the active integrated circuit die 404, thereby enabling direct bonding between the non-active die 408a and the active integrated circuit die 404.

[0138] The trench structure 474 and channel structure 476 may each include other electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au). In the non-active die 408b, the channel structure 476 may be located on one side adjacent to the non-active die 408a, with one side of the non-active die 408a facing away from the active integrated circuit die 406. In some embodiments, one or more pads 478 are included between the dielectric structure 472, trench structure 474, and channel structure 476 of the non-active die 408b. The one or more pads 478 include a tantalum nitride (TaN) barrier layer, a titanium (Ti) or titanium nitride (TiN) barrier layer, and silicon oxide (SiO2). x Such as SiO2) pads and / or another suitable pad.

[0139] Figure 4D The trench structure 466 is shown in the bottom view within the inactive grain 408a. For example... Figure 4D As shown, the trench structure 466 may include a plurality of through trenches arranged on a lattice. This forms a mesh pattern having through trench openings 480 formed in the trench structure 466. The lattice arrangement of the trench structure 466 can reduce the likelihood of recesses in the semiconductor structure 464 when the trench structure 466 is planarized. In some embodiments, the overall width of the trench structure 466 in the x-direction may include a range of approximately 3 micrometers to 7 micrometers. However, other values ​​in the range are within the scope of this disclosure. In some embodiments, the overall width of the trench structure 466 in the y-direction may include a range of approximately 3 micrometers to 7 micrometers. However, other values ​​in the range are within the scope of this disclosure.

[0140] Figure 4E The trench structure 474 is shown in the bottom view within the inactive grain 408b. For example... Figure 4EAs shown, the trench structure 474 may include a plurality of through trenches arranged in a lattice. This forms a mesh pattern having openings 482 formed in the through trenches of the trench structure 474. When the trench structure 474 is planarized, the lattice arrangement of the trench structure 474 can reduce the likelihood of recesses in the dielectric structure 472. In some embodiments, the overall width of the trench structure 474 in the x-direction may include a range of approximately 3 micrometers to 7 micrometers. However, other values ​​in the range are within the scope of this disclosure. In some embodiments, the overall width of the trench structure 474 in the y-direction may include a range of approximately 3 micrometers to 7 micrometers. However, other values ​​in the range are within the scope of this disclosure.

[0141] As indicated above, Figures 4A-4E This is provided as an example. Other examples can be found from [link to relevant information]. Figures 4A-4E The descriptions are used to distinguish them.

[0142] Figures 5A-5E This is an example 500 of a semiconductor die package 502 described herein. The semiconductor die package 502 includes a packaged semiconductor device, which includes a plurality of active integrated circuit dies or wafers. The plurality of active integrated circuit dies may be vertically arranged and / or stacked in the semiconductor die package 502 using three-dimensional packaging techniques such as direct bonding.

[0143] like Figures 5A-5E As shown, the semiconductor die package 502 includes similar combinations and arrangements of layers and / or structures 504-582 as described above. Figures 4A-4E The layers and / or structures 404-482 of the semiconductor die package 402 described and illustrated. The layers and / or structures 504-582 of the semiconductor die package 502 can be formed using similar technologies and / or processes in relation to... Figures 3A-3T Those descriptions.

[0144] However, as Figure 5B As shown, the vertical (z-direction) orientation of the trench structure 566 and the channel structure 568 is flipped, so that the channel structure 568 is bonded to the pad 554a in the active integrated circuit die 504. Similarly, as... Figure 5C As shown, the vertical (z-direction) orientation of the trench structure 574 and the channel structure 576 is flipped so that the channel structure 576 is bonded to the pad 554a in the active integrated circuit die 504.

[0145] As mentioned above, Figures 5A-5E The diagram provides an example. Other examples can be found from [link to relevant information]. Figures 5A-5E Use descriptions to differentiate.

[0146] Figures 6A-6F The accompanying drawing is an example of a top view layout of the semiconductor die package described herein. Figure 6AThe accompanying drawings illustrate a top-view layout example 600 of the semiconductor die package 602 described herein. (See attached figures.) Figure 6A As shown, the semiconductor die package 602 includes, as in Example 600, Figure 1A The semiconductor die package 602 includes a similar combination and arrangement of dies. However, the semiconductor die package 602 includes a plurality of active integrated circuit dies 604a-604c that may be laterally adjacent to each other. Active integrated circuit die 606 may be included on and / or arranged perpendicularly to active integrated circuit die 604a. Non-active die 608a may be included on and / or arranged perpendicularly to active integrated circuit die 604b, and non-active die 608b may be included on and / or arranged perpendicularly to active integrated circuit die 604c. In other words, each of the active integrated circuit die 606 and the non-active dies 608a and 608b is included on and / or on different active integrated circuit dies. In Example 600, active integrated circuit die 606 and non-active die 608a are separated by a gap 610, active integrated circuit die 606 and non-active die 608b are separated by a gap 610, and non-active dies 608a and 608b are separated by a gap 610.

[0147] The passive dies 608a and 608b include non-active dies 608a and 608b that can be fabricated on and / or on different active integrated circuit dies to optimize the non-active dies 608a and 608b respectively for active integrated circuit dies 604b and 604c. The non-active dies 608a and 608b may include different materials (or different combinations of materials), structural arrangements with different levels and / or features, may include different combinations and device arrangements, and / or may have different top-view dimensions and / or shapes, etc. For example, active integrated circuit die 604b may include logic dies and active integrated circuit die 604c may include silicon photonic dies. Therefore, non-active die 608a may include a semiconductor non-active die that provides high thermal conductivity to dissipate heat from logic devices in the logic die; however, non-active die 608a may include a dielectric film that provides low thermal conductivity to maintain high operating temperatures in the silicon photonic die (e.g., including silicon photonic devices such as optical modulators that have more stable operation at high temperatures).

[0148] Active integrated circuit chips 604-604c and 606 may each include similar combinations and arrangements of layers and / or structures, such as for in Figure 1B , Figure 1C , Figure 4B , Figure 4C , Figure 5B and / or Figure 5CThe descriptions of one or more active integrated circuit dies, etc. Additionally and / or alternatively, each of the non-active dies 608a and 608b may include similar combinations and arrangements of layers and / or structures, as described in [the context of...]. Figure 1B , Figure 1C , Figure 4B , Figure 4C , Figure 5B , Figure 5C , Figure 5D and / or Figure 5E The descriptions of one or more non-active integrated circuit dies, etc. The layers of the semiconductor die package 602 can be formed using similar technologies and / or processes as described in those concerning... Figures 3A-3T describe.

[0149] like Figure 6B As shown, example 612 of the top-view layout for a non-active device in a semiconductor die package 602 includes a similar top-view layout as shown below. Figure 6A Except that the non-active dies 608a and 608b are substantially in contact along adjacent edges, the adjacent edges are generally perpendicular to the edges of the non-active dies 608a and 608b adjacent to the active integrated circuit die 606.

[0150] like Figure 6C As shown, example 614 of the top-view layout for the non-active device in the semiconductor die package 602 includes a similar top-view layout as... Figure 6A In addition to having different top-view dimensions, the non-active dies 608a and 608b can have different top-view dimensions, allowing the non-active die 608b to be located, for example, on a portion of the active integrated circuit die 604b. Therefore, the non-active die 608b can be configured to optimize thermal and / or partial structural performance of the active integrated circuit die 604b, in addition to being configured to optimize thermal and / or structural performance for the active integrated circuit die 604c.

[0151] like Figure 6D As shown, example 616 of the top-view layout of non-active dies in semiconductor die package 602 includes a similar top-view arrangement such as Figure 6A The description includes, except that another non-active die 608c is included on and / or on the active integrated circuit die 604c. A non-active die 608b spans portions of active integrated circuit dies 604b and 604c and is included above portions of active integrated circuit dies 604b and 604c. Other numbers of non-active dies are also described in this disclosure. Increasing the number of non-active dies, as in... Figure 6D Example 616 enables increased flexibility in adjusting different portions or regions of the active integrated circuit dies 604b and 604c, thereby increasing performance in the heat pipe and / or structural integration of the semiconductor die package 602.

[0152] like Figure 6E As shown, Example 618 of the top-view layout of a non-active die in a semiconductor die package 602 includes, as... Figure 6D The described top-view layout, except that two or more non-active dies 608a-608c have different top-view dimensions and are all housed around the same active integrated circuit die, allows for greater flexibility in adjusting the non-active dies 608b and 608c for different portions or regions of the active integrated circuit die 604c.

[0153] like Figure 6F Example 620 of the top-view layout of a non-active die in a semiconductor die package 602 includes, for example: Figure 6E The described top-view layout, except that the non-active grains 608a-608c are arranged in the x-direction in contrast to those arranged in the x-direction... Figure 6E The example shows the non-active dies 608a-608c in the y-direction. Other combinations of x-direction and / or y-direction arrangements are within the scope of this disclosure and can increase flexibility in adjusting the non-active dies for different portions or regions of the active integrated circuit dies 604b and / or 604c, thereby increasing thermal management performance and / or structural integration of the semiconductor die package 602.

[0154] As mentioned above, Figures 6A-6F This is provided as an example. Other examples can be found from [link to relevant information]. Figures 6A-6E The descriptions are used to distinguish them.

[0155] Figure 7 This is a flowchart of an example process 700 for forming the semiconductor die package described herein. In some embodiments, in Figure 7 One or more process blocks in the process are executed using one or more semiconductor process tools, such as deposition tools, exposure tools, development work, etching tools, planarization work, ion implantation tools, annealing tools, bonding tools, wafer / die transfer tools and / or another type of semiconductor process tool.

[0156] like Figure 7 As shown, process 700 may include attaching a first active integrated circuit die to a first side of a carrier substrate (block 710). For example, one or more semiconductor process tools may be used to attach the first side of a first active integrated circuit die (e.g., active integrated circuit die 104, active integrated circuit die 404, active integrated circuit die 504) to a carrier substrate described herein (e.g., carrier substrate 304).

[0157] Further as Figure 7As shown. Process 700 may include bonding a second active integrated circuit die to a second side of the first active integrated circuit die opposite to the first side, such that the first and second active integrated circuit dies are stacked and vertically arranged in the semiconductor die package described herein (block 720). For example, one or more semiconductor process tools may be used to bond the second active integrated circuit die (e.g., active integrated circuit die 106, active integrated circuit die 406, active integrated circuit die 506) to a second side opposite to the first side of the first active integrated circuit die, such that the first and second active integrated circuit dies are stacked and vertically arranged in the semiconductor die package described herein (e.g., semiconductor die package 102, semiconductor die package 402, semiconductor die package 502).

[0158] Further as Figure 7 As shown, process 700 may include a first non-active die provided on a second side of the first active integrated circuit die, such that the first non-active die is spaced apart from and laterally adjacent to the second active integrated circuit die (block 730). For example, one or more semiconductor process tools may be used to provide a first non-active die (such as non-active die 108a, non-active die 408a, non-active die 508a) on a second side of the first active integrated circuit die, such that the first non-active die is spaced apart from and laterally adjacent to the second active integrated circuit die described herein.

[0159] Further as Figure 7 As shown, process 700 may include a second non-active die provided on a second side of the first active integrated circuit die, such that the second non-active die is laterally adjacent to the first non-active die and is spaced apart from and laterally adjacent to the second active integrated circuit die (block 740). For example, one or more semiconductor process tools may be used to provide a second non-active die (e.g., non-active die 108b, non-active die 408b, non-active die 508b) on a second side of the first active integrated circuit die such that the second non-active die is laterally adjacent to the first non-active die and is spaced apart from and laterally adjacent to the second active integrated circuit die described herein.

[0160] Further as Figure 7 As shown, process 700 may include forming a dielectric filling layer surrounding a second active integrated circuit die, a first non-active die, and a second non-active die (block 750). For example, one or more semiconductor process tools may be used to form dielectric filling layers (e.g., dielectric filling layer 114b, dielectric filling layer 414b, dielectric filling layer 514b) surrounding the second active integrated circuit die, the first non-active integrated circuit die, and the second non-active integrated circuit die described herein.

[0161] Process 700 may include additional implementations, such as any of the implementations or any descriptions below and / or with respect to one or more processes described elsewhere.

[0162] In a first embodiment, providing a first non-active die on a second side of a first active integrated circuit die includes placing the non-active die on the second side of the first active integrated circuit die.

[0163] In a second embodiment, providing a second non-active die on a second side of the first active integrated circuit die, alone or in combination with the first embodiment, includes depositing a non-active die, such as a film, on the second side of the first active integrated circuit die.

[0164] In a third embodiment, a first non-active die provided on a second side of the first active integrated circuit die, alone or in combination with one or more of the first and second embodiments, includes a conductive trench structure (e.g., conductive trench structure 466) in the first non-active die bonded to a pad (e.g., pad 554a) in the first active integrated circuit die.

[0165] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the conductive trench structure includes a plurality of internal conductive trenches arranged in a grid.

[0166] In the fifth embodiment, a first non-active die combination on the second side of the first active integrated circuit die is provided, alone or in combination with one or more of the first to fourth embodiments, to bond a conductive channel structure (e.g., conductive channel structure 568) in the first non-active die to a bonding pad (e.g., bonding pad 554a) in the first active integrated circuit die.

[0167] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 700 includes forming a conductive channel structure in at least one of the semiconductor layers or in the dielectric layer of the first non-active grain and forming a conductive trench structure (e.g., conductive trench structure 566) such that the conductive trench structure is coupled to the conductive channel structure.

[0168] Although Figure 7 The example blocks of process 700 are shown. In some embodiments, process 700 includes additional blocks, fewer blocks, different blocks, or blocks with different arrangements compared to those in... Figure 7 The description. Additionally or alternatively, two or more blocks of process 700 can be executed in parallel.

[0169] Figure 8 This is a flowchart of an example process 800 for forming the semiconductor die package described herein. In some embodiments, Figure 8One or more process blocks are executed using one or more process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, bonding tools, wafer / die transfer tools and / or another type of semiconductor process tool.

[0170] like Figure 8 As shown, process 800 may include attaching a first side of a first active integrated circuit die to a carrier substrate (block 810). For example, one or more semiconductor tools may be used to attach the first side of a first active integrated circuit die (such as active integrated circuit die 604a) to a carrier substrate (such as carrier substrate 304), as described herein.

[0171] like Figure 8 As shown, process 800 may include a first side of a carrier substrate (block 820) on which a first active integrated circuit die is attached. For example, one or more semiconductor tools may be used to attach the first side of a first active integrated circuit die (such as active integrated circuit die 604b) to a carrier substrate (such as carrier substrate 304) as described herein. In some embodiments, the first active integrated circuit die and the second active integrated circuit die are laterally adjacent to each other on the carrier substrate.

[0172] like Figure 8 As shown, process 800 may include attaching a first side of a first active integrated circuit die to a carrier substrate (block 830). For example, one or more semiconductor tools may be used to attach the first side of a first active integrated circuit die (such as active integrated circuit die 604c) to a carrier substrate (such as carrier substrate 304) as described herein. In some embodiments, the first active integrated circuit die and the second active integrated circuit die are laterally adjacent to each other on the carrier substrate.

[0173] Further as Figure 8 As shown, process 800 may include bonding a fourth active integrated circuit die to a second side of the first active integrated circuit die opposite to the first side, such that the first and fourth active integrated circuit dies are stacked and vertically arranged in a semiconductor die package (block 840). For example, one or more semiconductor process tools may be used to bond a fourth active integrated circuit die (e.g., active integrated circuit die 606) to a second side of the first active integrated circuit die opposite to the first side, such that the first and fourth active integrated circuit dies are stacked and vertically arranged in a semiconductor die package (e.g., semiconductor die package 602) as described herein.

[0174] Further as Figure 8As shown, process 800 may include providing a first non-active die on a second side of a second active integrated circuit die opposite to the first side, such that the second active integrated circuit die and the first non-active die are stacked and vertically arranged in a semiconductor die package (block 850). For example, one or more semiconductor process tools may be used to provide a first non-active die (e.g., non-active die 608a) to a second side of a second active integrated circuit die opposite to the first side, such that the second active integrated circuit die and the first non-active die are stacked and vertically arranged in a semiconductor die package as described herein. In some embodiments, the first non-active die is laterally adjacent to and spaced from a fourth active integrated circuit die.

[0175] Further as Figure 8 As shown, process 800 may include providing a second passive die on a second side of a third active integrated circuit die, such that the third active integrated circuit die and the second passive die are stacked and vertically arranged in a semiconductor die package (block 860). For example, one or more semiconductor process tools may be used to provide a second passive die (e.g., passive die 608b) on a second side of the third active integrated circuit die, such that the third active integrated circuit die and the second passive die are stacked and vertically arranged in a semiconductor die package as described herein. In some embodiments, the second passive die is laterally adjacent to and spaced from a fourth active integrated circuit die.

[0176] Process 800 may include additional implementations, such as any single implementation or any combination of implementations described below and / or with regard to one or more other process descriptions elsewhere.

[0177] In the first embodiment, a portion of the second non-active die is also located on top and arranged perpendicularly to the second active integrated circuit die.

[0178] In a second embodiment, either alone or with respect to the first embodiment, process 800 includes providing a third non-active die (such as non-active die 608c) arranged on and perpendicular to a third active integrated circuit die, the third non-active die being laterally adjacent to the second non-active die.

[0179] In the third embodiment, each of the first inactive grain, the second inactive grain, and the third inactive grain, individually or with respect to one of the first or second embodiments, comprises a different combination of materials.

[0180] In the fourth embodiment, individually or with respect to one of the first to third embodiments, the top view area of ​​the second non-active die and the top view area of ​​the third non-active die are substantially the same top view area, and the top view area of ​​the first non-active die is different from the top view area of ​​the second non-active die and the top view area of ​​the third non-active die.

[0181] In the fifth embodiment, individually or in relation to any one of the first to fourth embodiments, the second active integrated circuit die includes a logic die, the third active integrated circuit die includes a silicon photonic die, the first non-active die includes a semiconductor non-active die, and the second non-active die includes a dielectric film.

[0182] Although Figure 8 Examples illustrating process 800, in some embodiments, process 800 includes additional blocks, fewer blocks, different blocks, or blocks with different arrangements compared to those in... Figure 8 The description.

[0183] In this method, a substantially smaller first integrated circuit die is directly bonded to a substantially larger second integrated circuit die and vertically arranged within a semiconductor die package. The smaller substantial size of the first integrated circuit die allows multiple passive dies to be placed on top of the second integrated circuit die in areas not occupied by the first integrated circuit die. Including multiple passive dies allows for customization of the passive dies to different properties for different regions of the second integrated circuit. For example, different passive dies can be manufactured with different heat dissipation distributions for different regions of the second integrated circuit die with different thermal requirements. As another example, different passive dies can be manufactured to occupy different proportions of thermal expansion and contraction within the second integrated circuit. In this method, including multiple passive dies in the semiconductor die package increases the thermal stability of the semiconductor die package, which can lead to increased operating life for the integrated circuit die, reducing the likelihood of integrated circuit die failure and / or increasing the overall reliability of the semiconductor die package, etc.

[0184] As described above in more detail, some embodiments described herein provide a semiconductor die package. The semiconductor die package includes a first active integrated circuit die. The semiconductor die package includes a second active integrated circuit die over a first portion of the first active integrated circuit die. The semiconductor die package includes a first passive die over a second portion of the first active integrated circuit die. The semiconductor die package includes a second passive die over a third portion of the first active integrated circuit die, the second active integrated circuit die, the first passive die, and the second passive die being located on the same side of the first active integrated circuit die. In some embodiments, the first passive die and the second passive die are spaced apart by a gap. The semiconductor die package also includes a dielectric filling layer. The dielectric filling layer surrounds the second active integrated circuit, the first passive die, and the second passive die. The dielectric filling layer is included in the gap between the first passive die and the second passive die. In some embodiments, the first passive die and the second passive die are in contact along a first side of the first passive die and a second side of the second passive die. In some embodiments, the third side of the second active integrated circuit die is the fourth side adjacent to the first passive die. The third side of the second active integrated circuit die is the fifth side adjacent to the second passive die. In some embodiments, the first passive die includes a semiconductor passive die having a semiconductor structure. The second passive die includes a dielectric passive die having a dielectric structure. In some embodiments, the first passive die is adjacent to the first side of the second active integrated circuit die. The second passive die is the second side of the second active integrated circuit die facing away from the first side. In some embodiments, a third passive die is included, which is located on the fourth portion of the first active integrated circuit die. The first passive die, the second passive die, and the third passive die are of different sizes.

[0185] As described above in more detail, some embodiments described herein provide a method for forming a semiconductor die package. The method for forming a semiconductor die package includes attaching a first side of a first active integrated circuit die to a carrier substrate. This method includes bonding a second active integrated circuit die to a second side of the first active integrated circuit die opposite to the first side, such that the first and second active integrated circuit dies are stacked and vertically arranged in the semiconductor die package, and providing a first non-active die on the second side of the first active integrated circuit die, such that the first non-active die is spaced apart and laterally adjacent to the second active integrated circuit die. This method includes providing a second non-active die on the second side of the first active integrated circuit die, such that the second non-active die is spaced apart and laterally adjacent to the second active integrated circuit die. This method includes forming a dielectric fill layer surrounding the second active integrated circuit die, the first non-active die, and the second non-active die. In some embodiments, the first non-active die is provided on the second side of the first active integrated circuit die. The non-active die is placed on the second side of the first active integrated circuit die. In some embodiments, a second non-active die is provided on the second side of the first active integrated circuit die. A film is deposited on a non-active die as a second side of a first active integrated circuit die. In some embodiments, a first non-active die is provided on the second side of the first active integrated circuit die. A conductive trench structure in the first non-active die is bonded to a bonding pad in the first active integrated circuit die. In some embodiments, the conductive trench structure includes a plurality of interconnect conductive trenches, and the interconnect conductive trenches are arranged in a grid. In some embodiments, a first non-active die is provided on the second side of the first active integrated circuit die. A conductive channel structure in the first non-active die is bonded to a bonding pad in the first active integrated circuit die. In some embodiments, a conductive channel structure is formed in at least one of a semiconductor layer or a dielectric layer of the first non-active die. The conductive trench structure is formed such that the conductive trench structure is coupled to the conductive channel structure.

[0186] As described above in more detail, some embodiments described herein provide a semiconductor die package. The semiconductor die package includes a first active integrated circuit die. The semiconductor die package includes a second active integrated circuit die laterally adjacent to the first active integrated circuit die. The semiconductor die package includes a third active integrated circuit die laterally adjacent to both the first and second active integrated circuit dies. The semiconductor die package includes a fourth active integrated circuit die arranged on top of and perpendicular to the first active integrated circuit die. The semiconductor die package includes a first non-active die on the second active integrated circuit die and arranged perpendicular to it. The semiconductor die package includes a second non-active die on the third active integrated circuit die and arranged perpendicular to it. In some embodiments, a portion of the second non-active die is also located and arranged perpendicularly on the second active integrated circuit die. In some embodiments, a third non-active die is included, located and arranged perpendicularly on the third active integrated circuit die. The third non-active die is laterally adjacent to the second non-active die. In some embodiments, the first passive die, the second passive die, and the third passive die comprise different material compositions. In some embodiments, the top view regions of the second passive die and the third passive die have substantially the same top view region. The top view region of the first passive die is different from the top view regions of the second and third passive dies. In some embodiments, the second active integrated circuit die comprises a logic die. The third active integrated circuit die comprises a silicon photonic die. The first passive die comprises a semiconductor passive die. The second passive die comprises a dielectric film.

[0187] As described above in more detail, a semiconductor die package includes a first active integrated circuit die, a second active integrated circuit die, a third active integrated circuit die, a fourth active integrated circuit die, a first passive die, and a second passive die. The second active integrated circuit die is laterally adjacent to the first active integrated circuit die. The third active integrated circuit die is laterally adjacent to both the first and second active integrated circuit dies. The fourth active integrated circuit die is vertically disposed on the first active integrated circuit die. The first passive die is vertically disposed on the second active integrated circuit die, and the second passive die is vertically disposed on the third active integrated circuit die, wherein a portion of the second passive die is also located on and vertically disposed on the second active integrated circuit die. In some embodiments, the semiconductor die package further includes a third passive die located on and vertically disposed on the third active integrated circuit die, wherein the third passive die is laterally adjacent to the second passive die.

[0188] The terms "probably" and "generally" may indicate values ​​for specific quantities that differ from the value by no more than 5% (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It is understood that the terms "probably" and "generally" may refer to the percentage of a specific quantity found in this disclosure.

[0189] The foregoing outline features of most embodiments enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that their various modifications, equivalents, and substitutions do not depart from the spirit and scope of this disclosure.

Claims

1. A semiconductor die package, comprising: include: The first active integrated circuit die; A second active integrated circuit die is located on a first portion of the first active integrated circuit die; A first non-active die, on a second portion of the first active integrated circuit die; and A second non-active die is located on a third portion of the first active integrated circuit die. The second active integrated circuit die, the first non-active die, and the second non-active die are located on the same side of the first active integrated circuit die.

2. The semiconductor die package of claim 1, wherein, The first inactive grain and the second inactive grain are separated by a gap; and The semiconductor die package further includes a dielectric filling layer surrounding the second active integrated circuit, the first passive die, and the second passive die. The dielectric filling layer is included in the gap between the first inactive grain and the second inactive grain.

3. The semiconductor die package as described in claim 1, characterized in that, The first passive grain and the second passive grain are in contact along a first side of the first passive grain and a second side of the second passive grain.

4. The semiconductor die package of claim 3, wherein, Wherein a third side of the second active integrated circuit die is a fourth side adjacent to the first non-active die; and The third side of the second active integrated circuit die is a fifth side adjacent to the second non-active die.

5. The semiconductor die package of claim 1, wherein, It also includes a third non-active die, which is located on a fourth portion of the first active integrated circuit die. The first inactive grain, the second inactive grain, and the third inactive grain are of different sizes.

6. A semiconductor die package, comprising: include: The first active integrated circuit die; A second active integrated circuit die is laterally adjacent to the first active integrated circuit die; A third active integrated circuit die is laterally adjacent to the first active integrated circuit die and laterally adjacent to the second active integrated circuit die; A fourth active integrated circuit die is vertically arranged on the first active integrated circuit die; A first non-active die is vertically arranged on the second active integrated circuit die; and A second non-active die is vertically arranged on the third active integrated circuit die.

7. The semiconductor die package as described in claim 6, characterized in that, It also includes a third non-active die, which is located and vertically arranged on the third active integrated circuit die. The third non-active grain is laterally adjacent to the second non-active grain.

8. The semiconductor die package as described in claim 7, characterized in that, The upper viewing regions of the second non-active die and the third non-active die have substantially the same upper viewing region; and The top view area of ​​the first non-active die is different from the top view area of ​​the second non-active die and the top view area of ​​the third non-active die.

9. A semiconductor die package, comprising: include: The first active integrated circuit die; A second active integrated circuit die is laterally adjacent to the first active integrated circuit die; A third active integrated circuit die is laterally adjacent to the second active integrated circuit die; A fourth active integrated circuit die is vertically arranged on the first active integrated circuit die; A first non-active die is vertically arranged on the second active integrated circuit die; and A second non-active die is vertically arranged on the third active integrated circuit die, wherein a portion of the second non-active die is also located on and vertically arranged on the second active integrated circuit die.

10. The semiconductor die package of claim 9, wherein the semiconductor die package is a flip chip semiconductor die package. It also includes a third non-active die, which is located and vertically arranged on the third active integrated circuit die. The third non-active grain is laterally adjacent to the second non-active grain.

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