Multipath interconnection system and computer equipment
By designing a multi-way interconnect system and utilizing the connection channels between computing acceleration entities and interface switching chips, high-speed data exchange between multiple computing units was achieved, solving the multi-way interconnection requirement in high-performance computer systems and realizing efficient data transmission and communication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HYGON INFORMATION TECH CO LTD
- Filing Date
- 2025-05-14
- Publication Date
- 2026-05-05
AI Technical Summary
How to provide a multi-way interconnect system to meet the high-speed data exchange needs between multiple computing units, especially in computer systems with high computing power requirements.
Design a multi-way interconnect system including multiple computing acceleration entities and interface switching chips. The interconnection between the computing acceleration entities and the interface switching chips is realized through connection channels. It supports multiple ports of the memory interconnect bus and uses the interface switching chips for communication relay to realize the interconnection between multiple computing units.
It enables efficient data transmission and communication between multiple computing units, meeting the interconnection requirements of high-performance computer systems.
Smart Images
Figure CN224203684U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of processor technology, specifically to a multi-way interconnect system and computer device. Background Technology
[0002] The processor motherboard is the core hardware platform of a computer system, primarily used to connect and coordinate the computer system's computing units, processors, and other IP (Intellectual Property) components to ensure the operation and communication of the computer system. Computing units are IP components designed within a computer system to perform specific computational tasks. For example, taking a deep learning computing unit as an example, a deep learning computing unit is an IP component in a computer system specifically designed to perform deep learning and machine learning tasks.
[0003] With the development of artificial intelligence technology, the demand for computing power is increasing, requiring processor motherboards to incorporate multiple computing units to meet the demands of higher-density computing. To achieve high-speed data exchange between these multiple computing units, a topology connecting them, known as a multiplexed interconnect system, is needed. Against this backdrop, how to provide a multiplexed interconnect system to meet the interconnection requirements between multiple computing units has become a critical technical problem that needs to be solved by those skilled in the art. Utility Model Content
[0004] In view of this, embodiments of this application provide a multi-way interconnection system and computer device that can meet the interconnection needs between multiple computing units.
[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.
[0006] In a first aspect, embodiments of this application provide a multi-path interconnection system, the multi-path interconnection system comprising:
[0007] Multiple computing acceleration entities, wherein the computing acceleration entity is a standardized entity unit for integrating computing units, the computing acceleration entity includes computing units, and the computing units include multiple first ports supporting a memory interconnect bus;
[0008] Multiple interface switching chips, each interface switching chip including multiple second ports, the second ports being matched with the first ports;
[0009] The connection channel connects the first port of the computing acceleration entity and the second port of the interface switching chip.
[0010] Each computing acceleration entity has multiple connection channels that are respectively connected to the multiple interface switching chips.
[0011] Optionally, the number of multiple first ports of a computing acceleration entity is greater than the number of multiple interface switching chips; wherein the multiple first ports include: at least one independent first port and at least one group of first ports, wherein the group of first ports includes at least two first ports;
[0012] A computation acceleration entity may have multiple connectivity channels, including:
[0013] Each group of first ports corresponds to a connection channel, wherein each group of first ports is connected to an interface switching chip;
[0014] Each independent first port corresponds to a connection channel, and one independent first port connects to one interface switching chip.
[0015] Optionally, the first port is a Serdes port, and the plurality of first ports include: a zeroth Serdes port, a first Serdes port, a second Serdes port, a third Serdes port, a fourth Serdes port, a fifth Serdes port, and a sixth Serdes port;
[0016] Wherein, the at least one independent first port is the sixth Serdes port, and the at least one group of first ports includes the first group of first ports corresponding to the zeroth Serdes port and the first Serdes port, the second group of first ports corresponding to the second Serdes port and the third Serdes port, and the third group of first ports corresponding to the fourth Serdes port and the fifth Serdes port.
[0017] Optionally, the number of multiple first ports of a computing acceleration entity is equal to the number of multiple interface switching chips, wherein the multiple connection channels of a computing acceleration entity include:
[0018] A one-to-one connection channel corresponding to each of the plurality of interface switching chips, wherein a first port of a computing acceleration entity is connected to a second port of an interface switching chip.
[0019] Optionally, the first port is a Serdes port, and the plurality of first ports include: a zeroth Serdes port, a first Serdes port, a second Serdes port, a third Serdes port, a fourth Serdes port, a fifth Serdes port, and a sixth Serdes port; one first port corresponds to a one-to-one connection channel of one interface switching chip.
[0020] Optionally, the plurality of computing acceleration entities are arranged in one or more rows.
[0021] Optionally, the computing unit further includes a third port and a fourth port; the third port supports a PCIe bus and a memory interconnect bus between the computing unit; the fourth port supports a PCIe bus, and the PCIe bus supported by the third port and the fourth port has different bit widths.
[0022] The multiplexed system also includes: multiple PCIe retimers, one of which is connected to the fourth port of a compute acceleration entity.
[0023] Optionally, the multiplexed interconnect system further includes: multiple PCIe connectors, with one PCIe retimer connected to one PCIe connector.
[0024] Optionally, the multiplexing system further includes:
[0025] External connector, the plurality of PCIe retimers are connected to the external connector;
[0026] Computing unit management controller and field-programmable gate array (FPGA) chip;
[0027] The computing unit management controller is connected to the field-programmable gate array (FPGA) chip via a PCIe bus and / or an I2C bus; both the computing unit management controller and the FPGA chip are connected to the external connector via an I2C bus.
[0028] Secondly, embodiments of this application provide a computer device, the computer device including the multiplexing system as described above.
[0029] The multi-channel interconnect system provided in this application includes: multiple computing acceleration entities, each computing acceleration entity being a standardized entity unit for integrating computing units, each computing acceleration entity including a computing unit, the computing unit including multiple first ports supporting a memory interconnect bus; multiple interface switching chips, each interface switching chip including multiple second ports, the second ports matching the first ports; and connection channels connecting the first ports of the computing acceleration entities and the second ports of the interface switching chips; wherein any computing acceleration entity has multiple connection channels respectively connected to the multiple interface switching chips.
[0030] As can be seen, the multi-path interconnection system provided in this application includes multiple computing acceleration entities integrating computing units, and multiple interface switching chips for interconnecting multiple computing acceleration entities to achieve interconnection of multiple computing units. Each computing unit carried by a computing acceleration entity includes multiple first ports supporting a memory interconnect bus, and each interface switching chip includes multiple second ports, with the second ports matching the first ports. Furthermore, this application embodiment can achieve separate connections between any computing acceleration entity and each interface switching chip through connection channels connecting the first ports of the computing acceleration entities and the second ports of the interface switching chips. This allows multiple computing acceleration entities to communicate via multiple interface switching chips, achieving interconnection between multiple computing acceleration entities and thus interconnection between multiple computing units carried by multiple computing acceleration entities. In other words, in this application embodiment, each computing acceleration entity has multiple connection channels respectively connected to the multiple interface switching chips. Therefore, any computing acceleration entity can interconnect with any other computing acceleration entity through the multiple interface switching chips, thereby achieving interconnection between multiple computing units, meeting the interconnection requirements between multiple computing units, and enabling data transmission and communication. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of the structure of a processor motherboard provided in an embodiment of this application;
[0033] Figure 2 This is a schematic diagram of an optional structure of the multi-way interconnection system provided in the embodiments of this application;
[0034] Figure 3 This is a schematic diagram of another optional structure of the multi-way interconnection system provided in the embodiments of this application;
[0035] Figure 4 This is another optional structural diagram of the multi-way interconnection system provided in the embodiments of this application;
[0036] Figure 5 This is another optional structural diagram of the multi-way interconnection system provided in the embodiments of this application. Detailed Implementation
[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0038] In computer systems, computation acceleration entities, as standardized unit entities, can be used to integrate computational units (such as deep computing units) to provide high-performance computational acceleration. For example, a computation acceleration entity can integrate one or more computational units (such as deep computing units), so that the computational units (such as deep computing units) integrated by multiple computation acceleration entities are responsible for managing the data flow and processing logic of computational tasks such as deep learning and machine learning tasks, and optimizing the execution of computational tasks.
[0039] In this embodiment, the computational acceleration entity can be an OAM (OCP Accelerator Module), a standard hardware module designed specifically for accelerating computational tasks such as artificial intelligence and machine learning. For ease of understanding, Figure 1 This illustration shows a schematic diagram of a processor motherboard provided in an embodiment of this application. (Refer to...) Figure 1 The motherboard has multiple computing acceleration entities (taking OAM as an example), and each computing acceleration entity integrates a computing unit.
[0040] When computing units (e.g., deep computing units) are integrated into computing acceleration entities, there is an interconnection requirement between the computing units integrated into multiple computing acceleration entities (e.g., between deep computing units). This necessitates constructing a topology connecting these multiple computing units, known as a multiplexed interconnect system. Therefore, providing a multiplexed interconnect system to meet the interconnection requirements between multiple computing units and to provide a foundation for data transmission between them is particularly important.
[0041] In view of this, embodiments of this application provide a multi-way interconnection system that can meet the interconnection requirements between multiple computing units, so as to perform data transmission and communication between multiple computing units.
[0042] The multi-channel interconnection system provided in the embodiments of this application will now be described with reference to the accompanying drawings.
[0043] Figure 2 This is a schematic diagram of an optional structure of the multi-channel interconnection system provided in an embodiment of this application. For example... Figure 2 As shown, the multiplex interconnect system may include the following.
[0044] Multiple computing acceleration entities, wherein the computing acceleration entity is a standardized entity unit for integrating computing units, the computing acceleration entity including computing units, the computing units including multiple first ports supporting memory interconnect buses.
[0045] The memory interconnect bus between computing units refers to the bus used for memory access and data exchange between computing units (such as between deep computing units), allowing different computing units (such as different deep computing units) to share and access each other's memory resources.
[0046] It should be noted that the computing unit refers to a basic unit in a computer hardware architecture, responsible for performing specific computing tasks such as arithmetic, logical operations, and data transmission. For example, the computing unit could be a deep computing unit, responsible for performing computing tasks such as deep learning and machine learning; for instance, taking OAM as a computing acceleration entity, the deep computing unit integrated into OAM can be used to perform computing tasks such as artificial intelligence and deep learning.
[0047] Multiple interface switching chips, each interface switching chip including multiple second ports, the second ports being matched with the first ports.
[0048] A connection channel connects a first port of a computing acceleration entity to a second port of an interface switching chip; wherein each computing acceleration entity has multiple connection channels that are respectively connected to the plurality of interface switching chips.
[0049] In this embodiment, the first port of the computing unit matches the second port of the interface switching chip, and there is a connection channel between the first port and the second port for connection; thus, multiple interface switching chips can connect multiple computing acceleration entities through multiple connection channels, playing a relay function between multiple computing acceleration entities; that is, any computing acceleration entity can connect to the multiple interface switching chips, and then connect to other computing acceleration entities through the link switching inside the multiple interface switching chips, thereby realizing the interconnection between the multiple computing units carried by the multiple computing acceleration entities.
[0050] As can be seen, the multi-path interconnection system provided in this application includes multiple computing acceleration entities integrating computing units, and multiple interface switching chips for interconnecting multiple computing acceleration entities to achieve interconnection of multiple computing units. Each computing unit carried by a computing acceleration entity includes multiple first ports supporting a memory interconnect bus, and each interface switching chip includes multiple second ports, with the second ports matching the first ports. Furthermore, this application embodiment can achieve separate connections between any computing acceleration entity and each interface switching chip through connection channels connecting the first ports of the computing acceleration entities and the second ports of the interface switching chips. This allows multiple computing acceleration entities to communicate via multiple interface switching chips, achieving interconnection between multiple computing acceleration entities and thus interconnection between multiple computing units carried by multiple computing acceleration entities. In other words, in this application embodiment, each computing acceleration entity has multiple connection channels respectively connected to the multiple interface switching chips. Therefore, any computing acceleration entity can interconnect with any other computing acceleration entity through the multiple interface switching chips, thereby achieving interconnection between multiple computing units, meeting the interconnection requirements between multiple computing units, and enabling data transmission and communication.
[0051] As an optional implementation, the number of multiple first ports of a computing acceleration entity may be greater than the number of multiple interface switching chips; wherein the multiple first ports include: at least one independent first port and at least one group of first ports, wherein the group of first ports includes at least two first ports.
[0052] Accordingly, a computing acceleration entity may have multiple connection channels, including: connection channels corresponding to each group of first ports, wherein each group of first ports is connected to an interface switching chip; and connection channels corresponding to an independent first port, wherein an independent first port is connected to an interface switching chip.
[0053] In an optional implementation, different computing acceleration entities are interconnected through interface switching chips. This interconnection can be achieved through interface switching chips connected to the independent first ports of each computing acceleration entity, or through interface switching chips connected to the respective groups of first ports of each computing acceleration entity.
[0054] In other words, in this embodiment, for a computing acceleration entity, the connection between a computing acceleration entity and an interface switching chip can be divided into: the computing acceleration entity connecting to an interface switching chip through a first port, and the computing acceleration entity connecting to the same interface switching chip simultaneously through at least two first ports; furthermore, the computing acceleration entity can connect to an interface switching chip through a connection channel corresponding to an independent first port, or connect to an interface switching chip through a group of first ports, so that the interface switching chip connected by multiple computing acceleration entities can perform link switching control to realize the interconnection of multiple computing units.
[0055] In one specific implementation, taking four computing acceleration entities as an example, and the first port including seven SerDes ports, the multiple interface switching chips may include four interface switching chips, as shown in the reference. Figure 3 , Figure 3 This is a schematic diagram of another optional structure of the multi-channel interconnection system provided in the embodiments of this application. For example... Figure 3 As shown, the multiple computing acceleration entities are OAM0, OAM1, OAM2 and OAM3, wherein each computing acceleration entity OAM integrates a computing unit (not shown in the figure).
[0056] For any computing unit, the computing unit may include multiple first ports, which may be Serdes (serializer / deserializer) ports. Specifically, the multiple first ports of a computing unit may include zeroth Serdes port G0, first Serdes port G1, second Serdes port G2, third Serdes port G3, fourth Serdes port G4, fifth Serdes port G5, and sixth Serdes port G6. For example, the computing unit integrated in OAM0 includes multiple first ports: zeroth Serdes port G0, first Serdes port G1, second Serdes port G2, third Serdes port G3, fourth Serdes port G4, fifth Serdes port G5, and sixth Serdes port G6. Similarly, each computing unit integrated in OAM1, OAM2, and OAM3 includes the above seven first ports.
[0057] It should be noted that the SerDes port is a type of port based on high-speed serial communication technology, supporting high-speed time division multiplexing (TDM) and point-to-point serial communication technologies. Specifically, at the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, transmitted through the transmission medium (optical fiber or copper wire), and finally converted back into low-speed parallel signals at the receiving end.
[0058] Further integration Figure 3 As shown, the plurality of interface switching chips may include: interface switching chip S0, interface switching chip S1, interface switching chip S2 and interface switching chip S3; the interface switching chip may include a plurality of second ports, the second ports may be PCIe ports, the plurality of second ports may include: PCIe port C0, PCIe port C1, PCIe port C2, PCIe port C3, PCIe port C4, PCIe port C5, PCIe port C6 and PCIe port C7.
[0059] In this embodiment, the interface switching chip may include multiple x16 PCIe interfaces, such as PCIe1, PCIe2, PCIe3, PCIe4, and PCIe5. Some PCIe interfaces may consist of two PCIe ports; that is, a PCIe interface providing 16 lanes of bandwidth can be divided into two parts, each providing 8 lanes of bandwidth, corresponding to two PCIe ports respectively. In an optional embodiment, refer to... Figure 3 The PCIe1 interface can be divided into PCIe port C0 and PCIe port C1, the PCIe2 interface can be divided into PCIe port C2 and PCIe port C3, the PCIe4 interface can be divided into PCIe port C4 and PCIe port C5, and the PCIe5 interface can be divided into PCIe port C6 and PCIe port C7.
[0060] In the optional implementation, continue to refer to Figure 3 The at least one independent first port can be the sixth Serdes port G6, and the at least one group of first ports includes: the first group of first ports corresponding to the zeroth Serdes port G0 and the first Serdes port G1, the second group of first ports corresponding to the second Serdes port G2 and the third Serdes port G3, and the third group of first ports corresponding to the fourth Serdes port G4 and the fifth Serdes port G5.
[0061] In this embodiment, the sixth Serdes port G6 of the computing acceleration entity supports configuration as a connection channel corresponding to an independent first port, with one independent first port connecting to one interface switching chip; wherein, each independent first port of the plurality of computing acceleration entities can connect to the same interface switching chip and to different second ports of the same interface switching chip; for example, referring to Figure 3The sixth Serdes port G6 of OAM0 connects to the PCIe port C5 of the interface switching chip S3; the sixth Serdes port G6 of OAM1 connects to the PCIe port C4 of the interface switching chip S3; the sixth Serdes port G6 of OAM2 connects to the PCIe port C3 of the interface switching chip S3; and the sixth Serdes port G6 of OAM3 connects to the PCIe port C2 of the interface switching chip S3.
[0062] Each computing acceleration entity OAM's sixth Serdes port G6 serves as an independent first port, allowing each computing acceleration entity to connect to the same interface switching chip S3 via the connection channel corresponding to its independent first port. The interface switching chip S3 then controls the internal link switching to enable the interconnection of any two computing acceleration entities, thus achieving interconnection between multiple computing units.
[0063] As an optional implementation, the zeroth Serdes port G0, the first Serdes port G1, the second Serdes port G2, the third Serdes port G3, the fourth Serdes port G4, and the fifth Serdes port G5 of the computing acceleration entity can be configured as multiple sets of connection channels corresponding to the first ports, and each set of first ports connects to one interface switching chip; for example, continuing to refer to Figure 3 Each computing acceleration entity's first group of first ports (zeroth Serdes port G0 and first Serdes port G1) is connected to interface switching chip S2; each computing acceleration entity's second group of first ports (second Serdes port G2 and third Serdes port G3) is connected to interface switching chip S1; and each computing acceleration entity's third group of first ports (fourth Serdes port G4 and fifth Serdes port G5) is connected to interface switching chip S0. Furthermore, when multiple computing acceleration entities have their same group of first ports connected to the same interface switching chip, the multiple computing acceleration entities can interconnect with each other through the switching control of the connected interface switching chips. Of course, connecting multiple computing acceleration entities' same group of first ports to the same interface switching chip is only an optional implementation. This application embodiment can also support different groups of first ports of different computing acceleration entities connecting to the same interface switching chip, as long as each computing acceleration entity is connected to multiple interface switching chips.
[0064] As can be seen, in this embodiment of the application, taking the interconnection of four computing units as an example, each computing acceleration entity has multiple connection channels that are respectively connected to the multiple interface switching chips. The multiple connection channels may include connection channels corresponding to each group of first ports and connection channels corresponding to independent first ports. Thus, any computing acceleration entity can interconnect with any other computing acceleration entity through the multiple interface switching chips, thereby realizing the interconnection between multiple computing units and meeting the interconnection requirements between multiple computing units for data transmission and communication.
[0065] In other alternative implementations, the number of multiple first ports of a computing acceleration entity may be equal to the number of multiple interface switching chips, wherein the multiple connection channels of a computing acceleration entity include:
[0066] A one-to-one connection channel corresponding to each of the plurality of interface switching chips, wherein a first port of a computing acceleration entity is connected to a second port of an interface switching chip.
[0067] In an optional implementation, different computing acceleration entities are interconnected through interface switching chips, which can be interconnected through interface switching chips connected to multiple first ports of each computing acceleration entity.
[0068] In other words, in this embodiment, for a computing acceleration entity and an interface switching chip, there is only one one-to-one connection channel between a first port and a second port; therefore, the computing acceleration entity can be connected to an interface switching chip through a one-to-one connection channel corresponding to a first port, so that the interface switching chip connected by multiple computing acceleration entities can perform link switching control to realize the interconnection of multiple computing units.
[0069] In one specific implementation, taking eight computing acceleration entities as an example, and the first port including seven SerDes ports, the multiple interface switching chips may include seven interface switching chips, as shown in the reference. Figure 4 , Figure 4 This is another optional structural diagram of the multi-way interconnection system provided in the embodiments of this application. For example... Figure 4 As shown, the multiple computing acceleration entities are OAM0, OAM1, OAM2, OAM3, OAM4, OAM5, OAM6, and OAM7, where each computing acceleration entity OAM integrates a computing unit (not shown in the figure).
[0070] For any given computing unit, the computing unit may include multiple first ports, which may be SerDes (serializer / deserializer) ports. For details, refer to... Figure 4The integrated unit in OAM0 includes multiple first ports: zeroth Serdes port G0, first Serdes port G1, second Serdes port G2, third Serdes port G3, fourth Serdes port G4, fifth Serdes port G5, and sixth Serdes port G6; similarly, each computing unit integrated in OAM0, OAM1, OAM2, OAM3, OAM4, OAM5, OAM6, and OAM7 includes the above seven first ports.
[0071] The plurality of interface switching chips may include: interface switching chip S0, interface switching chip S1, interface switching chip S2, interface switching chip S3, interface switching chip S4, interface switching chip S5, and interface switching chip S6; the interface switching chip may include a plurality of second ports, the second ports being PCIe ports, and the plurality of second ports may include: PCIe port C0, PCIe port C1, PCIe port C2, PCIe port C3, PCIe port C4, PCIe port C5, PCIe port C6, and PCIe port C7.
[0072] In this embodiment, the interface switching chip may include multiple x16 PCIe interfaces, such as PCIe1, PCIe2, PCIe3, PCIe4, and PCIe5. Some PCIe interfaces may consist of two PCIe ports; that is, a PCIe interface providing 16 lanes of bandwidth can be divided into two parts, each providing 8 lanes of bandwidth, corresponding to two PCIe ports respectively. In an optional embodiment, refer to... Figure 4 The PCIe1 interface can be divided into PCIe port C0 and PCIe port C1, the PCIe2 interface can be divided into PCIe port C2 and PCIe port C3, the PCIe4 interface can be divided into PCIe port C4 and PCIe port C5, and the PCIe5 interface can be divided into PCIe port C6 and PCIe port C7.
[0073] As an optional implementation, in this embodiment, to facilitate the connection layout between multiple computing acceleration entities and multiple interface switching chips, for each computing acceleration entity, the zeroth Serdes port, the first Serdes port, the second Serdes port, and the third Serdes port can be connected to the same second port of interface switching chip S0, interface switching chip S1, interface switching chip S2, and interface switching chip S3, respectively; the fourth Serdes port, the fifth Serdes port, and the sixth Serdes port can be connected to the same second port of interface switching chip S4, interface switching chip S5, and interface switching chip S6, respectively.
[0074] For example, refer to Figure 4 Taking OAM0 as an example, the connection between the multiple first ports and the second ports of each interface switching chip is as follows:
[0075] The zeroth Serdes port G0, the first Serdes port G1, the second Serdes port G2, and the third Serdes port G3 of the OAM0 are respectively connected to the same second port: PCIe port C0 of the interface switching chips S0, S1, S2, and S3.
[0076] The fourth Serdes port G4, the fifth Serdes port G5, and the sixth Serdes port G6 of the OAM0 are respectively connected to the same second port: PCIe port C4 of the interface switching chip S4, the interface switching chip S5, and the interface switching chip S6.
[0077] Taking OAM1 as an example, the connection between the multiple first ports and the second ports of each interface switching chip is as follows:
[0078] The zeroth Serdes port G0, the first Serdes port G1, the second Serdes port G2, and the third Serdes port G3 of OAM1 are respectively connected to the same second port: PCIe port C4 of interface switching chips S0, S1, S2, and S3.
[0079] The fourth Serdes port G4, the fifth Serdes port G5, and the sixth Serdes port G6 of the OAM1 are respectively connected to the same second port: PCIe port C0 of the interface switching chips S4, S5, and S6.
[0080] Taking OAM2 as an example, the connection between the multiple first ports and the second ports of each interface switching chip is as follows:
[0081] The zeroth Serdes port G0, the first Serdes port G1, the second Serdes port G2, and the third Serdes port G3 of OAM2 are respectively connected to the same second port: PCIe port C5 of interface switching chips S0, S1, S2, and S3.
[0082] The fourth Serdes port G4, the fifth Serdes port G5, and the sixth Serdes port G6 of the OAM2 are respectively connected to the same second port: PCIe port C1 of the interface switching chips S4, S5, and S6.
[0083] Taking OAM3 as an example, the connection between the multiple first ports and the second ports of each interface switching chip is as follows:
[0084] The zeroth Serdes port G0, the first Serdes port G1, the second Serdes port G2, and the third Serdes port G3 of the OAM3 are respectively connected to the same second port: PCIe port C1 of the interface switching chips S0, S1, S2, and S3.
[0085] The fourth Serdes port G4, the fifth Serdes port G5, and the sixth Serdes port G6 of the OAM3 are respectively connected to the same second port: PCIe port C5 of the interface switching chips S4, S5, and S6.
[0086] Taking OAM4 as an example, the connection between the multiple first ports and the second ports of each interface switching chip is as follows:
[0087] The zeroth Serdes port G0, the first Serdes port G1, the second Serdes port G2, and the third Serdes port G3 of the OAM4 are respectively connected to the same second port: PCIe port C2 of interface switching chips S0, S1, S2, and S3.
[0088] The fourth Serdes port G4, the fifth Serdes port G5, and the sixth Serdes port G6 of the OAM4 are respectively connected to the same second port: PCIe port C6 of the interface switching chips S4, S5, and S6.
[0089] Taking OAM5 as an example, the connection between the multiple first ports and the second ports of each interface switching chip is as follows:
[0090] The zeroth Serdes port G0, the first Serdes port G1, the second Serdes port G2, and the third Serdes port G3 of the OAM5 are respectively connected to the same second port: PCIe port C6 of the interface switching chips S0, S1, S2, and S3.
[0091] The fourth Serdes port G4, the fifth Serdes port G5, and the sixth Serdes port G6 of the OAM5 are respectively connected to the same second port: PCIe port C2 of the interface switching chips S4, S5, and S6.
[0092] Taking OAM6 as an example, the connection between the multiple first ports and the second ports of each interface switching chip is as follows:
[0093] The zeroth Serdes port G0, the first Serdes port G1, the second Serdes port G2, and the third Serdes port G3 of the OAM6 are respectively connected to the same second port: PCIe port C7 of the interface switching chips S0, S1, S2, and S3.
[0094] The fourth Serdes port G4, the fifth Serdes port G5, and the sixth Serdes port G6 of the OAM6 are respectively connected to the same second port: PCIe port C3 of the interface switching chips S4, S5, and S6.
[0095] Taking OAM7 as an example, the connection between the multiple first ports and the second ports of each interface switching chip is as follows:
[0096] The zeroth Serdes port G0, the first Serdes port G1, the second Serdes port G2, and the third Serdes port G3 of the OAM7 are respectively connected to the same second port: PCIe port C3 of the interface switching chips S0, S1, S2, and S3.
[0097] The fourth Serdes port G4, the fifth Serdes port G5, and the sixth Serdes port G6 of the OAM7 are respectively connected to the same second port: PCIe port C7 of the interface switching chips S4, S5, and S6.
[0098] In other words, a first port of a computing acceleration entity is connected to a second port of an interface switching chip, so that a computing acceleration entity can be connected one-to-one with multiple interface switching chips through multiple first ports, and thus a computing acceleration entity can be connected to multiple interface switching chips respectively; furthermore, when multiple computing acceleration entities are connected to multiple interface switching chips, the multiple computing acceleration entities can be interconnected through multiple interface switching chips.
[0099] Furthermore, in the embodiments of this application, reference is made to Figure 3 and Figure 4 The plurality of computation acceleration entities can be arranged in one or more rows, specifically, referring to Figure 3 The four computation acceleration entities can be arranged in a row; refer to Figure 4The eight computing acceleration entities can be arranged in two rows, with four computing acceleration entities in each row; in other embodiments, the plurality of computing acceleration entities can be arranged according to the specific number of computing acceleration entities to simplify the connection structure layout.
[0100] Furthermore, continue to refer to Figure 3 and Figure 4 The computing unit further includes a third port P0 and a fourth port P1; the third port P0 supports the PCIe bus and the memory interconnect bus between the computing unit; the fourth port P1 supports the PCIe bus, and the PCIe bus supported by the third port P0 and the fourth port P1 has different bit widths; for example, P0[15:0] indicates that the P0 port supports a 16-bit wide PCIe bus, and P1[1:0] indicates that the P1 port supports a 2-bit wide PCIe bus.
[0101] The multiplexed interconnect system also includes multiple PCIe retimers, each PCIe retimer being connected to the fourth port P1 of a computing acceleration entity.
[0102] Continue to refer to Figure 3 The multi-way interconnect system further includes: multiple PCIe connectors (PCIe CONN), wherein one of the PCIe retimers is connected to one PCIe connector.
[0103] Furthermore, Figure 5 This is a schematic diagram of another optional structure of the multi-way interconnection system provided in the embodiments of this application, wherein, Figure 5 Based on Figure 4 Another structural diagram of the interconnection of 8 computing acceleration entities, combined with Figure 5 As shown, the multi-channel interconnect system also includes: an external connector, to which the plurality of PCIe retimers are connected; a computing unit management controller; and a field-programmable gate array (FPGA) chip.
[0104] The computing unit management controller is used to manage and control the computing units; FPGA is an integrated circuit that consists of a large number of logic units, memory units and programmable interconnect resources. These resources are connected into specific logic circuits through specific programming methods, allowing users to programmatically configure the hardware structure, providing flexibility and customizability. Users can implement specific logic functions through programming.
[0105] The computing unit management controller can be connected to the field-programmable gate array (FPGA) via a PCIe bus and / or an I2C bus to perform integrated control, management, and scheduling of the FPGA's internal computing resources to achieve specific computing tasks. In addition, both the computing unit management controller and the FPGA can be connected to the external connector via an I2C (Inter-Integrated Circuit) bus to communicate with external devices (e.g., external host) through the external connector.
[0106] As can be seen, the multi-way interconnection system provided in this application includes multiple computing acceleration entities with integrated computing units, and multiple interface switching chips for interconnecting multiple computing acceleration entities to achieve interconnection of multiple computing units. The computing units carried by the computing acceleration entities include multiple first ports supporting memory interconnect buses, and the interface switching chips include multiple second ports, with the second ports matching the first ports. Furthermore, this application embodiment can achieve separate connections between any computing acceleration entity and each interface switching chip through connection channels connecting the first ports of the computing acceleration entities and the second ports of the interface switching chips. Thus, multiple computing acceleration entities can communicate through multiple interface switching chips to achieve interconnection between multiple computing acceleration entities, thereby achieving interconnection between multiple computing units carried by multiple computing acceleration entities, meeting the interconnection requirements between multiple computing units, and enabling data transmission and communication.
[0107] This application provides a computer device, such as a terminal device or a server device, which includes the multi-way interconnection system described in the foregoing embodiments.
[0108] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.
[0109] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A multi-channel interconnection system, characterized in that, include: Multiple computing acceleration entities, wherein the computing acceleration entity is a standardized entity unit for integrating computing units, the computing acceleration entity includes computing units, and the computing units include multiple first ports supporting a memory interconnect bus; Multiple interface switching chips, each interface switching chip including multiple second ports, the second ports being matched with the first ports; The connection channel connects the first port of the computing acceleration entity and the second port of the interface switching chip. Each computing acceleration entity has multiple connection channels that are respectively connected to the multiple interface switching chips.
2. The multi-channel interconnection system according to claim 1, characterized in that, The number of multiple first ports of a computing acceleration entity is greater than the number of multiple interface switching chips; wherein the multiple first ports include: at least one independent first port and at least one group of first ports, wherein one group of first ports includes at least two first ports; A computation acceleration entity may have multiple connectivity channels, including: Each group of first ports corresponds to a connection channel, wherein each group of first ports is connected to an interface switching chip; Each independent first port corresponds to a connection channel, and one independent first port connects to one interface switching chip.
3. The multi-channel interconnection system according to claim 2, characterized in that, The first port is a Serdes port, and the plurality of first ports include: the zeroth Serdes port, the first Serdes port, the second Serdes port, the third Serdes port, the fourth Serdes port, the fifth Serdes port, and the sixth Serdes port; Wherein, the at least one independent first port is the sixth Serdes port, and the at least one group of first ports includes the first group of first ports corresponding to the zeroth Serdes port and the first Serdes port, the second group of first ports corresponding to the second Serdes port and the third Serdes port, and the third group of first ports corresponding to the fourth Serdes port and the fifth Serdes port.
4. The multi-channel interconnection system according to claim 1, characterized in that, The number of multiple first ports of a computing acceleration entity is equal to the number of multiple interface switching chips, wherein the multiple connection channels of a computing acceleration entity include: A one-to-one connection channel corresponding to each of the plurality of interface switching chips, wherein a first port of a computing acceleration entity is connected to a second port of an interface switching chip.
5. The multi-channel interconnection system according to claim 4, characterized in that, The first port is a Serdes port, and the plurality of first ports include: a zeroth Serdes port, a first Serdes port, a second Serdes port, a third Serdes port, a fourth Serdes port, a fifth Serdes port, and a sixth Serdes port; one first port corresponds to a one-to-one connection channel of one interface switching chip.
6. The multiplexing system according to any one of claims 2-5, characterized in that, The multiple computing acceleration entities are arranged in one or more rows.
7. The multi-channel interconnection system according to claim 1, characterized in that, The computing unit further includes a third port and a fourth port; the third port supports the PCIe bus and the memory interconnect bus between the computing unit. The fourth port supports the PCIe bus, and the PCIe bus widths supported by the third port and the fourth port are different. The multiplexed system also includes: multiple PCIe retimers, one of which is connected to the fourth port of a compute acceleration entity.
8. The multi-channel interconnection system according to claim 7, characterized in that, The multiplexed interconnect system also includes: multiple PCIe connectors, with one PCIe retimer connected to one PCIe connector.
9. The multi-channel interconnection system according to claim 7, characterized in that, The multi-way interconnection system also includes: External connector, the plurality of PCIe retimers are connected to the external connector; Computing unit management controller and field-programmable gate array (FPGA) chip; The computing unit management controller is connected to the field-programmable gate array (FPGA) chip via a PCIe bus and / or an I2C bus; both the computing unit management controller and the FPGA chip are connected to the external connector via an I2C bus.
10. A computer device, characterized in that, The computer device includes a multiplexing system as described in any one of claims 1 to 9.