Hybrid channel analog-to-digital converter

Abstract

The utility model relates to the field of analog-to-digital converters, in particular to a mixed channel analog-to-digital converter, which comprises an anti-aliasing filter bank, a digital calibration engine, a signal processing module, a self-adaptive clock distribution network and a data integration module, according to the mixed channel analog-to-digital converter provided by the utility model, the SAR ADC and the Pipeline ADC architecture ADC are integrated, and two paths of signals work cooperatively through the adaptive clock distribution network, so that full-band signal acquisition is realized; an error suppression double-closed-loop architecture design is adopted, the random offset error standard deviation is reduced, and random noise interference generated by a front-end analog circuit is effectively suppressed.

Description

Technical Field

[0001] This utility model relates to the field of analog-to-digital converters, and more specifically to a mixed-channel analog-to-digital converter. Background Technology

[0002] An analog-to-digital converter (ADC) is a device or circuit that converts a continuous analog signal into a discrete digital signal. Common ADC architectures include successive approximation (SAR) architecture, pipeline architecture, flash memory architecture, and Sigma-Delta architecture. After the ADC converts the continuous analog signal into a digital signal, a comparator compares the digital signal with a reference voltage and outputs the comparison result. Since the number of comparators increases exponentially with resolution, comparator performance is crucial. However, in actual circuits, non-ideal factors such as component parameter mismatch, process deviations, and temperature drift cause the comparator to require a certain difference in input voltage to trigger a switching, directly affecting the accuracy of the ADC.

[0003] Existing analog-to-digital converters have the following problems: 1. It is difficult to simultaneously acquire signals from multiple frequency bands; 2. Comparator misalignment leads to DNL deterioration and clock jitter causes sampling time uncertainty, which further causes systematic deviations in the target detection accuracy of the equipment. Utility Model Content

[0004] In view of this, the present invention discloses a hybrid channel analog-to-digital converter to solve the above problems; comprising: an anti-aliasing filter bank, a digital calibration engine, a signal processing module, an adaptive clock distribution network, and a data integration module;

[0005] Furthermore, an anti-aliasing filter bank is used to acquire the radio frequency input signal;

[0006] A digital calibration engine is used to distribute RF input signals to the signal processing module;

[0007] The signal processing module is used to process the radio frequency input signal into an equivalent sampled digital stream, including a low-frequency channel and a high-frequency channel. The low-frequency channel adopts a pipeline ADC architecture, and the high-frequency channel adopts a SAR ADC architecture.

[0008] An adaptive clock distribution network is used to distribute error vectors to the digital calibration engine and phase identification codes to the data integration module based on the relative time difference of the sampling edges of the signal processing module; the digital calibration engine generates a correction coefficient matrix based on the error vectors.

[0009] The data integration module aligns the equivalent sampled digital stream based on the phase identification code and performs post-processing compensation and correction based on the correction coefficient matrix to output a full-band digital signal.

[0010] The beneficial effects of this utility model include:

[0011] By adopting a heterogeneous parallel architecture design, the low-frequency channel and the high-frequency channel perform analog-to-digital conversion independently. A parallel 4-channel SAR ADC is used to process the high-frequency signal, and an improved 4-channel Pipeline ADC is used to process the low-frequency signal. The two signals work together through an adaptive clock distribution network to achieve full-band signal acquisition.

[0012] By adopting a background calibration loop design, based on the cooperative statistical characteristics of the comparator array, the standard deviation of random offset error is reduced by 11.3 times, effectively suppressing random noise interference from the front-end analog circuit.

[0013] By employing a least mean square algorithm accelerator, joint compensation is implemented for system-level nonlinear distortion. By using the error vector as a priori constraint of the least mean square algorithm, a closed-loop feedback is established in the digital domain to form an iterative elimination mechanism for nonlinear error, thereby improving the integral nonlinear error from ±2.1 LSB to ±0.8 LSB.

[0014] By employing a distributed delay-locked loop to suppress clock jitter from 300fs to 80fs at a clock frequency of 1.5GHz, the timing stability of the analog-to-digital conversion process is ensured. Furthermore, an on-chip LC filter is used to perform secondary shaping of the clock signal to suppress high-frequency jitter components (>100MHz). This achieves embedded coupling of time-domain phase locking and frequency-domain noise filtering, thereby improving the clock stability across the entire frequency band and ultimately enhancing the detection accuracy of the device. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the system architecture of the hybrid channel analog-to-digital converter in this utility model. Detailed Implementation

[0016] To make the objectives, technical solutions, features and advantages of this utility model clearer, the following description, in conjunction with the accompanying drawings and embodiments, will further illustrate this utility model.

[0017] This embodiment includes a mixed-channel analog-to-digital converter, such as... Figure 1 As shown, it includes: an anti-aliasing filter bank, a digital calibration engine, a signal processing module, an adaptive clock distribution network, and a data integration module.

[0018] Among them, the anti-aliasing filter bank is used to acquire the radio frequency input signal.

[0019] The digital calibration engine is used to distribute the RF input signal to the signal processing module and correct the signal processing module.

[0020] The signal processing module is used to process the radio frequency input signal into an equivalent sampled digital stream, including a low-frequency channel and a high-frequency channel. The low-frequency channel adopts a pipeline ADC (analog-to-digital converter) architecture, and the high-frequency channel adopts a SAR ADC (successive approximation analog-to-digital converter) architecture.

[0021] An adaptive clock distribution network is used to distribute error vectors to the digital calibration engine and phase identification codes to the data integration module based on the relative time difference of the sampling edges of the signal processing module; the digital calibration engine generates a correction coefficient matrix based on the error vectors.

[0022] The data integration module aligns the equivalent sampled digital stream based on the phase identification code and performs post-processing compensation and correction based on the correction coefficient matrix to output a full-band digital signal.

[0023] Specifically, the anti-aliasing filter bank acquires the radio frequency input signal and performs frequency division and routing on the radio frequency input signal, dividing the signal into a high-frequency band signal above -40dBm and a low-frequency band signal below -40dBm to avoid frequency band overlap interference.

[0024] The digital calibration engine includes a Least Mean Square (LMS) algorithm accelerator. The LMS accelerator processes the error vector output by the adaptive clock distribution network. Through a parallel multiply-accumulate unit array, it rapidly iterates the statistical properties of the error vector to generate a 32-bit floating-point correction coefficient matrix. This matrix dynamically corrects inter-stage gain errors and code-domain nonlinear distortion in the Pipeline ADC. By jointly estimating the inter-stage gain error of the Pipeline ADC and the residual phase noise of the adaptive clock distribution network, the LMS accelerator can optimize the integral nonlinearity deviation from ±2.1 LSB to ±0.8 LSB, increase the system effective number of bits (ENOB) from 6.2 bits to 8.9 bits, and suppress the integral nonlinearity error at frequency band boundaries to below ±0.5 LSB.

[0025] Furthermore, the digital calibration engine also monitors the signal's spectral distribution in real time. When the high-frequency signal energy is detected to be below -40dBm, it shuts down two SAR channels and switches the sampling rate to 2.5GS / s, while simultaneously increasing the low-frequency Pipeline ADC resolution to 16 bits to achieve energy efficiency optimization.

[0026] The signal processing module adopts a heterogeneous parallel architecture, in which the low-frequency and high-frequency channels perform analog-to-digital conversion independently, while sharing the same reference voltage source (1.2V±0.1%). A cross-channel reference voltage buffer is used to achieve level matching in order to eliminate DC offset between channels.

[0027] The low-frequency channel employs an improved 4-channel pipeline ADC architecture. The pipeline ADC consists of multiple cascaded sub-ADCs. Each sub-ADC performs preliminary quantization of the input analog signal, and the resulting margin voltage is amplified by a margin amplifier before being used as the input to the next sub-ADC. This invention inserts redundant bit comparators between each pipeline stage and a calibration threshold at the 2.5th bit within each pipeline stage, extending the ADC's error coverage to ±1.5 LSB. The low-frequency channel also utilizes a shared operational amplifier architecture, with all four channels sharing a single calibration operational amplifier to reduce component count and ADC power consumption. The final output is a low-frequency equivalent sampled digital stream.

[0028] The high-frequency channel adopts a parallel 4-channel independent SAR ADC architecture. The SAR ADC, controlled by a clock signal, generates comparison signals sequentially from the most significant bit to the least significant bit. It compares the input analog signal with a reference voltage generated by the DAC capacitor network within the SAR ADC architecture, then latches the comparison result to form the final digital output code. This invention integrates a 128-bit asynchronous comparator array and a charge recovery switch array within each channel. When the comparator array enters the latching phase, the charge recovery switch array recovers residual charge from the DAC capacitor network in the SAR ADC. By recovering the residual charge to the energy storage node, the periodic synchronization of comparator reset and charge reuse is achieved.

[0029] Furthermore, the high-frequency channel achieves a 125ps sampling interval control between channels through a four-phase non-overlapping clock signal, outputs a high-frequency equivalent sampled digital stream synthesized by four-phase time interleaving, and synchronously embeds a phase identification code generated by an adaptive clock distribution network. The phase identification code is a 3-bit phase ID; the four-phase non-overlapping clock signal is implemented by the adaptive clock distribution network.

[0030] The adaptive clock distribution network includes a clock jitter suppression circuit and a distributed delay-locked loop.

[0031] The clock jitter suppression circuit is used to monitor and quantify the relative time difference of the sampling edges of the signal processing module in real time, obtain the error vector, and feed the error vector back to the distributed delay-locked loop and digital calibration engine.

[0032] Distributed Delay-Locked Ring (DLL) is used to generate phase identification codes based on the error vector.

[0033] Specifically, the distributed delay-locked loop uses an on-chip LC filter to perform secondary shaping of the clock signal; the LC filter can suppress high-frequency clock jitter to below 80fs, ensure strict timing alignment of multi-channel sampling clocks, control the timestamp error within 1ps, and thus ensure timing consistency during data transmission.

[0034] In this embodiment, the distributed delay-locked loop adopts a progressively adjustable delay chain with a step accuracy of 5ps to perform 1 / 4-cycle phase cutting on the 1.25GHz master clock signal, cutting the 800ps master clock cycle into a 200ps four-phase effective sampling interval, and then compressing it to a 125ps effective sampling interval through a duty cycle shaping circuit, so as to achieve strict timing interleaving of sampling points between channels, and finally generate a four-phase non-overlapping clock signal.

[0035] The adaptive clock distribution network adopts a tree-like H-shaped wiring structure. Through the tree-like H-shaped wiring structure, the adaptive clock distribution network distributes phase-synchronized four-phase non-overlapping clock signals to the high-frequency SAR ADC channel, the low-frequency Pipeline ADC channel and the digital calibration engine, dynamically compensating for the transmission delay differences between channels.

[0036] Furthermore, the adaptive clock distribution network is implemented based on a multi-channel synchronous detection circuit. The multi-channel synchronous detection circuit captures the relative time difference of the sampling edges of each channel at a resolution of 1ps through a differential time-to-digital converter (TDC), feeds the error vector back to the delay-locked loop and digital calibration engine, forming a closed-loop feedback adjustment mechanism, and ensures strict timing alignment of the cross-band sampling windows (deviation ≤ ±15ps), eliminating inter-channel aliasing interference and spectrum leakage caused by transmission path differences.

[0037] Furthermore, in this invention, during the operation of the hybrid channel analog-to-digital converter, the digital calibration engine, signal processing module, data integration module, and adaptive clock distribution network form a background calibration loop. This background calibration loop dynamically eliminates system-level nonlinear errors and gain drift during the analog-to-digital conversion process. Specifically, by injecting an amplitude-adjustable pseudo-random perturbation signal (PRBS31 sequence, 0.1-1.0 LSB) into the distributed capacitor DAC array of the high-frequency SAR ADC and the margin amplifier of the low-frequency Pipeline ADC, the perturbation response is extracted in real time, and an error statistical feature vector, i.e., the error vector, is generated. This error vector is then input to the least mean square algorithm accelerator of the digital calibration engine to update the correction coefficient matrix, thereby achieving dynamic offset compensation and gain error suppression. Through the background calibration loop, the total harmonic distortion (THD) can be reduced by 12 dB.

[0038] The data integration module, based on a global timestamp (1ps resolution), performs cross-band sampling point interpolation and alignment between the high-frequency equivalent sampled digital stream and the low-frequency equivalent sampled digital stream to form a seamless spectrum sampling matrix across the 0.5-6GHz full-band frequency range. The global timestamp is implemented by an adaptive clock allocation network to ensure that events across nodes and devices have a unified time reference.

[0039] Specifically, a noise shaping filter is used to achieve cross-band sampling point interpolation alignment, and high-frequency data (5GS / s) and low-frequency data (1.25GS / s) are upsampled / downsampled to a 20GS / s time base, and then further synthesized into a 20-bit wide dynamic range signal.

[0040] The wide dynamic range signal is post-processed using a correction coefficient matrix to compensate for aliasing distortion at the frequency band junction (2-2.5GHz) between high-frequency and low-frequency data, and output a full-band digital signal.

[0041] Finally, it should be noted that the above description only depicts some embodiments of the present utility model. For those skilled in the art, it is conceivable that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present utility model. The protection scope of the present utility model is defined by the appended claims and their equivalents, and all the above-mentioned behaviors should be covered within the protection scope of the present utility model.

Claims

1. A mixed-channel analog-to-digital converter, characterized in that, include: Anti-aliasing filter bank, digital calibration engine, signal processing module, adaptive clock distribution network, and data integration module; Among them, the anti-aliasing filter bank is used to acquire the radio frequency input signal; A digital calibration engine is used to distribute RF input signals to the signal processing module; The signal processing module is used to process the radio frequency input signal into an equivalent sampled digital stream, including a low-frequency channel and a high-frequency channel. The low-frequency channel adopts a pipeline ADC architecture, and the high-frequency channel adopts a SAR ADC architecture. An adaptive clock distribution network is used to distribute error vectors to the digital calibration engine and phase identification codes to the data integration module based on the relative time difference of the sampling edges of the signal processing module; the digital calibration engine generates a correction coefficient matrix based on the error vectors. The data integration module aligns the equivalent sampled digital stream based on the phase identification code and performs post-processing compensation and correction based on the correction coefficient matrix to output a full-band digital signal.

2. The hybrid channel analog-to-digital converter according to claim 1, characterized in that, The anti-aliasing filter bank acquires the RF input signal and performs frequency division and routing on the RF input signal, dividing the signal into a high-frequency band signal and a low-frequency band signal. The high-frequency band signal and the low-frequency band signal are used as input to the high-frequency band channel and the low-frequency band channel, respectively.

3. The hybrid channel analog-to-digital converter according to claim 1, characterized in that, The digital calibration engine includes a least mean square algorithm accelerator, which uses a parallel multiply-accumulate unit array to iteratively calculate the statistical properties of the error vector and generate a correction coefficient matrix.

4. The mixed-channel analog-to-digital converter according to claim 1, characterized in that, The signal processing module adopts a heterogeneous parallel architecture, with low-frequency and high-frequency channels performing analog-to-digital conversion independently, sharing the same reference voltage source, and using a cross-channel reference voltage buffer to achieve level matching.

5. The mixed-channel analog-to-digital converter according to claim 1, characterized in that, The adaptive clock distribution network includes a clock jitter suppression circuit and a distributed delay-locked loop.

6. The mixed-channel analog-to-digital converter according to claim 5, characterized in that, The clock jitter suppression circuit is used to monitor and quantify the relative time difference of the sampling edges of the signal processing module in real time, obtain the error vector, and feed the error vector back to the distributed delay-locked loop and digital calibration engine.

7. The mixed-channel analog-to-digital converter according to claim 6, characterized in that, Distributed delay-locked loops are used to generate phase identification codes based on error vectors.

8. The mixed-channel analog-to-digital converter according to claim 7, characterized in that, The distributed delay-locked loop performs a 1 / 4-cycle phase cut on the master clock signal, dividing the master clock cycle into four effective sampling intervals. A duty cycle shaping circuit is used to compress the four effective sampling intervals to generate a four-phase non-overlapping clock signal, which is used to drive the hybrid channel analog-to-digital converter.

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