Semiconductor device

Abstract

A semiconductor device includes a first transistor over a substrate including a first semiconductor channel layer, a first gate structure including a first ferroelectric layer, and a first source region and a first drain region on opposite sides of the first semiconductor channel layer. A second transistor is over the substrate and includes a second semiconductor channel layer, a second gate structure including a second ferroelectric layer, and a second source region and a second drain region on opposite sides of the second semiconductor channel layer. In a profile, the second semiconductor channel layer is shorter than the first semiconductor channel layer. An output terminal is electrically connected with the first drain region of the first transistor and the second drain region of the second transistor. A material of the first ferroelectric layer is in contact with a top surface of the substrate.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in several generations of ICs. Each generation features smaller and more complex circuits compared to the previous one. However, these advancements have increased the complexity of handling and manufacturing ICs. In the evolution of ICs, functional density (i.e., the number of interconnects per die area) has generally increased, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. However, as feature sizes continue to decrease, manufacturing processes continue to become more difficult to execute. Therefore, forming reliable semiconductor devices in increasingly smaller sizes remains a challenge. Utility Model Content

[0003] In some embodiments disclosed herein, a semiconductor device is characterized by comprising: a first transistor above a substrate, including a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer and including a first ferroelectric layer, and a first source region and a first drain region on a plurality of opposite sides of the first semiconductor channel layer. A second transistor is above the substrate and including a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer and including a second ferroelectric layer, and a second source region and a second drain region on a plurality of opposite sides of the second semiconductor channel layer. In a cross-sectional view, the second semiconductor channel layer is shorter than the first semiconductor channel layer. An output terminal is electrically connected to the first drain region of the first transistor and the second drain region of the second transistor. A material of the first ferroelectric layer is in contact with a top surface of the substrate.

[0004] In some embodiments disclosed herein, a semiconductor device is characterized by comprising: a first transistor above a substrate, including a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer and including a first ferroelectric layer, and a first source region and a first drain region on a plurality of opposite sides of the first semiconductor channel layer. A second transistor is above the substrate and including a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer and including a second ferroelectric layer, and a second source region and a second drain region on a plurality of opposite sides of the second semiconductor channel layer. In a cross-sectional view, the second semiconductor channel layer is shorter than the first semiconductor channel layer. An output terminal is electrically connected to the first drain region of the first transistor and the second drain region of the second transistor. A material of the first ferroelectric layer is in contact with a top surface of the substrate. The substrate includes a semiconductor layer and an insulating layer, wherein the material of the first ferroelectric layer is in contact with the insulating layer of the substrate.

[0005] In some embodiments disclosed herein, a semiconductor device is characterized by comprising: a first transistor above a substrate, including a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer and including a first ferroelectric layer, and a first source region and a first drain region on a plurality of opposite sides of the first semiconductor channel layer. A second transistor above the substrate includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer and including a second ferroelectric layer, and a second source region and a second drain region on a plurality of opposite sides of the second semiconductor channel layer. In a cross-sectional view, the second semiconductor channel layer is shorter than the first semiconductor channel layer. An output terminal is electrically connected to the first drain region of the first transistor and the second drain region of the second transistor. A first input terminal is electrically connected to the first source region of the first transistor. A second input terminal is electrically connected to the second source region of the second transistor, wherein the first input terminal and the second input terminal are spaced apart from each other. A polarization state terminal is electrically connected to the first gate structure of the first transistor and the second gate structure of the second transistor. A material of the first ferroelectric layer is in contact with a top surface of the substrate. Attached Figure Description

[0006] The features disclosed herein are best understood when read in conjunction with the accompanying drawings from the following detailed description. Please note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of explanation.

[0007] Figure 1A A perspective view of a semiconductor device according to some embodiments of the present disclosure;

[0008] Figure 1B A cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0009] Figure 1C This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure;

[0010] Figure 1D Simulation results for semiconductor devices in different polarization states according to some embodiments of this disclosure;

[0011] Figures 2A to 13 The illustrations depict methods for forming a semiconductor device at various stages according to some embodiments of the present disclosure;

[0012] Figure 14 This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure;

[0013] Figure 15A This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 15B and Figure 15C Simulation results of a semiconductor device according to some embodiments of this disclosure;

[0015] Figure 16A This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 16B and Figure 16C Simulation results of a semiconductor device according to some embodiments of this disclosure;

[0017] Figure 17 This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure;

[0018] Figure 18A and Figure 18B Circuit diagrams and simulation results of semiconductor devices in different polarization states according to some embodiments of this disclosure;

[0019] Figure 19A and Figure 19B Circuit diagrams and simulation results of semiconductor devices in different polarization states according to some embodiments of this disclosure;

[0020] Figure 20A and Figure 20B Circuit diagrams and simulation results of semiconductor devices in different polarization states according to some embodiments of this disclosure;

[0021] Figure 21A and Figure 21B Circuit diagrams and simulation results of semiconductor devices in different polarization states according to some embodiments of this disclosure;

[0022] Figure 22A , Figure 22B , Figure 22C and Figure 22D The following are circuit diagrams, equivalent circuits, truth tables, and simulation results of semiconductor devices according to some embodiments of the present disclosure;

[0023] Figure 23A , Figure 23B , Figure 23C and Figure 23D The following are circuit diagrams, equivalent circuits, truth tables, and simulation results of semiconductor devices according to some embodiments of the present disclosure;

[0024] Figure 24A , Figure 24B , Figure 24C and Figure 24D The following are circuit diagrams, equivalent circuits, truth tables, and simulation results of semiconductor devices according to some embodiments of the present disclosure;

[0025] Figure 25 A perspective view of a semiconductor device according to some embodiments of the present disclosure;

[0026] Figures 26 to 31 The illustrations depict methods for forming a semiconductor device at various stages according to some embodiments of this disclosure.

[0027] [Symbol Explanation]

[0028] 10: Semiconductor Devices / Complementary Field-Effect Transistors (CFETs) / 2-to-1 Multiplexers / AND Gates / OR Gates / XOR Gates

[0029] 20: Complementary Field-Effect Transistor (CFET)

[0030] 10A, 10B, 10C: CFET

[0031] 50:Substrate

[0032] 50A: Semiconductor layer

[0033] 50B: Insulation layer

[0034] 55: Sacrifice Layer

[0035] 60: Dielectric layer

[0036] 71, 72, 73, 74, 75: Conductive vias

[0037] 81, 82, 83, 84: Conductive pads

[0038] 100:Substrate

[0039] 102: Semiconductor layer

[0040] 102CH: Passage Area

[0041] 102SD1: Source / Drain Region

[0042] 102SD2: Source / Drain Region

[0043] 104: Semiconductor layer

[0044] 105: Semiconductor layer

[0045] 115: Gate spacer

[0046] 116: Internal spacers

[0047] 117: Isolation layer

[0048] 130: Dummy gate structure

[0049] 132: Dummy gate dielectric

[0050] 134: Dummy Gate Electrode

[0051] 140A: Source / Drain epitaxial structure

[0052] 140B: Source / Drain epitaxial structure

[0053] 150: Isolation Structure

[0054] 152: Interlayer Dielectric (ILD) Layer

[0055] 155: Contact Etching Stop Layer (CESL)

[0056] 170: Metal gate structure

[0057] 172: Interface Layer

[0058] 174: Ferroelectric layer

[0059] 176: Gate electrode

[0060] 180: Etching Stop Layer (ESL)

[0061] 185: Interlayer Dielectric (ILD) Layer

[0062] 191: Source / Drain Contact

[0063] 191: Source / Drain Contact

[0064] 192: Source / Drain Contact

[0065] 193: Gate via

[0066] 194: Source / Drain Contact

[0067] 202: Semiconductor layer

[0068] 202CH: Passage Area

[0069] 202SD1: Source / Drain Region

[0070] 202SD2: Source / Drain Region

[0071] 204: Semiconductor layer

[0072] 240A: Source / Drain epitaxial structure

[0073] 240B: Source / Drain epitaxial structure

[0074] 250: Isolation Structure

[0075] 252: Interlayer Dielectric (ILD) Layer

[0076] 255: Contact Etching Termination Layer (CESL)

[0077] 270: Metal gate structure

[0078] 272: Interface Layer

[0079] 274: Ferroelectric layer

[0080] 276: Gate electrode

[0081] 330: First hard mask

[0082] 332: Second hard mask

[0083] C1: Curve

[0084] C2: Curve

[0085] D1: Drain electrode

[0086] D1: Curve

[0087] D2: Drain electrode

[0088] D2: Curve

[0089] G1: Gate

[0090] G2: Gate

[0091] GND: Grounding

[0092] I D Drain current

[0093] IMP1: Fabric implantation technology

[0094] IMP2: Fabric implantation technology

[0095] IN0, IN1, IN2, IN3: Input terminals

[0096] LA: Latch element

[0097] MA: Patterned Mask

[0098] MA1: Patterned Mask

[0099] O1: Source / Drain opening

[0100] OUT: Input terminal

[0101] PS: Polarization state terminal

[0102] PS1: Polarization state terminal

[0103] PS2: Polarization State Terminal

[0104] S1: Source

[0105] S2: Source

[0106] ST: Semiconductor Stacking

[0107] TR1: First transistor

[0108] TR2: Second transistor

[0109] V G Gate voltage Detailed Implementation

[0110] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0111] Additionally, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” and similar terms, are used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein are interpreted accordingly. As used herein, “approximately,” “about,” “around,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The quantities given herein are approximate values, thus meaning that the terms “approximately,” “about,” “around,” or “substantially” may be interpreted without explicit statement. However, those skilled in the art will recognize that the values ​​or ranges described throughout the description are merely examples and may decrease or change as integrated circuits are scaled down.

[0112] Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine optical lithography and self-alignment processes to allow patterns to be generated with a pitch, for example, smaller than that obtained using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0113] As the semiconductor industry continues to advance to technology nodes in pursuit of higher device density, higher efficiency, and lower costs, challenges from both manufacturing and design issues have led to stacked device structure configurations, such as complementary field effect transistors (C-FETs), in which n-type multi-gate transistors and p-type multi-gate transistors are stacked vertically on top of each other.

[0114] Figure 1A This is a perspective view of a semiconductor device according to some embodiments of the present disclosure. Figure 1B This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figure 1C This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure. More specifically, Figure 1A The figure shows a perspective view of the semiconductor device 10. Figure 1B For along Figure 1AThe cross-sectional view of line BB, and Figure 1C This is a circuit diagram of semiconductor device 10. Please note that... Figure 1B For the sake of simplicity, some components described herein are not illustrated. Figure 1A middle.

[0115] A complementary field-effect transistor (CFET) 10 is provided, and a method for manufacturing the same is disclosed in the following disclosure. More specifically, the CFET 10 is a complementary ferroelectric field-effect transistor (CFeFET), which will be discussed below, comprising ferroelectric transistors stacked on top of each other.

[0116] See Figure 1A and Figure 1B In CFET 10, a first transistor TR1 is disposed above the substrate 50, and a second transistor TR2 is disposed vertically above the first transistor TR1. In some embodiments, the first transistor TR1 and the second transistor TR2 may each be a field-effect transistor (FET) and may include a gate-all-around (GAA) structure, and therefore the first transistor TR1 and the second transistor TR2 may also be referred to as GAA FETs.

[0117] Regarding the first transistor TR1, the first transistor TR1 includes a first semiconductor layer 102 and a first metal gate structure 170 surrounding a channel region 102CH of the first semiconductor layer 102, wherein the first semiconductor layer 102 also includes source / drain regions 102SD1 and 102SD2 on opposite sides of the channel region 102CH. Similarly, the second transistor TR2 includes a second semiconductor layer 202 and a second metal gate structure 270 surrounding a channel region 202CH of the second semiconductor layer 202, wherein the second semiconductor layer 202 also includes source / drain regions 202SD1 and 202SD2 on opposite sides of the channel region 202CH. The first metal gate structure 170 may include an interface layer 172, a ferroelectric layer 174, and a gate electrode 176. Similarly, the second metal gate structure 270 may include an interface layer 272, a ferroelectric layer 274, and a gate electrode 276. In some embodiments, the first transistor TR1 has a first conductivity type (e.g., n-type), and the second transistor TR2 has a second conductivity type (e.g., p-type) different from the first conductivity type. In other embodiments, the first transistor TR1 has a second conductivity type (e.g., p-type), and the second transistor TR2 has a first conductivity type (e.g., n-type).

[0118] In some embodiments, substrate 50 may include a semiconductor layer 50A and an insulating layer 50B above the semiconductor layer 50A. In other embodiments, the insulating layer 50B may be omitted. In such embodiments, the first transistor TR1 may be directly disposed on the semiconductor layer 50A. Semiconductor layer 50A typically comprises a crystalline semiconductor material such as silicon, but may include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or alloys thereof (e.g., Ga...). x Al 1-x As, Ga x Al 1-x N、In x Ga 1-x As and similar materials, oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and similar materials), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates. The insulating layer 50B may include, and may be, a buried oxide (BOX) layer formed by processes such as separation by implanted oxygen (SIMOX) and / or other suitable processes. In some embodiments, the insulating layer 50B is a silicon oxide (SiO2) layer.

[0119] The first semiconductor layer 102 and the second semiconductor layer 202 may comprise silicon or other suitable semiconductor materials. In some embodiments, the source / drain regions 102SD1 and 102SD2 of the first semiconductor layer 102 and the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202 comprise different types of dopants and therefore comprise different conductivity types. For example, if the first transistor TR1 is an n-type device and the second transistor TR2 is a p-type device, then the source / drain regions 102SD1 and 102SD2 may comprise n-type dopants, while the source / drain regions 202SD1 and 202SD2 may comprise p-type dopants. On the other hand, if the first transistor TR1 is a p-type device and the second transistor TR2 is an n-type device, then the source / drain regions 102SD1 and 102SD2 may comprise p-type dopants, while the source / drain regions 202SD1 and 202SD2 may comprise n-type dopants. P-type dopants may include boron (B), gallium (Ga), indium (In), aluminum (Al), or the like. N-type dopants may include phosphorus (P), arsenic (As), or antimony (Sb), or the like. In some embodiments, the channel region 102CH of the first semiconductor layer 102 and the channel region 202CH of the second semiconductor layer 202 may be intrinsic (e.g., undoped or negligibly doped).

[0120] The interface layer 172 of the first metal gate structure 170 and the interface layer 272 of the second metal gate structure 270 may be made of oxides, such as aluminum oxide (Al2O3), silicon oxide (SiO2), or the like. In other embodiments, each of the interface layers 172 and 272 may include an oxide layer (e.g., silicon oxide) and a high-k dielectric layer above the oxide layer. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0121] The ferroelectric layer 174 of the first metal gate structure 170 and the ferroelectric layer 274 of the second metal gate structure 270 may include materials capable of switching between two different polarization directions by applying an appropriate voltage difference across each of the ferroelectric layers 174 and 274. For example, the ferroelectric layers 174 and 274 include high-k dielectric materials, such as hafnium (Hf)-based dielectric materials or the like. In some embodiments, the ferroelectric layers 174 and 274 include hafnium oxide (HfO2), hafnium zirconium oxide (HZO), silicon-doped hafnium oxide, or the like.

[0122] In some embodiments, ferroelectric layers 174 and 274 may include barium titanium oxide (BaTiO3), lead titanium oxide (PbTiO3), lead zirconium oxide (PbZrO3), lithium niobium oxide (LiNbO3), sodium niobium oxide (NaNbO3), potassium niobium oxide (KNbO3), potassium tantalum oxide (KTaO3), bismuth scandium oxide (BiScO3), bismuth iron oxide (BiFeO3), and hafnium erbium oxide (Hf). 1-x Er x O), hafnium oxide (Hf) 1- x La x O), hafnium oxide (Hf) 1-x Y x O), hafnium gadolinium oxide (Hf) 1-x Gd x O), hafnium oxide (Hf) 1-x Al x O), hafnium oxide (Hf) 1- x Zr x O, HZO), hafnium titanium oxide (Hf) 1-x Ti x O), hafnium tantalum oxide (Hf) 1-x Ta x O) or similar. In other embodiments, ferroelectric layers 174 and 274 include HfZrO, HfAlO, HfLaO, HfCeO, HfO, HfGdO, HfSiO, or combinations thereof.

[0123] In some embodiments, each of the ferroelectric layers 174 and 274 has a thickness of about 2 nm to about 10 nm, while other thickness ranges are also applicable. In some embodiments, each of the ferroelectric layers 174 and 274 is formed in a fully crystalline state. In alternative embodiments, each of the ferroelectric layers 174 and 274 may be in a partially crystalline state; that is, each of the ferroelectric layers 174 and 274 is formed in a mixed crystalline-amorphous state and has a certain degree of structural order. In some embodiments, each of the ferroelectric layers 174 and 274 is a single layer. In alternative embodiments, each of the ferroelectric layers 174 and 274 has a multilayer structure.

[0124] The gate electrode 176 of the first metal gate structure 170 and the gate electrode 276 of the second metal gate structure 270 may include a work function metal layer and a filler metal. The work function metal layer may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include multiple layers. The filler metal may include tungsten (W), aluminum (Al), copper (Cu), or another suitable conductive material.

[0125] Gate electrodes 176 and 276 are connected to each other. In some embodiments, gate electrodes 176 and 276 are made of the same material and can be formed via the same deposition process. That is, the first transistor TR1 and the second transistor TR2 can share a common gate electrode (e.g., a combination of gate electrodes 176 and 276). Therefore, the first metal gate structure 170 of the first transistor TR1 is electrically connected to the second metal gate structure 270 of the second transistor TR2.

[0126] CFET 10 further includes a dielectric layer 60 covering the first transistor TR1 and the second transistor TR2. In some embodiments, the dielectric layer 60 may include oxides, such as silicon oxide (SiO2) or aluminum oxide (Al2O3). In other embodiments, the dielectric layer 60 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material, and / or other suitable dielectric materials.

[0127] The CFET 10 further includes conductive vias 71, 72, 73, 74, and 75 in the dielectric layer 60. More specifically, conductive via 71 contacts the source / drain region 102SD1 of the first transistor TR1. Conductive via 72 contacts the source / drain region 202SD1 of the second transistor TR2. Conductive via 73 contacts the second metal gate structure 270 of the second transistor TR2. Conductive via 74 contacts the source / drain region 202SD2 of the second transistor TR2. Conductive via 75 contacts the source / drain region 102SD2 of the first transistor TR1. Conductive vias 71, 72, 73, 74, and 75 may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive materials.

[0128] The CFET 10 includes conductive pads 81, 82, 83, and 84 above the dielectric layer 60. More specifically, conductive pad 81 contacts a conductive via 71 and is electrically connected to the source / drain region 102SD1 of the first transistor TR1. Conductive pad 82 contacts a conductive via 72 and is electrically connected to the source / drain region 202SD1 of the second transistor TR2. Conductive pad 83 contacts a conductive via 73 and is electrically connected to both the second metal gate structure 270 of the second transistor TR2 and the first metal gate structure 170 of the first transistor TR1. Conductive pad 84 contacts conductive vias 74 and 75 and is electrically connected to both the source / drain region 202SD2 of the second transistor TR2 and the source / drain region 102SD2 of the first transistor TR1. In some embodiments, conductive pads 81, 82, 83, and 84 are spaced apart from each other. The conductive pads 81, 82, 83 and 84 may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni) or other suitable conductive materials.

[0129] See Figure 1C ,in Figure 1C As mentioned above Figure 1A and Figure 1B The circuit diagram of the CFET 10 is described below. Specifically, the source S1 of the first transistor TR1 is electrically coupled to the input terminal IN1, and the source S2 of the second transistor TR2 is electrically connected to the input terminal IN0. The drains D1 of the first transistor TR1 and D2 of the second transistor TR2 are electrically coupled to each other and to the output terminal OUT. The gates G1 of the first transistor TR1 and G2 of the second transistor TR2 are electrically coupled to each other and to the polarization state terminal PS.

[0130] about Figures 1A to 1CThe gate G1, source S1, and drain D1 of the first transistor TR1 can be a first metal gate structure 170, a source / drain region 101SD1, and a source / drain region 101SD2, respectively. Similarly, the gate G2, source S2, and drain D2 of the second transistor TR2 can be a second metal gate structure 270, a source / drain region 201SD1, and a source / drain region 201SD2, respectively. Figure 1B The conductive pads 81, 82, 83 and 84 can respectively serve as Figure 1C The input terminals are IN1, IN0, PS (polarization status), and OUT (output).

[0131] Figure 1D These are simulation results of semiconductor devices in different polarization states according to some embodiments of this disclosure. More specifically, Figure 1D Illustration Figure 1C Different drain currents (Id) of the first transistor TR1 and the second transistor TR2 under different polarization states D ) for gate voltage (V G The curve of the first transistor TR1 and the second transistor TR2 is shown above. As mentioned above, both the first transistor TR1 and the second transistor TR2 are ferroelectric transistors, and therefore the first transistor TR1 and the second transistor TR2 can be polarized to have different resistivity states. More specifically, the ferroelectric layers 174 and 274 can be polarized to have different polarization states, and therefore have different resistivity states.

[0132] In the first polarization state (state 1), a positive write voltage can be applied to the polarization state terminal PS, and the first transistor TR1 and the second transistor TR2 are simultaneously forward polarized. After the first transistor TR1 and the second transistor TR2 are polarized, the first transistor TR1 (e.g., an n-type FeFET) can operate in depletion mode, as illustrated by curve C1. Conversely, the second transistor TR2 (e.g., a p-type FeFET) can operate in enhancement mode, as indicated by curve C2. In some embodiments, during the application of the write voltage, the input terminals IN1 and IN0 can be biased to ground (e.g., 0V).

[0133] On the other hand, in the second polarization state (state 0), when a negative write voltage is applied to the polarization state terminal PS, the first transistor TR1 and the second transistor TR2 are simultaneously negatively polarized. After the first transistor TR1 and the second transistor TR2 are polarized, the first transistor TR1 (e.g., an n-type FeFET) operates in enhancement mode, as illustrated by curve D1. Conversely, the second transistor TR2 (e.g., a p-type FeFET) can operate in depletion mode, as indicated by curve D2. In some embodiments, during the application of the write voltage, the input terminals IN1 and IN0 can be biased to ground (e.g., 0V).

[0134] Here, when the transistor operates in "depletion mode", the transistor is at a gate voltage V G zero (V) G When V = 0, it can include low resistance, as illustrated by curves C1 and D2. That is, when the gate voltage V G zero (V) G When the gate voltage V = 0, the transistor can be in the ON state. In contrast, when the transistor operates in "enhancement mode," the gate voltage V = 0. G zero (V) G When the gate voltage is zero (V = 0), it can include high resistance, as illustrated by curves C2 and D1. That is, when the gate voltage VG is zero (V = 0), it can include high resistance. G When the ratio is 0, the transistor can be in the off state (OFF). In some embodiments, the on / off ratio of the supplementary path is greater than 10. 6 It provides sufficient capabilities for a wide range of applications, which will be discussed in more detail later. Alternatively, the ratio of the drain current of the on-state transistor to the drain current of the off-state transistor is greater than 10. 6 .

[0135] With this configuration, the CFET 10, as described above, can be used in a variety of applications, which will be discussed in more detail later. In some embodiments, by properly adjusting the metal work functions of the n-type and p-type ferroelectric transistors, their high Vth and low Vth can be symmetrically aligned at VG = 0V.

[0136] Figures 2A to 13 The illustrations depict methods for forming a semiconductor device at various stages according to some embodiments of this disclosure. More specifically, Figures 2A to 13 The diagram is used to form Figure 1A and Figure 1B The CFET 10 method. Although Figures 2A to 13 The description is a series of actions, but it should be understood that these actions are not limited to a specific order that can be changed in other embodiments, and the disclosed method can also be applied to other structures. In other embodiments, some actions illustrated and / or described may be omitted in whole or in part. Please note that Figures 2A to 13 Some components mentioned above Figure 1A and Figure 2B As discussed, such components are marked the same, and related details will not be repeated for the sake of brevity.

[0137] See Figure 2A and Figure 2B ,in Figure 2A This is a perspective view of a semiconductor device. Figure 2B For along Figure 2AThe cross-sectional view of line BB is shown here. The initial structure is shown here. The sacrificial layer 55, the first semiconductor layer 102, the sacrificial layer 55 and the second semiconductor layer 202 are stacked on the substrate 50.

[0138] In some embodiments, semiconductor layers 102 and 202 may be made of germanium-free pure silicon layers. In some embodiments, semiconductor layers 102 and 202 may also be substantially pure silicon layers, such as layers having a germanium percentage of less than about 1%. The sacrificial layer 55 may be made of silicon-germanium. For example, the germanium percentage (atomic percentage) of the sacrificial layer 55 may be in the range of about 20% to about 60%. In some embodiments, semiconductor layers 102 and 202 and sacrificial layer 55 may be deposited using suitable deposition processes, such as selective epitaxial growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable processes. In some embodiments, sacrificial layer 55 may be removed during a replacement gate (RPG) process. Sacrificial layer 55 may also be referred to as a sacrificial semiconductor layer.

[0139] See Figure 3A and Figure 3B ,in Figure 3A This is a perspective view of a semiconductor device. Figure 3B For along Figure 3A A cross-sectional view of line BB. The stack of sacrificial layer 55, first semiconductor layer 102, sacrificial layer 55, and second semiconductor layer 202 is patterned to form a fin structure protruding from the top surface of substrate 50. In some embodiments, a patterned mask (not shown) may be formed over the stack, and an etching process may be performed using the patterned mask as an etching mask to remove unwanted portions of the stack, and the remaining portion of the stack is referred to as the fin structure. Once the fin structure is formed, the patterned mask is then removed.

[0140] See Figure 4A and Figure 4B ,in Figure 4A This is a perspective view of a semiconductor device. Figure 4B For along Figure 4A A cross-sectional view of line BB. A patterned mask MA is formed over the fin structure of sacrificial layer 55, first semiconductor layer 102, and second semiconductor layer 202. In some embodiments, the patterned mask MA is formed to cover the channel region 102CH of the first semiconductor layer 102 and the channel region 202CH of the second semiconductor layer 202. In some embodiments, the patterned mask MA may be a photoresist or a rigid mask.

[0141] See Figure 5A and Figure 5B ,in Figure 5A This is a perspective view of a semiconductor device. Figure 5B For along Figure 5A A cross-sectional view of line BB. The implantation process IMP1 is performed to dope the source / drain regions 102SD1 and 102SD2 of the first semiconductor layer 102. In some embodiments, the implants in implantation process IMP1 may be n-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb), or similar. That is, after the first implantation process IMP1 is completed, the source / drain regions 110SD of semiconductor layer 110 and 120SD of semiconductor layer 120 are both n-type doped regions. In some embodiments, the energy of the first implantation process IMP1 may be controlled such that the implants in implantation process IMP1 are driven down through the second semiconductor layer 202 to the first semiconductor layer 102. Therefore, the second semiconductor layer 202 may not be doped during implantation process IMP1. However, in other embodiments, the second semiconductor layer 202 may also be lightly doped, and thus n-type dopants can be detected in the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202.

[0142] See Figure 6A and Figure 6B ,in Figure 6A This is a perspective view of a semiconductor device. Figure 6B For along Figure 6A A cross-sectional view of line BB. The implantation process IMP2 is performed to dope the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202. In some embodiments, the implants in the second implantation process IMP2 may be p-type dopants, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or similar. That is, after the implantation process IMP2 is completed, both the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202 are p-type doped regions. In some embodiments, the energy of the implantation process IMP2 can be controlled such that the implantation of the implantation process IMP2 is driven into the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202. As mentioned above, the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202 are lightly doped during the implantation process IMP1. Therefore, both n-type and p-type dopants can be detected in the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202, with the p-type dopant concentration being higher than the n-type dopant concentration. Consequently, the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202 exhibit p-type conductivity.

[0143] See Figure 7A and Figure 7B ,in Figure 7A This is a perspective view of a semiconductor device. Figure 7B For along Figure 7A A cross-sectional view of line BB. The patterned mask is removed. Subsequently, the sacrificial layer 55 is removed, such that the first semiconductor layer 102 and the second semiconductor layer 202 are suspended above the substrate 50. In some embodiments, a patterned mask (not shown) may be formed above the substrate 50 and have openings to expose unwanted portions of the sacrificial layer 55, and an etching process is then performed to remove the sacrificial layer 55 through the openings in the patterned mask. The suspended portions of the first semiconductor layer 102 and the second semiconductor layer 202 may be supported by other portions of the structure covered by the patterned mask (e.g., other portions of the structure where the sacrificial layer 55 has not been removed).

[0144] See Figure 8A and Figure 8B ,in Figure 8A This is a perspective view of a semiconductor device. Figure 8B For along Figure 8A The cross-sectional view of line BB. A first metal gate structure 170 is formed above the substrate 50 and around the channel region 102CH of the first semiconductor layer 102, and a second metal gate structure 270 is formed above the first metal gate structure 170 and around the channel region 202CH of the second semiconductor layer 202.

[0145] The first metal gate structure 170 and the second metal gate structure 270 can be formed, for example, by selectively performing oxidation processes on the exposed surfaces of the first semiconductor layer 102 and the second semiconductor layer 202 to form interface layers 172 and 272, respectively. Subsequently, a deposition process is performed to form ferroelectric layers 174 and 274 over the interface layers 172 and 272, respectively. In some embodiments, the deposition process for forming the ferroelectric layers 174 and 274 can be a suitable deposition technique, such as CVD, PECVD, metal oxide chemical vapor deposition (MOCVD), ALD, RPALD, PEALD, MBD, or the like. In some embodiments, the material of the ferroelectric layers 174 and 274 is in contact with the top surface of the insulating layer 50B of the substrate 50. After the ferroelectric layers 174 and 274 are formed, a deposition process is performed to form gate electrodes 176 and 276 over the ferroelectric layers 174 and 274, respectively. In some embodiments, the deposition process may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.

[0146] See Figure 9A and Figure 9B ,in Figure 9A This is a perspective view of a semiconductor device. Figure 9B For along Figure 9A A cross-sectional view of line BB. The first gate structure 170 and the second gate structure 270 are patterned such that the first gate structure 170 and the second gate structure 270 surround the channel region 102CH of the first semiconductor layer 102 and the channel region 202CH of the second semiconductor layer 202, respectively. Subsequently, the source / drain regions 102SD1 and 102SD2 of the first semiconductor layer 102 and the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202 are exposed via the first gate structure 170 and the second gate structure 270 after the patterning process.

[0147] After the first gate structure 170 and the second gate structure 270 are patterned, a crystallization process may be performed to crystallize the ferroelectric layers 174 and 274. More specifically, the crystallization process may be an annealing process performed at a temperature of about 350°C to about 700°C. In some embodiments, the ferroelectric layers 174 and 274 may include an amorphous structure. The crystallization process may be performed such that the ferroelectric layers 174 and 274 include a fully crystalline structure or a partially crystalline structure; that is, each of the ferroelectric layers 174 and 274 is formed in a mixed crystalline-amorphous state and has a certain degree of structural order.

[0148] See Figure 10 ,in Figure 10 for Figure 9B The cross-sectional view following the cross-sectional view. A dielectric layer 60 is formed over the substrate 50 and covers the source / drain regions 102SD1 and 102SD2 of the first semiconductor layer 102 and the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202. In some embodiments, the dielectric layer 60 may be formed by, for example, depositing a dielectric material over the substrate 50 and then performing a planarization process until the second gate structure 270 is exposed.

[0149] See Figure 11 ,in Figure 11 for Figure 10 The cross-sectional view following the cross-sectional view. The dielectric layer 60 is patterned to expose portions of the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202. Subsequently, an etching process is performed to remove the exposed portions of the source / drain regions 202SD1 and 202SD2 of the second semiconductor layer 202 in order to shorten the second semiconductor layer 202.

[0150] See Figure 12 ,in Figure 12 for Figure 11 The cross-sectional view following the first. Dielectric material is deposited over substrate 50 to reconstruct dielectric layer 60. Subsequently, the top surface of dielectric layer 60 is higher than the top surface of the second metal gate structure 270.

[0151] See Figure 13 ,in Figure 13 for Figure 12 The cross-sectional view following the cross-sectional view. Conductive vias 71, 72, 73, 74, and 75 are formed in dielectric layer 60. Conductive vias 71, 72, 73, 74, and 75 can be formed, for example, by forming a patterned mask (not shown) over dielectric layer 60, wherein the patterned mask may include a number of openings corresponding to the locations of conductive vias 71, 72, 73, 74, and 75. An etching process is performed to remove portions of dielectric layer 60 through the openings of the patterned mask to form openings in dielectric layer 60. The patterned mask is then removed, and conductive material is deposited in the openings of dielectric layer 60. A planarization process, such as CMP, can be performed to remove excess conductive material outside the openings of dielectric layer 60, and the portion of conductive material retained in the openings can serve as conductive vias 71, 72, 73, 74, and 75. Conductive pads 81, 82, 83, and 84 are formed over dielectric layer 60. The conductive pads 81, 82, 83 and 84 can be formed, for example, by depositing a conductive layer over the dielectric layer 60 and then patterning the conductive layer according to a predetermined pattern.

[0152] Figure 14 This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 14 Similar to Figure 1C , and Figure 14 In this context, CFET 10 can function as a 2-to-1 MUX, and therefore CFET 10 will be referred to as 2-to-1 multiplexer 10 in the following discussion. Generally, a 2-to-1 multiplexer includes two inputs (e.g., input terminals IN1 and IN0), a selector (e.g., a polarization state terminal PS), and one output (e.g., input OUT). The output is connected to either of the inputs depending on the selection signal applied to the selector. Since there are two input signals, only two methods are possible to connect the input to the output; therefore, a selection is required to perform these operations.

[0153] Before operation, a write signal (e.g., a non-zero voltage) is first applied to the polarization state terminal PS to set the polarization state of the first transistor TR1 and the second transistor TR2. (As mentioned above...) Figure 1D As mentioned, once the first transistor TR1 and the second transistor TR2 are polarized, they can each have a relative polarity state. That is, when the first transistor TR1 has a polarization state P, the second transistor TR2 also has a polarization state P. For example, when the first transistor TR1 has a polarization state "1", the second transistor TR1 has a polarization state "0". Alternatively, when the first transistor TR1 has a polarization state "0", the second transistor TR1 has a polarization state "1".

[0154] Therefore, after setting the polarization states of the first transistor TR1 and the second transistor TR2, the 2-to-1 multiplexer 10 operates by applying input signals to the input terminals IN1 and IN0, and the output signal is read at the output terminal OUT. In some embodiments, the output signal can be expressed as During operation of the 2-to-1 multiplexer 10, a zero voltage (e.g., 0V) is applied to the polarization state terminal PS, resulting in a zero gate voltage (e.g., V). G =0) is applied to both the gate G1 of the first transistor TR1 and the gate G2 of the second transistor Tr2.

[0155] Figure 15A This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 15B and Figure 15C These are simulation results for a semiconductor device according to some embodiments of this disclosure. More specifically, Figures 15A to 15C The illustrations show embodiments where the polarization states of the first transistor TR1 and the second transistor TR2 are "1" and "0" respectively.

[0156] See Figure 15B and Figure 15C Before operation, a write signal is first applied to the polarization state terminal PS to set the polarization state of the first transistor TR1 and the second transistor TR2. In some embodiments, a positive write voltage is applied to the polarization state terminal PS. During the application of the positive write voltage, the input terminals IN1 and IN0 and the output terminal OUT may be biased to ground (e.g., 0V). The positive write voltage is applied to positively polarize the first transistor TR1 and the second transistor TR2, such that the first transistor TR1 and the second transistor TR2 are at V G At =0, it operates in depletion mode and enhancement mode respectively. In some embodiments, the positive write voltage may be approximately 3.0V.

[0157] After the first transistor TR1 and the second transistor TR2 are forward polarized, operation is performed on the 2-to-1 multiplexer 10. For example, input signals are applied to input terminals IN1 and IN0, respectively, and the output signal is read at the output terminal OUT. During operation, the polarization state terminal PS is biased at 0V, so that the gate voltages of both the first transistor TR1 and the second transistor TR2 are 0V (V). G =0). For example Figure 15A and Figure 15B As shown in the figure, when V G When V = 0, the first transistor TR1 has low resistance (e.g., high drain current level) and the second transistor TR2 has high resistance (e.g., low drain current level or no drain current). That is, when V G When = 0, the first transistor TR1 is turned on and the second transistor TR1 is turned off.

[0158] Therefore, in Figure 15A In this configuration, current can flow only from the input terminal IN1 through the first transistor TR1 (e.g., in the on state) to the output terminal OUT, while there is no current flowing through the second transistor TR2 (e.g., in the off state). That is, the output signal can be expressed as... exist Figure 15C As can also be seen, the input signal applied to the input terminal IN1 can be read at the output terminal OUT.

[0159] Figure 16A This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 16B and Figure 16C These are simulation results for a semiconductor device according to some embodiments of this disclosure. More specifically, Figures 16A to 16C The illustrations show embodiments where the polarization states of the first transistor TR1 and the second transistor TR2 are "0" and "1", respectively.

[0160] See Figure 16B and Figure 16C Before operation, a write signal is first applied to the polarization state terminal PS to set the polarization state of the first transistor TR1 and the second transistor TR2. In some embodiments, a negative write voltage is applied to the polarization state terminal PS. During the application of the negative write voltage, the input terminals IN1 and IN0 and the output terminal OUT may be biased to ground (e.g., 0V). The negative write voltage is applied to negatively polarize the first transistor TR1 and the second transistor TR2, such that the first transistor TR1 and the second transistor TR2 are at V G At =0, it operates in enhancement mode and depletion mode respectively. In some embodiments, the negative write voltage may be approximately -3.0V.

[0161] After the first transistor TR1 and the second transistor TR2 are negatively polarized, operation is performed on the 2-to-1 multiplexer 10. For example, input signals are applied to input terminals IN1 and IN0, respectively, and the output signal is read at the output terminal OUT. During operation, the polarization state terminal PS is biased at 0V, so that the gate voltages of both the first transistor TR1 and the second transistor TR2 are 0V (V). G =0). For example Figure 16A and Figure 16B As shown in the figure, when V G When V = 0, the first transistor TR1 has high resistance (e.g., low drain current level or no drain current) and the second transistor TR2 has low resistance (e.g., high drain current level). That is, when V G When = 0, the first transistor TR1 is off, and the second transistor TR1 is on.

[0162] Therefore, in Figure 16A In this configuration, current can flow only from the input terminal IN0 through the second transistor TR2 (e.g., in the on state) to the output terminal OUT, while no current flows through the first transistor TR1 (e.g., in the off state). That is, the output signal can be expressed as... exist Figure 16C As can also be seen, the input signal applied to the input terminal IN0 can be read at the output terminal OUT.

[0163] Figure 17 This is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 17 In the circuit diagram, there are CFETs 10A, 10B, and 10C that are electrically coupled to each other. Each of CFETs 10A, 10B, and 10C may include the same configuration as CFET 10 discussed above, and therefore, the relevant details will not be repeated for the sake of brevity. Figure 17In the circuit diagram, CFET 10A, 10B, and 10C can act as 2-to-1 multiplexers, and therefore CFET 10A, 10B, and 10C can also be referred to as 2-to-1 multiplexers 10A, 10B, and 10C in the following discussion.

[0164] exist Figure 17 In CFET 10A, the source of the second transistor TR2 is electrically coupled to the input terminal IN0, and the source of the first transistor TR1 is electrically connected to the input terminal IN1. In CFET 10B, the source of the second transistor TR2 is electrically connected to the input terminal IN2, and the source of the first transistor TR1 is electrically connected to the input terminal IN3. The gates of the first transistor TR1 and the second transistor TR2 in CFET 10A and the gates of the first transistor TR1 and the second transistor TR2 in CFET 10B are electrically coupled to the polarization state terminal PS1. Therefore, the first transistors TR1 and TR2 in CFET 10A and the first transistors TR1 and TR2 in CFET 10B are simultaneously polarized. The drain of the second transistor TR2 in CFET 10A and the drain of the first transistor TR1 in CFET 10A are electrically coupled to the source of the first transistor TR1 in CFET 10C. On the other hand, the drain of the second transistor TR2 of CFET 10B and the drain of the first transistor TR1 of CFET 10B are electrically coupled to the source of the second transistor TR2 of CFET 10C. The gates of the first transistor TR1 and the second transistor TR2 of CFET 10C are electrically coupled to the polarization state terminal PS2. The drains of the first transistor TR1 and the second transistor TR2 of CFET 10C are electrically coupled to the output terminal OUT.

[0165] Figure 18A , Figure 19A , Figure 20A and Figure 21A The present invention provides circuit diagrams of semiconductor devices in different polarization states according to some embodiments of the present disclosure. Figure 18B , Figure 19B , Figure 20B and Figure 21B Simulation results for semiconductor devices in different polarization states according to some embodiments of this disclosure.

[0166] See Figure 18A and Figure 18B .exist Figure 18A and Figure 18BIn one embodiment, a positive write voltage (state 1) is applied to the polarization state terminal PS1, and a negative write voltage (state 0) is applied to the polarization state terminal PS2, so as to set the polarization states of the first transistor TR1 and the second transistor TR2 of CFET 10A, 10B and 10C respectively.

[0167] In response to a positive write voltage applied to the polarization terminal PS1, the first transistor TR1 and the second transistor TR2 of CFETs 10A and 10B are forward polarized. That is, when V G When V = 0, the first transistor TR1 of CFET 10A and 10B is turned on, while the second transistor TR2 of CFET 10A and 10B is turned off. Conversely, in response to a negative write voltage applied to the polarization state terminal PS2, the first transistor TR1 and the second transistor TR2 of CFET 10C are negatively polarized. That is, when V = 0, G When the voltage is 0, the first transistor TR1 of the CFET 10C is off, while the second transistor TR2 of the CFET 10C is on. It should be understood that during the application of write voltage to the polarization state terminals PS1 and PS2, the input terminals IN0, IN1, IN2, and IN3 and the output terminal OUT are biased at 0V.

[0168] Therefore, during operation, polarization state terminals PS1 and PS2 are biased to 0V, and input signals are applied to input terminals IN0, IN1, IN2, and IN3 respectively, while the output signal is read at the output terminal OUT. Figure 18A As illustrated, current can flow from the input terminal IN2 through the first transistor TR1 of CFET 10B (e.g., in the on state) and the second transistor TR2 of CFET 10C (e.g., in the on state) to the output terminal OUT. Figure 18B As can also be seen, the input signal applied to the input terminal IN2 can be read at the output terminal OUT.

[0169] See Figure 19A and Figure 19B .exist Figure 19A and Figure 19B In one embodiment, a positive write voltage (state 1) is applied to the polarization state terminal PS1 and a positive write voltage (state 1) is applied to the polarization state terminal PS2 to set the polarization states of the first transistor TR1 and the second transistor TR2 of CFETs 10A, 10B and 10C, respectively.

[0170] In response to a positive write voltage applied to the polarization terminal PS1, the first transistor TR1 and the second transistor TR2 of CFETs 10A and 10B are forward polarized. That is, when V GWhen V = 0, the first transistor TR1 of CFET 10A and 10B is turned on, while the second transistor TR2 of CFET 10A and 10B is turned off. Similarly, in response to a positive write voltage applied to the polarization state terminal PS2, the first transistor TR1 and the second transistor TR2 of CFET 10C are forward polarized. That is, when V G When the voltage is 0, the first transistor TR1 of the CFET 10C is turned on, while the second transistor TR2 of the CFET 10C is turned off. It should be understood that during the application of write voltage to the polarization state terminals PS1 and PS2, the input terminals IN0, IN1, IN2, and IN3 and the output terminal OUT are biased at 0V.

[0171] Therefore, during operation, polarization state terminals PS1 and PS2 are biased to 0V, and input signals are applied to input terminals IN0, IN1, IN2, and IN3 respectively, while the output signal is read at the output terminal OUT. Figure 19A As illustrated, current can flow from the input terminal IN0 through the first transistor TR1 of CFET 10A (e.g., in the on state) and the first transistor TR1 of CFET 10C (e.g., in the on state) to the output terminal OUT. Figure 19B As can also be seen, the input signal applied to the input terminal IN0 can be read at the output terminal OUT.

[0172] See Figure 20A and Figure 20B .exist Figure 20A and Figure 20B In one embodiment, a negative write voltage (state 0) is applied to the polarization state terminal PS1, and a positive write voltage (state 1) is applied to the polarization state terminal PS2, so as to set the polarization states of the first transistor TR1 and the second transistor TR2 of CFET 10A, 10B and 10C respectively.

[0173] In response to a negative write voltage applied to the polarization terminal PS1, the first transistor TR1 and the second transistor TR2 of CFETs 10A and 10B are negatively polarized. That is, when V G When V = 0, the first transistor TR1 of CFET 10A and 10B is off, while the second transistor TR2 of CFET 10A and 10B is on. Conversely, in response to a positive write voltage applied to the polarization state terminal PS2, the first transistor TR1 and the second transistor TR2 of CFET 10C are forward polarized. That is, when V = 0, GWhen the voltage is 0, the first transistor TR1 of the CFET 10C is turned on, while the second transistor TR2 of the CFET 10C is turned off. It should be understood that during the application of write voltage to the polarization state terminals PS1 and PS2, the input terminals IN0, IN1, IN2, and IN3 and the output terminal OUT are biased at 0V.

[0174] Therefore, during operation, polarization state terminals PS1 and PS2 are biased to 0V, and input signals are applied to input terminals IN0, IN1, IN2, and IN3 respectively, while the output signal is read at the output terminal OUT. Figure 20A As illustrated, current can flow from the input terminal IN1 through the second transistor TR2 of CFET 10A (e.g., in the on state) and the first transistor TR1 of CFET 10C (e.g., in the on state) to the output terminal OUT. Figure 20B As can also be seen, the input signal applied to the input terminal IN1 can be read at the output terminal OUT.

[0175] See Figure 22A and Figure 22B .exist Figure 20A and Figure 20B In one embodiment, a negative write voltage (state 0) is applied to the polarization state terminal PS1 and a negative write voltage (state 0) is applied to the polarization state terminal PS2 to set the polarization states of the first transistor TR1 and the second transistor TR2 of CFETs 10A, 10B and 10C, respectively.

[0176] In response to a negative write voltage applied to the polarization terminal PS1, the first transistor TR1 and the second transistor TR2 of CFETs 10A and 10B are negatively polarized. That is, when V G When V = 0, the first transistor TR1 of CFET 10A and 10B is turned off, while the second transistor TR2 of CFET 10A and 10B is turned on. Similarly, in response to a negative write voltage applied to the polarization state terminal PS2, the first transistor TR1 and the second transistor TR2 of CFET 10C are negatively polarized. That is, when V G When the voltage is 0, the first transistor TR1 of the CFET 10C is off, while the second transistor TR2 of the CFET 10C is on. It should be understood that during the application of write voltage to the polarization state terminals PS1 and PS2, the input terminals IN0, IN1, IN2, and IN3 and the output terminal OUT are biased at 0V.

[0177] Therefore, during operation, polarization state terminals PS1 and PS2 are biased to 0V, and input signals are applied to input terminals IN0, IN1, IN2, and IN3 respectively, while the output signal is read at the output terminal OUT. Figure 21AAs illustrated, current can flow from the input terminal IN3 through the second transistor TR2 of CFET 10A (e.g., in the on state) and the second transistor TR2 of CFET 10C (e.g., in the on state) to the output terminal OUT. Figure 21B As can also be seen, the input signal applied to the input terminal IN3 can be read at the output terminal OUT.

[0178] Figure 22A , Figure 22B , Figure 22C and Figure 22D The following are circuit diagrams, equivalent circuits, truth tables, and simulation results of semiconductor devices according to some embodiments of this disclosure. More specifically, when the input terminal IN0 is grounded (e.g., biased at 0V), the AND logic function can be presented between the polarization state terminal PS and the input terminal IN1. Therefore, CFET 10 may also be referred to as AND gate 10 in the following discussion.

[0179] To operate AND gate 10, a write operation is first performed by applying a polarization signal to the polarization state terminal PS to polarize the first transistor TR1 and the second transistor TR2 of AND gate 10. During the write operation, the input terminal IN1 is biased at 0V. After the write operation is complete, a read operation is performed by applying an input signal to the input terminal IN1, and the output signal is read at the output terminal OUT. During the read operation, the polarization state terminal PS is biased at 0V.

[0180] For example, during a write operation, if a positive voltage (logic level "1") is applied to the polarization state terminal PS, then the first transistor TR1 and the second transistor TR2 of AND gate 10 are forward polarized. That is, when V G When the input voltage is 0, the first transistor TR1 is on, while the second transistor TR2 is off. Therefore, during a read operation, current can flow only from the input terminal IN1 through the first transistor TR1 (e.g., in the on state) to the output terminal OUT. Thus, when a positive voltage (logic level "1") is applied to the input terminal IN1, the positive voltage (logic level "1") can be read at the output terminal OUT. When zero voltage (logic level "0") is applied to the input terminal IN1, zero voltage (logic level "0") can be read at the output terminal OUT.

[0181] On the other hand, if a negative voltage (logic level "0") is applied to the polarization state terminal PS, then the first transistor TR1 and the second transistor TR2 of AND gate 10 are negatively polarized. That is, when V GWhen IN1 = 0, the first transistor TR1 is off, while the second transistor TR2 is on. Therefore, during a read operation, current can flow only from the input terminal IN0 through the second transistor TR2 (e.g., in the on state) to the output terminal OUT. However, the input terminal IN0 is grounded to GND, and therefore only the voltage (logic level "0") can be read at the output terminal OUT, regardless of the input signal applied to the input terminal IN1.

[0182] Figure 22B The diagram illustrates the equivalent circuit of an AND gate structure. The AND gate has a polarization state terminal PS and an input terminal IN1 as inputs, and an output terminal OUT as an output. The polarization state terminal PS is connected to a latching element LA. In some embodiments, the latching element LA can be a first transistor TR1 and a second transistor TR2, which allows previous data to be stored during a write operation and can also serve as an input to the AND gate.

[0183] Figure 23A , Figure 23B , Figure 23C and Figure 23D The following are circuit diagrams, equivalent circuits, truth tables, and simulation results of semiconductor devices according to some embodiments of the present disclosure. More specifically, when the input terminal IN1 is biased at a high voltage level during a read operation, the OR logic function can be presented between the polarization state terminal PS and the input terminal IN0. Therefore, CFET 10 may also be referred to as OR gate 10 in the following discussion.

[0184] To operate OR gate 10, a write operation is first performed by applying a polarization signal to the polarization state terminal PS to polarize the first transistor TR1 and the second transistor TR2 of OR gate 10. During the write operation, input terminals IN0 and IN1 are biased at 0V. After the write operation is complete, a read operation is performed by applying an input signal to input terminal IN0, and the output signal is read at output terminal OUT. During the read operation, the polarization state terminal PS is biased at 0V, and input terminal IN1 is biased at a high voltage level. Here, "high voltage level" can be a positive voltage level greater than 0V, and is substantially equal to the logic level "1" identified by output terminal OUT.

[0185] For example, during a write operation, if a positive voltage (logic level "1") is applied to the polarization state terminal PS, then the first transistor TR1 and the second transistor TR2 of OR gate 10 are forward polarized. That is, when V GWhen the input voltage is 0, the first transistor TR1 is on, while the second transistor TR2 is off. Therefore, during a read operation, current can flow only from the input terminal IN1 through the first transistor TR1 (e.g., in the on state) to the output terminal OUT. However, the input terminal IN1 is biased at a constant high voltage level (logic level "1"), and therefore only the high voltage level (logic level "1") can be read at the output terminal OUT regardless of the input signal applied to the input terminal IN0.

[0186] On the other hand, if a negative voltage (logic level "0") is applied to the polarization state terminal PS, then the first transistor TR1 and the second transistor TR2 of AND gate 10 are negatively polarized. That is, when V G When the input voltage is 0, the first transistor TR1 is off, and the second transistor TR2 is on. Therefore, during a read operation, current can flow only from the input terminal IN0 through the second transistor TR2 (e.g., in the on state) to the output terminal OUT. Thus, when a positive voltage (logic level "1") is applied to the input terminal IN0, the positive voltage (logic level "1") can be read at the output terminal OUT. When zero voltage (logic level "0") is applied to the input terminal IN0, zero voltage (logic level "0") can be read at the output terminal OUT.

[0187] Figure 23B The diagram illustrates the equivalent circuit of an OR gate, where the OR gate has a polarization state terminal PS and an input terminal IN0 as inputs, and an output terminal OUT as an output. The polarization state terminal PS is connected to a latching element LA. In some embodiments, the latching element LA may be a first transistor TR1 and a second transistor TR2, which allows previous data to be stored during a write operation and can also serve as the input to the OR gate.

[0188] Figure 24A , Figure 24B , Figure 24C and Figure 24D The following are circuit diagrams, equivalent circuits, truth tables, and simulation results of semiconductor devices according to some embodiments of the present disclosure. More specifically, when input terminals IN0 and IN1 are biased by supplementary signal voltages during a read operation, the XOR logic function can be presented between the polarization state terminal PS and input terminal IN0. That is, during a read operation, terminals IN0 and IN1 are biased by relative logic levels (e.g., ...). Bias voltage. Therefore, CFET 10 can also be referred to as XOR gate 10 in the following discussion.

[0189] For example, during a write operation, if a positive voltage (logic level "1") is applied to the polarization state terminal PS, then the first transistor TR1 and the second transistor TR2 of OR gate 10 are forward polarized. That is, when VG When the input voltage is 0, the first transistor TR1 is on, and the second transistor TR2 is off. Therefore, during a read operation, current can flow only from the input terminal IN1 through the first transistor TR1 (e.g., in the on state) to the output terminal OUT. Therefore, when a positive voltage (logic level "1") is applied to the input terminal IN0, a zero voltage (logic level "0") is applied to the input terminal IN1. Therefore, the zero voltage (logic level "0") can be read at the output terminal OUT. When a zero voltage (logic level "0") is applied to the input terminal IN0, a positive voltage (logic level "1") is applied to the input terminal IN1. Therefore, the positive voltage (logic level "1") can be read at the output terminal OUT.

[0190] On the other hand, if a negative voltage (logic level "0") is applied to the polarization state terminal PS, then the first transistor TR1 and the second transistor TR2 of AND gate 10 are negatively polarized. That is, when V G When the input voltage is 0, the first transistor TR1 is off, and the second transistor TR2 is on. Therefore, during a read operation, current can flow only from the input terminal IN0 through the second transistor TR2 (e.g., in the on state) to the output terminal OUT. Therefore, when a positive voltage (logic level "1") is applied to the input terminal IN0, a zero voltage (logic level "0") is applied to the input terminal IN1. Therefore, a positive voltage (logic level "1") can be read at the output terminal OUT. When a zero voltage (logic level "0") is applied to the input terminal IN0, a positive voltage (logic level "1") is applied to the input terminal IN1. Therefore, a zero voltage (logic level "0") can be read at the output terminal OUT.

[0191] Figure 24B The diagram illustrates the equivalent circuit of an XOR gate, where the OR gate has a polarization state terminal PS and an input terminal IN0 as inputs, and an output terminal OUT as an output. The polarization state terminal PS is connected to a latching element LA. In some embodiments, the latching element LA may be a first transistor TR1 and a second transistor TR2, which allows previous data to be stored during a write operation and can also serve as an input to the XOR gate.

[0192] Figure 25 This is a perspective view of a semiconductor device according to some embodiments of this disclosure. Please note that... Figure 25 Some components mentioned above Figure 1A and Figure 1BAs described, such components are designated as identical, and related details will not be repeated for simplicity. A complementary FET (CFET) 20 is provided, and its manufacturing method will be disclosed in the following disclosure. More specifically, CFET 10 is a complementary ferroelectric FET (CFeFET), which will be discussed below, comprising ferroelectric transistors stacked on top of each other.

[0193] CFET 20 includes a first transistor TR1, and a second transistor TR2 is vertically positioned above the first transistor TR1. Regarding the first transistor TR1, it includes a first semiconductor layer 102, a first metal gate structure 170 surrounding the first semiconductor layer 102, and source / drain epitaxial structures 140A and 140B on opposite sides of the first semiconductor layer 102. Similarly, the second transistor TR2 includes a second semiconductor layer 202, a second metal gate structure 270 surrounding the second semiconductor layer 202, and source / drain epitaxial structures 240A and 240B on opposite sides of the second semiconductor layer 202. In some embodiments, gate electrodes 176 and 276 are made of different materials.

[0194] CFET 20 further includes a source / drain contact 191 that contacts the bottom surface of the source / drain epitaxial structure 140A, a source / drain contact 192 that contacts the top surface of the source / drain epitaxial structure 240A, a gate via 193 that contacts the top surface of the second metal gate structure 270, and a source / drain contact 194 that passes through the source / drain epitaxial structure 240B and contacts the top surface of the source / drain epitaxial structure 140B.

[0195] Figures 26 to 31 The illustrations depict methods for forming a semiconductor device at various stages according to some embodiments of this disclosure. More specifically, Figures 26 to 31 The diagram is used to form Figure 25 The method of CFET 20, in which Figures 26 to 31 For along Figure 25 The cross-sectional view of line AA. Although Figures 26 to 31 The description is a series of actions, but it should be understood that these actions are not limited to a specific order that can be changed in other embodiments, and the disclosed method can also be applied to other structures. In other embodiments, some actions illustrated and / or described may be omitted in whole or in part. Please note that Figures 26 to 31 Some embodiments may be similar to those described above, and therefore related details will not be repeated for the sake of brevity.

[0196] See Figure 26The illustration depicts substrate 100. Generally, substrate 100 may comprise a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulating layer beneath a thin semiconductor layer, which is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically comprise silicon, a crystalline semiconductor material, but may include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, and the like), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and the like), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0197] A semiconductor stack ST is formed over substrate 100. The semiconductor stack ST includes a first stack of alternating semiconductor layers 102 and 104, a semiconductor layer 105 disposed over the first stack, and a second stack of alternating semiconductor layers 202 and 204 over semiconductor layer 105. In some embodiments, semiconductor layers 102 and 202 may be made of germanium-free pure silicon. Semiconductor layers 102 and 202 may also be substantially pure silicon layers, for example, layers having a germanium percentage of less than about 1%. Semiconductor layers 104, 105, and 204 may be made of silicon-germanium, and semiconductor layer 105 may include a higher composite than semiconductor layers 104 and 204. For example, the germanium percentage (atomic percentage concentration) of semiconductor layer 105 is in the range of about 60% to about 80%, and the germanium percentage (atomic percentage concentration) of semiconductor layers 104 and 204 is in the range of about 20% to about 40%. In some embodiments, semiconductor layers 102, 104, 105, 202, and 204 may be deposited using suitable deposition processes, such as selective epitaxial growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable processes. In some embodiments, semiconductor layers 104 and 204 may be removed during a replacement gate (RPG) process, and therefore semiconductor layers 104 and 204 may also be referred to as sacrificial layers.

[0198] See Figure 27A dummy gate structure 130 is formed above the substrate 100 and intersects with the semiconductor stack ST. In some embodiments, each of the dummy gate structures 130 includes a dummy gate dielectric 132 and a dummy gate electrode 134 above the dummy gate dielectric 132. The dummy gate dielectric 132 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate electrode 134 may be a conductive or non-conductive material and is selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicides, metal oxides, and metals.

[0199] The dummy gate electrode 134 and dummy gate dielectric 132 can be formed, for example, by depositing a dummy dielectric layer and a dummy gate layer over a substrate 100, forming a patterned mask MA1 over the dummy gate layer, and then performing an etching process on the dummy dielectric layer and the dummy gate layer using the patterned mask MA1 as an etching mask. In some embodiments, the dummy gate electrode 134 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, or other techniques for depositing selected materials. In some embodiments, the dummy gate dielectric 132 can be formed by thermal oxidation.

[0200] In some embodiments, each of the patterned masks MA1 includes a first hard mask 330 and a second hard mask 332 above the first hard mask 330. The first hard mask 330 and the second hard mask layer 332 may be made of different materials. In some embodiments, the first hard mask 330 may be formed of silicon nitride, and the second hard mask 332 may be formed of silicon oxide.

[0201] Gate spacers 115 are formed on the opposite sidewalls of each of the dummy gate structures 130. In some embodiments, gate spacers 115 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, gate spacers 115 may be formed, for example, by depositing a spacer layer blanket over a substrate and then performing an isotropic etching process to remove the horizontal portion of the spacer layer, such that the vertical portion of the spacer layer remains on the sidewall of the dummy gate structure 130. In some embodiments, the remaining vertical portion of the spacer layer may be referred to as gate spacer 115. The spacer layer may be deposited using techniques such as CVD, ALD, or similar methods.

[0202] See Figure 28 An etching process is performed to remove portions of the stacked ST by using a dummy gate structure 130 and gate spacers 115 as an etching mask to form source / drain openings O1 in the stacked ST. In some embodiments, the etching process may be dry etching, wet etching, or a combination thereof. In some embodiments, the bottom end of the source / drain openings O1 may be below the bottom semiconductor layer 104.

[0203] See Figure 29 Semiconductor layers 104 and 204 are laterally etched to form sidewall recesses. Subsequently, internal spacers 116 are formed in the sidewall recesses at opposite ends of each of semiconductor layers 104 and 204.

[0204] Source / drain contacts 191 are formed in the bottom portion of source / drain opening O1. In some embodiments, source / drain contacts 191 can be formed, for example, by depositing conductive material in source / drain opening O1 and then etching the conductive material back to the desired location.

[0205] Source / drain epitaxial structures 140A and 140B are formed in the opening O1 and at opposite ends of each semiconductor layer 102, respectively. The source / drain epitaxial structures 140A and 140B can be formed by a suitable deposition process, such as selective epitaxial growth (SEG). In some embodiments, a placement process can be performed on the source / drain epitaxial structures 140A and 140B. For example, the placement process may include an n-type dopant.

[0206] A contact etch stop layer (CESL) 155 is formed to cover the first source / drain epitaxial structure 140, and an interlayer dielectric (ILD) layer 152 is formed above the CESL layer 155. Next, an etch-back process is performed to lower the top surfaces of the CESL 155 and ILD layer 152, exposing the sidewalls of the semiconductor layer 202 via source / drain openings O1. In some embodiments, the CESL 155 and ILD layer 152 may be collectively referred to as the isolation structure 150. In some embodiments, the topmost semiconductor layer 102 and the bottommost semiconductor layer 202 are in contact with the CESL 155 of the isolation structure 150.

[0207] In some embodiments, CESL 155 may be a nitride (such as silicon nitride), and ILD layer 152 may be an oxide (such as silicon oxide). In some embodiments, CESL 155 may be a dielectric layer comprising silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, ILD layer 152 may comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. CESL 155 and ILD layer 152 may be formed using, for example, CVD, ALD, or other suitable techniques.

[0208] Source / drain epitaxial structures 240A and 240B are formed at opposite ends of each of the semiconductor layer 202. In some embodiments, the second source / drain epitaxial structure 240 may be formed by a selective epitaxy growth (SEG) process. The SEG process selectively grows semiconductor material on an exposed semiconductor surface, such as the exposed surface of the semiconductor layer 202. In some embodiments, a placement process may be performed on the second source / drain epitaxial structure 240. For example, the placement process may include a p-type dopant.

[0209] A contact etch stop layer (CESL) 255 is formed to cover the second source / drain epitaxial structure 240. An interlayer dielectric (ILD) layer 252 is then formed over the CESL 255. Next, a planarization process, such as CMP, is performed to remove excess material from the CESL 255 and ILD layer 252 until the dummy gate structure 130 is exposed. In some embodiments, a patterned mask MA1 is removed during the planarization process. In some embodiments, the CESL 255 and ILD layer 252 may be collectively referred to as the isolation structure 250. The materials of the CESL 255 and ILD layer 252 may be similar to the materials of the CESL 155 and ILD layer 152, respectively. For example, the CESL 255 may be a nitride (such as silicon nitride), and the ILD layer 252 may be an oxide (such as silicon oxide).

[0210] See Figure 30 The dummy gate structure 130 is removed to form a gate trench between each pair of gate spacers 115. Next, an etching process is performed to remove semiconductor layers 104 and 204 via the gate trenches, such that semiconductor layers 102 and 202 are suspended above the substrate 100. Then, semiconductor layer 105 is replaced by an isolation layer 117.

[0211] Interface layers 172 and 272 are formed on the exposed surfaces of semiconductor layers 102 and 202, respectively. Ferroelectric layers 174 and 274 are then formed over interface layers 172 and 272, respectively. In some embodiments, interface layers 172 and 272 can be formed using the same deposition process, and ferroelectric layers 174 and 274 can be formed using the same deposition process.

[0212] After the interface layers 172 and 272 and the ferroelectric layers 174 and 274 are formed, a gate electrode 176 is formed in the gate trench and above the ferroelectric layer 174. The gate electrode 176 is then etched back. Thus, a first metal gate structure 170 is formed. The gate electrode 276 is then formed in the gate trench and above the first metal gate structure 170. Thus, a second metal gate structure 270 is formed. In some embodiments, the gate electrodes 176 and 276 are made of different materials.

[0213] After the first gate structure 170 and the second gate structure 270 are formed, a crystallization process may be performed to crystallize the ferroelectric layers 174 and 274. More specifically, the crystallization process may be an annealing process performed at a temperature of about 350°C to about 700°C. In some embodiments, the ferroelectric layers 174 and 274 may include an amorphous structure. The crystallization process may be performed such that the ferroelectric layers 174 and 274 include a fully crystalline structure or a partially crystalline structure; that is, each of the ferroelectric layers 174 and 274 is formed in a mixed crystalline-amorphous state and has a certain degree of structural order.

[0214] See Figure 31 An etch stop layer (ESL) 180 is formed over the isolation structure 250 and the second metal gate structure 270. An interlayer dielectric (ILD) layer 185 is then formed over the ESL 180. The materials of the ESL 180 and ILD layer 185 can be similar to those of the ESL 155 and ILD layer 152, respectively. For example, the ESL 180 can be a nitride (such as silicon nitride), and the ILD layer 185 can be an oxide (such as silicon oxide). The ESL 180 and ILD layer 185 can be formed using, for example, CVD, ALD, or other suitable techniques.

[0215] Next, source / drain contacts 192, gate vias 193, and source / drain contacts 194 are formed. More specifically, source / drain contacts 192 are formed in the ESL 180, ILD layer 185, and isolation structure 250, and are in contact with the top surface of the source / drain epitaxial structure 240A. Gate vias 193 are formed in the ESL 180 and ILD layer 185, and are in contact with the second metal gate structure 270. Source / drain contacts 192 are formed to pass through the ESL 180, ILD layer 185, isolation structure 250, source / drain epitaxial structure 240B, and isolation structure 150, and are in contact with the top surface of the source / drain epitaxial structure 140B.

[0216] Please note, Figure 31 The circuit diagram of the CFET 20 structure and Figure 1C The circuit diagrams are the same. Regarding... Figure 31 and Figure 1C The gate G1, source S1, and drain D1 of the first transistor TR1 can be a first metal gate structure 170, a source / drain epitaxial structure 140A, and a source / drain epitaxial structure 140B, respectively. Similarly, the gate G2, source S2, and drain D2 of the second transistor TR2 can be a second metal gate structure 270, a source / drain epitaxial structure 240A, and a source / drain epitaxial structure 240B, respectively. Figure 31 The source / drain contact 191, source / drain contact 192, gate via 193, and source / drain contact 194 can respectively serve as Figure 1C The input terminals are IN1, IN0, PS (polarization status), and OUT (output).

[0217] It should be understood that, as regarding Figures 25 to 31 The CFET 20 discussed above can also have the various applications described above. For example, CFET 10 (or...) Figure 17 The CFETs 10A, 10B, and 10C in the above can be replaced by the CFET 20. In detail, the CFET 20 can act as a 2 to 1 multiplexer, AND gate, OR gate, and / or XOR gate as discussed above, while related details are not repeated for the sake of brevity.

[0218] As can be seen from the foregoing embodiments, this disclosure provides advantages in the manufacture of integrated circuits. However, it should be understood that other embodiments may offer additional advantages, and not all advantages need to be disclosed herein, nor is any particular advantage claimed for all embodiments. Embodiments of this disclosure provide a method for forming a CFET having a first transistor and a second transistor perpendicularly above the first transistor. The first and second transistors may be ferroelectric transistors and may include opposite conductivity types. This configuration allows both the first and second ferroelectric transistors to switch back and forth between a first state (enhancement mode) and a second state (depletion mode). Embodiments of this disclosure also provide various applications of the CFET, such as 2-to-1 multiplexers. Furthermore, based on the 2-to-1 multiplexer configuration, the CFET can also be used to implement reconfigurable AND / OR / XOR logic gates.

[0219] In some embodiments disclosed herein, a method includes: forming a first semiconductor layer over a substrate and vertically forming a second semiconductor layer over the first semiconductor layer; forming a first ferroelectric layer and a second ferroelectric layer surrounding the first semiconductor layer and the second semiconductor layer, respectively; forming a first gate electrode and a second gate electrode over the first ferroelectric layer and the second ferroelectric layer, respectively, wherein the first gate electrode is in contact with the second gate electrode; and forming a conductive feature to electrically connect a drain region of the first semiconductor layer and a drain region of the second semiconductor layer.

[0220] In some embodiments, the first gate electrode and the second gate electrode are made of the same material.

[0221] In some embodiments, the method further includes etching back the first gate electrode before forming the second gate electrode, wherein the first gate electrode and the second gate electrode are made of a variety of different materials.

[0222] In some embodiments, the method further includes performing an annealing process to crystallize the first ferroelectric layer and the second ferroelectric layer.

[0223] In some embodiments, the first ferroelectric layer and the second ferroelectric layer are further formed along a top surface of the substrate using a material.

[0224] In some embodiments, the method further includes forming a first interface layer and a second interface layer surrounding the first semiconductor layer and the second semiconductor layer, respectively, before forming the first ferroelectric layer and the second ferroelectric layer.

[0225] In some embodiments, the method further includes forming a dummy gate structure over the first semiconductor layer and the second semiconductor layer; and removing the dummy gate structure before forming the first gate electrode and the second gate electrode.

[0226] In some embodiments, the method further includes performing a first implantation process to dope a plurality of n-type dopants in a source region and a drain region of the first semiconductor layer; and performing a second implantation process to dope a plurality of p-type dopants in a source region and a drain region of the second semiconductor layer.

[0227] In some embodiments disclosed herein, a method includes: a structure comprising a first ferroelectric transistor and a second ferroelectric transistor perpendicularly above the first ferroelectric transistor; applying a write voltage to a gate of the first ferroelectric transistor and a gate of the second ferroelectric transistor to set the polarization states of the first ferroelectric transistor and the second ferroelectric transistor; and after applying the write voltage, applying a zero voltage to the gate of the first ferroelectric transistor and the gate of the second ferroelectric transistor such that one of the first ferroelectric transistor and the second ferroelectric transistor exhibits a high drain current level and the other of the first ferroelectric transistor and the second ferroelectric transistor exhibits a low drain current level, the low drain current level being less than the high drain current level.

[0228] In some embodiments, the method further includes: applying a first input signal and a second input signal to a source region of the first ferroelectric transistor and a source region of the second ferroelectric transistor, respectively, while applying the zero voltage to the gate of the first ferroelectric transistor and the gate of the second ferroelectric transistor; and after applying the first input signal and the second input signal, reading an output signal from a terminal connected to a drain region of the first ferroelectric transistor and a drain region of the second ferroelectric transistor.

[0229] In some embodiments, the write voltage is a positive voltage such that during the application of the first input signal and the second input signal and the reading of the output signal, the first ferroelectric transistor presents the high drain current level and the second ferroelectric transistor presents the low drain current level, and the output signal is the same as the first input signal.

[0230] In some embodiments, the write voltage is a negative voltage such that during the application of the first input signal and the second input signal and the reading of the output signal, the first ferroelectric transistor presents the low drain current level and the second ferroelectric transistor presents the high drain current level, and the output signal is the same as the second input signal.

[0231] In some embodiments, during the application of the write voltage, a source region of the first ferroelectric transistor and a source region of the second ferroelectric transistor are biased with zero voltage.

[0232] In some embodiments, the first ferroelectric transistor and the second ferroelectric transistor have opposite conductivity types.

[0233] In some embodiments, the gate of the first ferroelectric transistor and the gate of the second ferroelectric transistor each include: an interface layer; a ferroelectric layer above the interface layer; and a gate electrode layer above the ferroelectric layer.

[0234] In some embodiments disclosed herein, a semiconductor device includes: a first transistor above a substrate, comprising a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer and including a first ferroelectric layer, and a first source region and a first drain region on a plurality of opposite sides of the first semiconductor channel layer. A second transistor is above the substrate and includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer and including a second ferroelectric layer, and a second source region and a second drain region on a plurality of opposite sides of the second semiconductor channel layer. In a cross-sectional view, the second semiconductor channel layer is shorter than the first semiconductor channel layer. An output terminal is electrically connected to the first drain region of the first transistor and the second drain region of the second transistor. A material of the first ferroelectric layer is in contact with a top surface of the substrate.

[0235] In some embodiments, the second transistor is positioned vertically above the first transistor, and the first transistor and the second transistor are an n-type transistor and a p-type transistor, respectively.

[0236] In some embodiments, the first gate structure and the second gate structure are made of the same material.

[0237] In some embodiments, the semiconductor device further includes a first input terminal electrically connected to the first source region of the first transistor; and a second input terminal electrically connected to the second source region of the second transistor, wherein the first input terminal and the second input terminal are spaced apart from each other.

[0238] In some embodiments, the semiconductor device further includes a material of the first ferroelectric layer in contact with a top surface of the substrate.

[0239] In some embodiments, the semiconductor device further includes a polarization state terminal electrically connected to the first gate structure of the first transistor and the second gate structure of the second transistor.

[0240] In some embodiments, the substrate includes a semiconductor layer and an insulating layer, wherein the material of the first ferroelectric layer is in contact with the insulating layer of the substrate.

[0241] In some embodiments disclosed herein, a semiconductor device includes: a first transistor above a substrate, comprising a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer and including a first ferroelectric layer, and a first source region and a first drain region on a plurality of opposite sides of the first semiconductor channel layer. A second transistor is above the substrate and includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer and including a second ferroelectric layer, and a second source region and a second drain region on a plurality of opposite sides of the second semiconductor channel layer. In a cross-sectional view, the second semiconductor channel layer is shorter than the first semiconductor channel layer. An output terminal is electrically connected to the first drain region of the first transistor and the second drain region of the second transistor. A material of the first ferroelectric layer is in contact with a top surface of the substrate. The substrate includes a semiconductor layer and an insulating layer, wherein the material of the first ferroelectric layer is in contact with the insulating layer of the substrate.

[0242] In some embodiments disclosed herein, a semiconductor device includes: a first transistor above a substrate, comprising a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer and including a first ferroelectric layer, and a first source region and a first drain region on a plurality of opposite sides of the first semiconductor channel layer. A second transistor above the substrate includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer and including a second ferroelectric layer, and a second source region and a second drain region on a plurality of opposite sides of the second semiconductor channel layer. In a cross-sectional view, the second semiconductor channel layer is shorter than the first semiconductor channel layer. An output terminal is electrically connected to the first drain region of the first transistor and the second drain region of the second transistor. A first input terminal is electrically connected to the first source region of the first transistor. A second input terminal is electrically connected to the second source region of the second transistor, wherein the first input terminal and the second input terminal are spaced apart from each other. A polarization state terminal is electrically connected to the first gate structure of the first transistor and the second gate structure of the second transistor. A material of the first ferroelectric layer is in contact with a top surface of the substrate.

[0243] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A first transistor above a substrate, comprising: A first semiconductor channel layer; A first gate structure surrounding the first semiconductor channel layer and including a first ferroelectric layer; and The first semiconductor channel layer has a first source region and a first drain region on multiple opposite sides; A second transistor above the substrate includes: A second semiconductor channel layer, wherein in a cross-sectional view, the second semiconductor channel layer is shorter than the first semiconductor channel layer; A second gate structure surrounding the second semiconductor channel layer and including a second ferroelectric layer; and A second source region and a second drain region on multiple opposite sides of the second semiconductor channel layer; An output terminal is electrically connected to the first drain region of the first transistor and the second drain region of the second transistor; and A material of the first ferroelectric layer is in contact with a top surface of the substrate.

2. The semiconductor device as claimed in claim 1, characterized in that, The second transistor is positioned vertically above the first transistor, and the first transistor and the second transistor are an n-type transistor and a p-type transistor, respectively.

3. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A first input terminal, which is electrically connected to the first source region of the first transistor; and A second input terminal is electrically connected to the second source region of the second transistor, wherein the first input terminal and the second input terminal are spaced apart from each other.

4. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A polarization state terminal is electrically connected to the first gate structure of the first transistor and the second gate structure of the second transistor.

5. The semiconductor device as claimed in claim 1, characterized in that, The substrate includes a semiconductor layer and an insulating layer, wherein the material of the first ferroelectric layer is in contact with the insulating layer of the substrate.

6. A semiconductor device, characterized in that, Include: A first transistor above a substrate, comprising: A first semiconductor channel layer; A first gate structure surrounding the first semiconductor channel layer and including a first ferroelectric layer; and The first semiconductor channel layer has a first source region and a first drain region on multiple opposite sides; A second transistor above the substrate includes: A second semiconductor channel layer, wherein in a cross-sectional view, the second semiconductor channel layer is shorter than the first semiconductor channel layer; A second gate structure surrounding the second semiconductor channel layer and including a second ferroelectric layer; and A second source region and a second drain region on multiple opposite sides of the second semiconductor channel layer; An output terminal is electrically connected to the first drain region of the first transistor and the second drain region of the second transistor; and A material of the first ferroelectric layer is in contact with a top surface of the substrate, wherein the substrate includes a semiconductor layer and an insulating layer, and the material of the first ferroelectric layer is in contact with the insulating layer of the substrate.

7. The semiconductor device as claimed in claim 6, characterized in that, The second transistor is positioned vertically above the first transistor, and the first transistor and the second transistor are an n-type transistor and a p-type transistor, respectively.

8. The semiconductor device as claimed in claim 6, characterized in that, Further includes: A first input terminal, which is electrically connected to the first source region of the first transistor; and A second input terminal is electrically connected to the second source region of the second transistor, wherein the first input terminal and the second input terminal are spaced apart from each other.

9. The semiconductor device as claimed in claim 6, characterized in that, Further includes: A polarization state terminal is electrically connected to the first gate structure of the first transistor and the second gate structure of the second transistor.

10. A semiconductor device, characterized in that, Include: A first transistor above a substrate, comprising: A first semiconductor channel layer; A first gate structure surrounding the first semiconductor channel layer and including a first ferroelectric layer; and The first semiconductor channel layer has a first source region and a first drain region on multiple opposite sides; A second transistor above the substrate includes: A second semiconductor channel layer, wherein in a cross-sectional view, the second semiconductor channel layer is shorter than the first semiconductor channel layer; A second gate structure surrounding the second semiconductor channel layer and including a second ferroelectric layer; and A second source region and a second drain region on multiple opposite sides of the second semiconductor channel layer; An output terminal is electrically connected to the first drain region of the first transistor and the second drain region of the second transistor. A first input terminal is electrically connected to the first source region of the first transistor; A second input terminal is electrically connected to the second source region of the second transistor, wherein the first input terminal and the second input terminal are spaced apart from each other; A polarization state terminal is electrically connected to the first gate structure of the first transistor and the second gate structure of the second transistor. as well as A material of the first ferroelectric layer is in contact with a top surface of the substrate.

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