Heterogeneous data collecting and recording device

Abstract

The utility model discloses a heterogeneous data acquisition and recording device, and relates to the technical field of data acquisition and storage, and the device comprises an input interface which is used for accessing a DI signal, an AD signal and an SPI signal; the main control circuit comprises a main control chip, and the main control circuit is connected with the input interface; the single chip microcomputer is connected with the main control circuit; the storage circuit is connected with the single-chip microcomputer and used for storing DI data, AD data and SPI data output by the single-chip microcomputer; the downloading interface is connected with the single chip microcomputer and used for being connected with an upper computer; and the power supply circuit is connected with the input interface and the downloading interface, and the power supply circuit is used for supplying power to the main control circuit and the single chip microcomputer. According to the application, a heterogeneous mode of combining the main control chip and the single-chip microcomputer is adopted, the high expansion performance of the ZYNQ processor and the low cost of the STM series single-chip microcomputer are effectively combined, and the cost is reduced on the premise of ensuring that the performance meets the requirements.

Description

Technical Field

[0001] This application relates to the field of data acquisition and storage technology, and in particular to a heterogeneous data acquisition and recording device. Background Technology

[0002] Various types of mechanical equipment, such as civilian or military equipment, generate a variety of data during operation. These data can reflect the working status of the equipment, so collecting and storing this data helps to monitor and analyze the equipment status.

[0003] Because there are many types of devices that need to be monitored, the data types are also diverse. To meet the diverse data acquisition and storage requirements, the data acquisition and recording device needs to have strong scalability to be compatible with different data types. Currently, many designs use processors based on the ZYNQ architecture to address this need. This type of processor integrates FPGA and ARM processors and has strong scalability. However, the scalability of a single ZYNQ processor is relatively limited. When input data occupies most of the interfaces, the remaining interfaces are often insufficient to support storage and retrieval. Therefore, when there are many scalability requirements, it is unavoidable to use multiple ZYNQ processors. However, ZYNQ processors are relatively expensive, and using multiple ZYNQ processors leads to a higher overall cost for the data acquisition and recording device. Utility Model Content

[0004] This application provides a heterogeneous data acquisition and recording device to solve the problem of high cost caused by using multiple ZYNQ processors in the prior art.

[0005] This application provides a heterogeneous data acquisition and recording device, including:

[0006] Input interface for receiving DI, AD, and SPI signals;

[0007] The main control circuit includes a main control chip of model XC7Z020-2CLG484I, and the main control circuit is connected to the input interface.

[0008] The microcontroller uses an STM32F427IIH6 chip and is connected to the main control circuit.

[0009] The storage circuit is connected to the microcontroller and is used to store the DI data, AD data and SPI data output by the microcontroller.

[0010] The download interface connects to the microcontroller and is also used to connect to the host computer.

[0011] The power supply circuit, connected to the input interface and download interface, is used to supply power to the main control circuit, microcontroller, and storage circuit.

[0012] In one possible implementation, the input interface uses a 24-pin connector, which can simultaneously receive 2 DI signals, 7 AD signals, and 2 SPI signals.

[0013] In one possible implementation, the input terminal of the main control chip is connected to a DI conditioning circuit, an AD acquisition circuit, and an SPI filtering circuit. The DI conditioning circuit, AD acquisition circuit, and SPI filtering circuit are used to receive DI signals, AD signals, and SPI signals, respectively.

[0014] In one possible implementation, a signal conditioning circuit is connected between the input interface and the DI conditioning circuit. The signal conditioning circuit is used to isolate the 8-15V input power supply from the input interface through an optocoupler and the DI conditioning circuit.

[0015] In one possible implementation, the storage circuit uses an eMMC storage chip with the model number SDINBDG4-8G-XA.

[0016] In one possible implementation, a converter circuit connects the download interface and the microcontroller.

[0017] In one possible implementation, the adapter circuit uses an expansion chip of model USB3300-EZK to implement the high-speed USB function of the microcontroller.

[0018] In one possible implementation, the power supply circuit includes a power switching circuit. The input terminal of the power switching circuit is connected to the input interface and the download interface, respectively. The power switching circuit includes a first power conversion chip of model MT2492 and a power switching chip of model TPS2115APWR. The first power conversion chip is connected between the input interface and the first input terminal of the power switching chip. The second input terminal of the power switching chip is connected to the download interface. The first power conversion chip is used to convert the 8-15V input power from the input interface into a 5V power supply. The power switching chip is used to switch between the 5V power supply input from the first power conversion chip and the 5V power supply input from the download interface.

[0019] In one possible implementation, the power supply circuit further includes a power conversion circuit, which includes three second power conversion chips of model TPS82085SIL. The input terminals of the second power conversion chips are connected to the output terminals of the power switching chip. The three second power conversion chips output power of 3.3V, 1.8V and 1.2V respectively to supply the main control chip, microcontroller and storage circuit.

[0020] The heterogeneous data acquisition and recording device of this application has the following advantages:

[0021] The system adopts a heterogeneous approach that combines a main control chip and a microcontroller. The main control chip uses a ZYNQ processor, while the microcontroller uses the STM series. This effectively combines the high scalability of the ZYNQ processor with the low cost of the STM series microcontroller, reducing costs while ensuring that performance meets requirements. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic block diagram of a heterogeneous data acquisition and recording device provided in an embodiment of this application.

[0024] Figure 2 This is a schematic diagram of a signal conditioning circuit provided in an embodiment of this application.

[0025] Figure 3 This is a schematic diagram of the DI conditioning circuit provided in an embodiment of this application.

[0026] Figure 4 This is a schematic diagram of the AD acquisition circuit provided in an embodiment of this application.

[0027] Figure 5 This is a schematic diagram of the SPI filter circuit provided in an embodiment of this application.

[0028] Figure 6 A schematic diagram of a storage circuit provided in an embodiment of this application.

[0029] Figure 7 This is a schematic diagram of the adapter circuit provided in an embodiment of this application.

[0030] Figure 8 This is a topology diagram of the power supply circuit provided in an embodiment of this application.

[0031] Figure 9 This is a schematic diagram of a power switching circuit provided in an embodiment of this application.

[0032] Figure 10 This is a schematic diagram of a power conversion circuit provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] Figure 1-10 A circuit diagram of a heterogeneous data acquisition and recording device provided in an embodiment of this application. This application provides a heterogeneous data acquisition and recording device, including:

[0035] Input interface for receiving DI, AD, and SPI signals;

[0036] The main control circuit includes a main control chip of model XC7Z020-2CLG484I, and the main control circuit is connected to the input interface.

[0037] The microcontroller uses an STM32F427IIH6 chip and is connected to the main control circuit.

[0038] The storage circuit is connected to the microcontroller and is used to store the DI data, AD data and SPI data output by the microcontroller.

[0039] The download interface connects to the microcontroller and is also used to connect to the host computer.

[0040] The power supply circuit, connected to the input interface and download interface, is used to supply power to the main control circuit, microcontroller, and storage circuit.

[0041] For example, this application embodiment uses a mature and stable ZYNQ processor paired with an STM32 series microcontroller to form a heterogeneous architecture to realize data acquisition, storage, and download functions.

[0042] The data acquisition and recording device of this application has two working modes: recording mode and downloading mode.

[0043] Recording mode: The main control chip acquires 8-15V input power, DI signal, AD signal, and SPI signal, frames the acquired signal data, and stores it in a buffer. Then, the microcontroller reads the data from the main control chip's buffer via the FMC bus and stores the read data in the eMMC onboard memory.

[0044] Download Mode: When the microcontroller receives instructions from the host computer, it can perform tasks such as data query, data upload, and data erasure. Data query allows the microcontroller to retrieve information such as the quantity and capacity of data stored in the acquisition and recording device; data upload allows the microcontroller to upload data stored in the acquisition and recording device to the host computer according to the instructions; data erasure clears the memory of the acquisition and recording device.

[0045] Mode Switching: After the microcontroller is powered on, it first checks whether the host computer is connected via the download interface. When the download interface is not connected to the host computer, the data acquisition and recording device operates in recording mode to acquire and record real-time data from each interface. When the download interface is connected to the host computer, the data acquisition and recording device enters download mode, receives instructions from the host computer, and performs data query, download, and erase operations.

[0046] Specifically, the download interface can be a USB interface.

[0047] The microcontroller used in this embodiment employs a Cortex-M4 32-bit RISC core with a main frequency of up to 168MHz. It contains 1Mb of Flash and 512Kb of SRAM, and features SPI and SDIO interfaces for data storage. It also has an FMC bus for high-speed data exchange with the main control chip and a USB interface for uploading data to a host computer. The rich physical interfaces meet the design and development requirements of this type of product.

[0048] The main performance specifications of this series of processors are as follows:

[0049] A Cortex-M4 core (with floating-point unit) operating at a frequency of 180MHz;

[0050] Two USB OTG ports (one of which supports HS);

[0051] Dedicated audio PLL and 2 full-duplex I / O pins 2 S-bus;

[0052] It has up to 15 communication interfaces (including 4 USARTs with speeds up to 11.25Mb / s, 2 SPIs with speeds up to 45Mb / s, and 3 I / O interfaces). 2 C, 2 CAN and 1 SDIO);

[0053] Two 12-bit DACs and three 12-bit ADCs with speeds of 2.4 MSPS or 7.2 MSPS (interleaved mode);

[0054] Up to 14 16-bit and 32-bit timers with frequencies up to 180MHz;

[0055] Storage capacity can be easily expanded using a flexible static memory controller that supports Compact Flash, SRAM, PSRAM, NOR, and NAND memories.

[0056] The main control chip used in this application primarily utilizes the following ARM resources: LGIC CELLS / SLICES / Distributes RAM / BLOCK RAM BLOCKS / USER IO. It mainly performs the following tasks:

[0057] Acquire 8-15V input power;

[0058] Acquire digital pulses and synthesize D flip-flops;

[0059] Integrated AD controller to receive analog signals;

[0060] The integrated UART controller receives serial port data.

[0061] Acquire SPI data;

[0062] Add hardware time stamp;

[0063] Frame data according to a fixed data frame format;

[0064] It receives instructions from the microcontroller to collect and upload data.

[0065] In the embodiments of this application, the input interface adopts a 24-pin connector, which can simultaneously receive 2 DI signals, 7 AD signals and 2 SPI signals.

[0066] In one possible embodiment, the input terminal of the main control chip is connected to a DI conditioning circuit, an AD acquisition circuit, and an SPI filtering circuit. The DI conditioning circuit, AD acquisition circuit, and SPI filtering circuit are used to receive DI signals, AD signals, and SPI signals, respectively.

[0067] For example, a signal conditioning circuit is connected between the input interface and the DI conditioning circuit. The signal conditioning circuit is used to isolate the 8-15V input power supply from the input interface through the optocoupler and the DI conditioning circuit.

[0068] Because the input power supply with a voltage of 8-15V has a high voltage amplitude, it cannot be directly connected to the digital system of the data acquisition and recording device. Therefore, it is necessary to reduce the impact of this input power supply on the digital system. Thus, in this embodiment, a TLP293 optocoupler is used for electrical isolation before being connected to the DI conditioning circuit for DI signal acquisition.

[0069] With an 8-15V input power supply effective time of less than 40ms, a 50M optocoupler and a 74LVC1G125DCKR DI conditioning chip are selected for signal conditioning, which can meet the characteristic requirements of the DI signal. Figure 2 and Figure 3 In this context, the optocoupler is represented by U1, while the DI conditioning chip is represented by U2.

[0070] The DI signal input from the input interface is level-converted by the DI conditioning chip and then provided to the main control chip for data acquisition.

[0071] The AD chip used in the AD acquisition circuit is the AD7606 from Analog Devices. Seven AD signal inputs are fed into the AD7606, supporting high-speed acquisition of multiple analog signals in a synchronous acquisition mode. Figure 4 In this context, AD7606 is represented by U3.

[0072] The main technical specifications of AD7606 are as follows:

[0073] 8 / 6 / 4-channel synchronous sampling input;

[0074] True bipolar analog input range: ±10V, ±5V;

[0075] A single 5V analog power supply and a 2.3V to 5V VDRIVE power supply;

[0076] A fully integrated data acquisition solution;

[0077] Flexible parallel / serial interface;

[0078] The ESD rating on the analog input channel is 7kV;

[0079] Temperature range: -40℃ to +85℃.

[0080] In this embodiment, the acquisition and recording device needs to acquire 6 channels of analog signals ranging from -10V to +10V, with an acquisition frequency of 40kHz and a resolution of 16bit. Compared to the technical specifications and requirements of the AD7606, the functional performance requirements of the acquisition and recording device in this embodiment are met.

[0081] The SPI filtering circuit uses a 74LVC1G125DCKR chip for conversion to reduce interference from signal transmission to the SPI signal. Figure 5 In this context, the chip is referred to as U4, U5, and U6.

[0082] In the embodiments of this application, the storage circuit uses an eMMC storage chip with model number SDINBDG4-8G-XA. Figure 6 In this context, the memory chip is represented by U7.

[0083] For example, an eMMC memory chip encapsulates the interface, flash memory device, and main controller within a single BGA chip, offering fast and scalable performance. Specifically, it provides the following advantages:

[0084] Simplified design. Integrated interface, memory, and controller; simple and unified interface protocol (using version 5.1 driver).

[0085] Fast update speed. The sequential read rate is 170MB / s, and the sequential write rate is 300MB / s.

[0086] When the eMMC storage chip operates in either of the two working modes of the data acquisition and recording device, it performs data writing and reading respectively. In recording mode, the microcontroller writes the data acquired by the main control chip into the eMMC storage chip; in download mode, the microcontroller reads the data stored in the eMMC storage chip and sends it to the host computer through the download interface.

[0087] In one possible embodiment, a converter circuit is connected between the download interface and the microcontroller.

[0088] For example, the adapter circuit uses an expansion chip of model USB3300-EZK, and the adapter circuit is used to implement the high-speed USB function of the microcontroller. Figure 7 In this context, the expansion chip is represented by U8.

[0089] Since the microcontroller only has an FS USB PHY (full-speed USB) interface, to implement the HS USB (high-speed USB) function, an external HS USB PHY interface needs to be connected through the ULPI interface. This interface is implemented by the adapter circuit in the embodiment of this application, which realizes the USB 2.0 transmission of the download interface.

[0090] In one possible embodiment, the power supply circuit includes a power switching circuit. The input terminal of the power switching circuit is connected to the input interface and the download interface, respectively. The power switching circuit includes a first power conversion chip of model MT2492 and a power switching chip of model TPS2115APWR. The first power conversion chip is connected between the input interface and the first input terminal of the power switching chip. The second input terminal of the power switching chip is connected to the download interface. The first power conversion chip is used to convert the 8-15V input power from the input interface into 5V power. The power switching chip is used to switch between the 5V power input from the first power conversion chip and the 5V power input from the download interface.

[0091] For example, the power supply circuit also includes a power conversion circuit, which includes three TPS82085SIL second power conversion chips. The input terminals of the second power conversion chips are connected to the output terminals of the power switching chip. The three second power conversion chips output 3.3V, 1.8V, and 1.2V power supplies respectively to the main control chip, microcontroller, and storage circuit. Figure 9-10 In this context, the first power conversion chip and the power switching chip are represented by U9 and U10, respectively.

[0092] The power supply voltage range provided by the input interface of the data acquisition and recording device in this application embodiment is DC 8-15V, and the operating current is less than 150mA. Based on actual functional performance requirements, the power supply circuit internally requires 5V, 3.3V, 2.5V, 1.8V, and 1.2V power supplies.

[0093] The MT2492 chip features a wide input voltage range of 4.5V to 18V. It is a fully integrated, high-efficiency product that can provide up to 2A of output current. As a current-mode buck DC / DC converter, it offers excellent transient response and requires no external compensation.

[0094] The data acquisition and recording device in this application requires a dual-power supply design. When powered by DC 8-15V from the input interface, the device enters recording mode; while when powered by 5V from the download interface, the device operates in download mode. Therefore, a power switching function for the 5V power supply is required, which is implemented by a power conversion chip.

[0095] The TPS2115APWR features manual and automatic switching and status output functions, and can output 2.8V to 5.5V, 84mΩ, 1.25A power.

[0096] Furthermore, the power supply circuit also requires 3.3V, 1.8V and 1.2V power supplies, which are obtained from the switched 5V power supply through three secondary power conversion chips.

[0097] The TPS82085SIL is an optimized 2A / 3A buck converter MicroSiP module that combines a small solution size with high efficiency. This power module integrates a synchronous buck converter and inductor, simplifying design, reducing external components, and saving printed circuit board (PCB) space. The device is housed in a compact, thin package, suitable for automated assembly using standard surface mount equipment.

[0098] To maximize efficiency, this second power converter operates in pulse-width modulation (PWM) mode at a nominal switching frequency of 2.4MHz and automatically enters a power-saving mode under light load current. In power-saving mode, the device's typical quiescent current is 17μA. With its DCS-Control topology, the device achieves excellent load transient performance and precise output regulation. The device's EN and PG pins support sequential configuration, allowing for flexible system design. Integrated soft-start functionality reduces the inrush current required by the input power supply. Over-temperature protection and automatic short-circuit protection make this solution robust and reliable.

[0099] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0100] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A heterogeneous data acquisition and recording device, characterized in that, include: Input interface for receiving DI, AD, and SPI signals; The main control circuit includes a main control chip of model XC7Z020-2CLG484I, and the main control circuit is connected to the input interface. The microcontroller is an STM32F427IIH6 chip, and the microcontroller is connected to the main control circuit. A storage circuit is connected to the microcontroller, and the storage circuit is used to store the DI data, AD data and SPI data output by the microcontroller; A download interface is provided, which is connected to the microcontroller and is used to connect to a host computer. A power supply circuit is connected to the input interface and the download interface, and the power supply circuit is used to supply power to the main control circuit, the microcontroller and the storage circuit.

2. The heterogeneous data acquisition and recording device according to claim 1, characterized in that, The input interface uses a 24-pin connector, which can simultaneously receive 2 DI signals, 7 AD signals, and 2 SPI signals.

3. The heterogeneous data acquisition and recording device according to claim 1, characterized in that, The input terminal of the main control chip is connected to a DI conditioning circuit, an AD acquisition circuit, and an SPI filtering circuit. The DI conditioning circuit, the AD acquisition circuit, and the SPI filtering circuit are respectively used to receive the DI signal, the AD signal, and the SPI signal.

4. The heterogeneous data acquisition and recording device according to claim 3, characterized in that, A signal conditioning circuit is connected between the input interface and the DI conditioning circuit. The signal conditioning circuit is used to isolate the 8-15V input power supply from the input interface from the DI conditioning circuit through an optocoupler.

5. A heterogeneous data acquisition and recording device according to claim 1, characterized in that, The storage circuit uses an eMMC storage chip with model number SDINBDG4-8G-XA.

6. The heterogeneous data acquisition and recording device according to claim 1, characterized in that, A converter circuit connects the download interface and the microcontroller.

7. A heterogeneous data acquisition and recording device according to claim 6, characterized in that, The adapter circuit uses an expansion chip of model USB3300-EZK, and the adapter circuit is used to realize the high-speed USB function of the microcontroller.

8. The heterogeneous data acquisition and recording device according to claim 1, characterized in that, The power supply circuit includes a power switching circuit. The input terminal of the power switching circuit is connected to the input interface and the download interface, respectively. The power switching circuit includes a first power conversion chip of model MT2492 and a power switching chip of model TPS2115APWR. The first power conversion chip is connected between the input interface and the first input terminal of the power switching chip. The second input terminal of the power switching chip is connected to the download interface. The first power conversion chip is used to convert the 8-15V input power from the input interface to 5V power. The power switching chip is used to switch between the 5V power input from the first power conversion chip and the 5V power input from the download interface.

9. A heterogeneous data acquisition and recording device according to claim 8, characterized in that, The power supply circuit also includes a power conversion circuit, which includes three second power conversion chips of model TPS82085SIL. The input terminal of the second power conversion chip is connected to the output terminal of the power switching chip. The three second power conversion chips output 3.3V, 1.8V and 1.2V power respectively to supply the main control chip, the microcontroller and the storage circuit.

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