Wireless communication module and wireless communication system
By adding SGMII interface compatibility outside the M.2 interface specification, the problem that the PCIe interface cannot meet the requirements of SGMII applications is solved, thereby improving the compatibility and competitiveness of wireless communication modules.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- FIBOCOM WIRELESS
- Filing Date
- 2025-04-21
- Publication Date
- 2026-05-08
AI Technical Summary
The existing M.2 interface specification only defines the PCIe interface, which cannot meet the application requirements of the SGMII interface.
A wireless communication module was designed, comprising a baseband chip, an M.2 connector, and a power management unit. The module enables switching between PCIe and SGMII signals through an interface type selection pin and a selection circuit, thereby increasing compatibility with the SGMII interface.
Without increasing the area and complexity of the printed circuit board, the compatibility and product competitiveness of the wireless communication module are improved, while the R&D and certification costs are reduced.
Smart Images
Figure CN224218390U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a wireless communication module and a wireless communication system. Background Technology
[0002] Wireless communication modules are now widely used in the Internet of Things (IoT) industry, including power grids and vehicle-to-everything (V2X) networks. Wireless communication modules using the M.2 interface are more widely used in the mobile broadband (MBB) market, such as personal computers (PCs) and customer premises equipment (CPEs), due to their relatively standardized pin definitions and structural dimensions, and their detachable design. For example, CPE applications convert cellular signals into Wi-Fi or Ethernet signals. Currently, the popular Ethernet chip types involve interface signals from the Peripheral Component Interconnect Express (PCIe) standard and the Serial Gigabit Media Independent Interface (SGMII). According to the PCI Express M.2 Specification, the M.2 interface only defines two high-speed interfaces: Universal Serial Bus (USB) and PCIe, therefore it cannot meet the needs of applications using the SGMII interface. Utility Model Content
[0003] This application provides a wireless communication module and a wireless communication system to address how to add compatibility with the SGMII interface in addition to the PCIe interface defined in the original M.2 specification.
[0004] In a first aspect, this application provides a wireless communication module, which includes at least a baseband chip, an M.2 connector, and a power management unit;
[0005] The baseband chip includes a multiplexing function module and an interface type selection pin; wherein, the multiplexing function module is used to transmit high-speed serial computer expansion bus standard PCIe signals or serial gigabit media independent interface SGMII signals according to the level state input by the interface type selection pin.
[0006] The M.2 connector includes an M.2 interface and a selection circuit; the M.2 interface is connected to the multiplexing function module, one end of the selection circuit is connected to the interface type selection pin, and outputs a high level or a low level to the interface type selection pin according to the connection state of the other end of the selection circuit;
[0007] The power management unit is connected to the communication interface power supply terminal of the baseband chip and is used to supply power to the communication interface and the communication interface core; wherein, the communication interface includes a PCIe interface and an SGMII interface.
[0008] Optionally, the selection circuit includes a first resistor and a second resistor;
[0009] The first end of the first resistor is connected to the first power supply; the second end of the first resistor is connected to the interface type selection pin and the first end of the M.2 connector.
[0010] The second end of the M.2 connector is used to connect to the first end of the second resistor, and the second end of the second resistor is grounded; wherein, when the connection state of the second end of the M.2 connector is not connected to the first end of the second resistor, the interface type selection pin is input with a high level; when the connection state of the second end of the M.2 connector is connected to the first end of the second resistor, the interface type selection pin is input with a low level.
[0011] Optionally, the power management unit includes a first output port and a second output port; the first output port is connected to the first core input terminal of the baseband chip, and the second output port is connected to the second core input terminal of the baseband chip; wherein the output voltages of the first output port and the second output port are different; the first core input terminal is connected to the PCIe core and the SGMII core, and the second core input terminal is connected to the PCIe core and the SGMII core.
[0012] Optionally, the baseband chip further includes a switching switch;
[0013] The switching switch is connected to the interface type selection pin; when the interface type selection pin is high, the multiplexing function module transmits PCIe signals under the action of the switching switch; when the interface type selection pin is low, the multiplexing function module transmits SGMII signals under the action of the switching switch.
[0014] Optionally, the multiplexing function module includes nine multiplexed pins.
[0015] Optionally, when the interface type selection pin input is high, the first multiplexed pin is connected to the negative terminal of the PCIe data transmission differential signal pair;
[0016] The second multiplexed pin is connected to the positive terminal of the PCIe data transmission differential signal pair;
[0017] The third multiplexed pin is connected to the negative terminal of the PCIe data receive differential signal pair;
[0018] The fourth multiplexed pin is connected to the positive terminal of the PCIe data receive differential signal pair;
[0019] The fifth multiplexed pin is connected to the PCIe interface reset signal;
[0020] The sixth multiplexed pin is connected to the PCIe reference clock request signal;
[0021] The seventh multiplexed pin is connected to the negative terminal of the PCIe reference clock differential signal;
[0022] The eighth multiplexed pin is connected to the PCIe system wake-up signal;
[0023] The ninth multiplexed pin is connected to the positive terminal of the PCIe reference clock differential signal.
[0024] Optionally, when the interface type selection pin input is low, the first multiplexed pin is connected to the negative terminal of the SGMII transmit data differential signal pair;
[0025] The second multiplexed pin is connected to the positive terminal of the SGMII transmit data differential signal pair;
[0026] The third multiplexing pin is connected to the negative terminal of the SGMII receive data differential signal pair;
[0027] The fourth multiplexed pin is connected to the positive terminal of the SGMII receive data differential signal pair;
[0028] The fifth multiplexed pin is connected to the SGMII reset signal;
[0029] The seventh multiplexed pin is connected to the SGMII management data clock signal;
[0030] The eighth multiplexed pin is connected to the SGMII interrupt signal;
[0031] The ninth multiplexed pin is connected to the SGMII management data input / output signals.
[0032] Optionally, the wireless communication module further includes: a radio frequency chip, an antenna, and a storage unit.
[0033] Secondly, this application provides a wireless communication system, which includes the wireless communication module described in any one of the first aspects.
[0034] Compared with the prior art, the technical solution provided in this application has the following advantages: The wireless communication module provided in this application includes at least a baseband chip, an M.2 connector, and a power management unit; the baseband chip includes a multiplexing function module and an interface type selection pin; wherein, the multiplexing function module is used to transmit high-speed serial computer extended bus standard PCIe signals or serial gigabit media independent interface SGMII signals according to the level state input by the interface type selection pin; the M.2 connector includes an M.2 interface and a selection circuit; the M.2 interface is connected to the multiplexing function module, one end of the selection circuit is connected to the interface type selection pin, and outputs a high level or a low level to the interface type selection pin according to the connection state of the other end of the selection circuit; the power management unit is connected to the communication interface power supply terminal of the baseband chip and is used to power the communication interface and the communication interface core; wherein, the communication interface includes a PCIe interface and an SGMII interface. This wireless communication module can output a high or low level to the interface type selection pin by selecting the connection state of the circuit. This allows the baseband chip's multiplexing function module to transmit PCIe or SGMII signals according to different level states. This enables the wireless communication module to support SGMII interfaces in addition to the PCIe interfaces defined by the original specifications, thereby improving the compatibility and competitiveness of the wireless communication module. Attached Figure Description
[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0038] Figure 1 This is a schematic diagram of the structure of a wireless communication module provided in one embodiment of this application;
[0039] Figure 2 This is a structural block diagram of a wireless communication module provided in one embodiment of this application. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0041] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.
[0042] To address the technical challenge of adding compatibility with the SGMII interface beyond the existing PCIe interface defined in the M.2 specification, this application provides a wireless communication module and a wireless communication system. This enables the wireless communication module to support the SGMII interface in addition to the existing PCIe interface, thereby enhancing the compatibility and competitiveness of the wireless communication module.
[0043] The first embodiment of this application provides a wireless communication module, such as... Figure 1 The wireless communication module includes at least a baseband chip 101, an M.2 connector 102, and a power management unit 103.
[0044] The baseband chip includes a multiplexing function module (PCIe / SGMII AUX) and an interface type selection pin (PCIe_EN# / SGMII_EN). The multiplexing function module is used to transmit high-speed serial computer expansion bus standard PCIe signals or serial gigabit media independent interface SGMII signals according to the level state of the interface type selection pin input. For example, when the interface type selection pin input is high, it transmits PCIe signals, and when the interface type selection pin input is low, it transmits SGMII signals.
[0045] The M.2 connector consists of an M.2 interface and a selection circuit. The M.2 interface connects to a multiplexing function module, and one end of the selection circuit is connected to the interface type selection pin. The connection status of the other end of the selection circuit outputs a high or low level to the interface type selection pin.
[0046] The Power Management Unit (PMU) is connected to the power supply terminal of the baseband chip's communication interface and is used to power the communication interface and the communication interface core; the communication interface includes a PCIe interface and an SGMII interface.
[0047] This wireless communication module can output a high or low level to the interface type selection pin by selecting the connection state of the circuit. This allows the baseband chip's multiplexing function module to transmit PCIe or SGMII signals according to different level states. This enables the wireless communication module to support SGMII interfaces in addition to the PCIe interfaces defined by the original specifications, thereby improving the compatibility and competitiveness of the wireless communication module.
[0048] In one embodiment, the structural block diagram of the wireless communication module is as follows: Figure 2 The selection circuit includes a first resistor R1 and a second resistor R2.
[0049] The first terminal of the first resistor is connected to the first power supply VCC, and the second terminal of the first resistor is connected to the interface type selection pin (PCIe_EN# / SGMII_EN) and the first terminal of the M.2 connector. The second terminal of the M.2 connector is used to connect to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is grounded (GND). When the second terminal of the M.2 connector is not connected to the first terminal of the second resistor, the interface type selection pin is high; when the second terminal of the M.2 connector is connected to the first terminal of the second resistor, the interface type selection pin is low.
[0050] In this embodiment, when the second resistor R2 is not connected, the interface type selection pin is high, allowing the multiplexed function module (PCIe / SGMII AUX) to transmit PCIe signals. The wireless communication module can then transmit PCIe signals via the M.2 connector. When the second resistor R2 is connected, the interface type selection pin is pulled down by R2, resulting in a low-level input. The wireless communication module can then transmit SGMII signals via the M.2 connector. This allows the wireless communication module to support SGMII interfaces in addition to the existing PCIe interfaces, improving its compatibility and product competitiveness. Furthermore, this solution does not increase the PCB area, the complexity of components and PCB traces, or affect the PCB's electromagnetic compatibility (EMC) performance, thus standardizing the PCB for module products and significantly reducing R&D investment and product certification costs.
[0051] In one embodiment, the power management unit includes a first output port Vout1 and a second output port Vout2. The first output port is connected to the first core input terminal PCIe / SGMII_1P2 of the baseband chip, and the second output port is connected to the second core input terminal PCIe / SGMII_0P9 of the baseband chip; wherein the output voltages of the first output port and the second output port are different; the first core input terminal is connected to the PCIe core and the SGMII core, and the second core input terminal is connected to the PCIe core and the SGMII core.
[0052] In this embodiment, the PMU includes two power supplies for the CPU's internal PCIe / SGMII cores. VOUT1 outputs 0.9V, and VOUT2 outputs 1.2V, supplying power to both the PCIe and SGMII cores. The default power supply can be configured to power the PCIe core. The PCIe_EN# / SGMII_EN pins control the enable. When this pin is high, VOUT1 and VOUT2 output voltages power the PCIe core; when this pin is low, VOUT1 and VOUT2 output voltages power the SGMII core. The interface type selection pins PCIe_EN# / SGMII_EN have two functions: first, controlling the multiplexing of the PCIe / SGMII interface within the baseband chip; and second, controlling the multiplexing of the power supplies for VOUT1 and VOUT2 within the PMU. This interface type selection pin can default to high, configured as a PCIe interface and power supply to the PCIe core; when pulled low by an external resistor R2, it is configured as an SGMII interface and power supply to the SGMII core. By utilizing the multiplexing design of the internal multiplexing function modules (PCIe / SGMII AUX) of the baseband chip, PCIe and SGMII compatibility on the M.2 wireless communication module can be achieved without adding extra wiring or power consumption. When an SGMII interface application is required, switching to the SGMII interface can be achieved simply by connecting a pull-down resistor R2, without any other circuit changes. When switching back to the PCIe interface application is required, only the connection of port R2 is needed to switch back to the PCIe interface. The operation is simple and requires no additional hardware cost.
[0053] In one specific embodiment, the baseband chip further includes a switching switch. The switching switch is connected to the interface type selection pin; when the interface type selection pin is high, the multiplexing function module transmits PCIe signals under the action of the switching switch; when the interface type selection pin is low, the multiplexing function module transmits SGMII signals under the action of the switching switch.
[0054] In this embodiment, when switching between PCIe and SGMII signals, a switching switch can be set inside the baseband chip. When the interface type selection pin is high, the multiplexing function module transmits the PCIe signal under the action of the switching switch. When the interface type selection pin is low, the multiplexing function module transmits the SGMII signal under the action of the switching switch.
[0055] In one specific embodiment, taking the M.2 wireless communication module with Socket2 Key-B interface as an example, some of the PCIe interface signals of the M.2 module are shown in Table 1 below.
[0056] Table 1
[0057]
[0058] The SGMII interface signals are shown in Table 2 below.
[0059] Table 2
[0060] pin name Pin Description SGMII_TX_N Negative end of SGMII data TX (SGMII is the negative end of the transmit data differential signal pair) SGMII_TX_P Positive end of SGMII data TX (SGMII is the positive terminal of the transmit data differential signal pair) SGMII_RX_N Negative end of SGMII data RXSGMII (the negative end of the received data differential signal pair) SGMII_RX_P Positive end of SGMII data RX (SGMII is the positive terminal of the received data differential signal pair) GBE_RST SGMII reset signal GBE_INT SGMII interrupt signal MDC SGMII MDC signal Management Data Clock MDIO SGMII MDIO signal management data input / output signals
[0061] Since both PCIe and SGMII interfaces are full-duplex communications, both have two differential pairs (TX and RX), and their PCB routing rules and impedance control are consistent, the pins mentioned in Tables 1 and 2 can be designed for PCB compatibility. For example, nine multiplexed pins can be set in the multiplexing function module. These multiplexed pins serve as different pins for PCIe and SGMII signals under different conditions, as shown in Table 3.
[0062] Table 3
[0063]
[0064] Specifically, when the interface type selection pin is high, the multiplexing function module (PCIe / SGMIIAUX) transmits PCIe signals to achieve function 1. Specifically, the first multiplexing pin is connected to the negative terminal (PETn0) of the PCIe data transmission differential signal pair, the second multiplexing pin is connected to the positive terminal (PETp0) of the PCIe data transmission differential signal pair, the third multiplexing pin is connected to the negative terminal (PERn0) of the PCIe data reception differential signal pair, the fourth multiplexing pin is connected to the positive terminal (PERp0) of the PCIe data reception differential signal pair, the fifth multiplexing pin is connected to the PCIe interface reset signal (PERST#), the sixth multiplexing pin is connected to the PCIe reference clock request signal (CLKREQ#), the seventh multiplexing pin is connected to the negative terminal (REFCLKN) of the PCIe reference clock differential signal, the eighth multiplexing pin is connected to the PCIe system wake-up signal (PEWAKE#), and the ninth multiplexing pin is connected to the positive terminal (REFCLKP) of the PCIe reference clock differential signal.
[0065] When the interface type selection pin is low, the multiplexing function module (PCIe / SGMII AUX) transmits SGMII signals to implement function 2. Specifically, the first multiplexing pin is connected to the negative terminal (SGMII_TX_N) of the SGMII transmit data differential signal pair, the second multiplexing pin is connected to the positive terminal (SGMII_TX_P) of the SGMII transmit data differential signal pair, the third multiplexing pin is connected to the negative terminal (SGMII_RX_N) of the SGMII receive data differential signal pair, the fourth multiplexing pin is connected to the positive terminal (SGMII_RX_P) of the SGMII receive data differential signal pair, the fifth multiplexing pin is connected to the SGMII reset signal (GBE_RST), the seventh multiplexing pin is connected to the SGMII management data clock signal (MDC), the eighth multiplexing pin is connected to the SGMII interrupt signal (GBE_INT), the ninth multiplexing pin is connected to the SGMII management data input / output signal (MDIO), and the sixth multiplexing pin is left floating (NC).
[0066] This embodiment's design enables M.2 module products to support SGMII interface applications while ensuring compatibility with M.2 specification-defined products. This enhances the compatibility and competitiveness of M.2 products and provides a new design solution for subsequent CPE applications. Furthermore, since the SGMII interface Mac controller is integrated into the CPU, IPA (Internet Protocol Accelerator) acceleration is implemented on the platform side. This saves CPU core and memory computing power on the module side and enables better network communication speeds, thus improving customer satisfaction.
[0067] In one embodiment, the wireless communication module may further include specific components such as radio frequency chips, antennas, and storage units. Since this embodiment does not involve improvements to components such as radio frequency chips, antennas, and storage units, they will not be described further.
[0068] Based on the same technical concept, the second embodiment of this application provides a wireless communication system, which includes the wireless communication module described in any one of the first embodiments.
[0069] The wireless communication system that uses the wireless communication module in the first embodiment adds compatibility with the SGMII interface in addition to supporting the PCIe interface defined by the original specification, thereby improving the compatibility of the wireless communication system.
[0070] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0071] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also mean including the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.
[0072] It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. In the description, suffixes such as "module," "part," or "unit" used to denote elements are used solely for illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.
[0073] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.
Claims
1. A wireless communication module, characterized in that, The wireless communication module includes at least a baseband chip, an M.2 connector, and a power management unit; The baseband chip includes a multiplexing function module and an interface type selection pin; wherein, the multiplexing function module is used to transmit high-speed serial computer expansion bus standard PCIe signals or serial gigabit media independent interface SGMII signals according to the level state input by the interface type selection pin. The M.2 connector includes an M.2 interface and a selection circuit; the M.2 interface is connected to the multiplexing function module, one end of the selection circuit is connected to the interface type selection pin, and outputs a high level or a low level to the interface type selection pin according to the connection state of the other end of the selection circuit; The power management unit is connected to the communication interface power supply terminal of the baseband chip and is used to supply power to the communication interface and the communication interface core; wherein, the communication interface includes a PCIe interface and an SGMII interface.
2. The wireless communication module according to claim 1, characterized in that, The selection circuit includes a first resistor and a second resistor; The first end of the first resistor is connected to the first power supply; the second end of the first resistor is connected to the interface type selection pin and the first end of the M.2 connector. The second end of the M.2 connector is used to connect to the first end of the second resistor, and the second end of the second resistor is grounded; wherein, when the connection state of the second end of the M.2 connector is not connected to the first end of the second resistor, the interface type selection pin is input with a high level; when the connection state of the second end of the M.2 connector is connected to the first end of the second resistor, the interface type selection pin is input with a low level.
3. The wireless communication module according to claim 1, characterized in that, The power management unit includes a first output port and a second output port; the first output port is connected to the first core input terminal of the baseband chip, and the second output port is connected to the second core input terminal of the baseband chip; wherein the output voltages of the first output port and the second output port are different; the first core input terminal is connected to the PCIe core and the SGMII core, and the second core input terminal is connected to the PCIe core and the SGMII core.
4. The wireless communication module according to claim 1, characterized in that, The baseband chip also includes a switching switch; The switching switch is connected to the interface type selection pin; when the interface type selection pin is high, the multiplexing function module transmits PCIe signals under the action of the switching switch; when the interface type selection pin is low, the multiplexing function module transmits SGMII signals under the action of the switching switch.
5. The wireless communication module according to claim 1, characterized in that, The multiplexing function module includes nine multiplexing pins.
6. The wireless communication module according to claim 5, characterized in that, When the interface type selection pin is high, the first multiplexed pin is connected to the negative terminal of the PCIe data transmission differential signal pair. The second multiplexed pin is connected to the positive terminal of the PCIe data transmission differential signal pair; The third multiplexed pin is connected to the negative terminal of the PCIe data receive differential signal pair; The fourth multiplexed pin is connected to the positive terminal of the PCIe data receive differential signal pair; The fifth multiplexed pin is connected to the PCIe interface reset signal; The sixth multiplexed pin is connected to the PCIe reference clock request signal; The seventh multiplexed pin is connected to the negative terminal of the PCIe reference clock differential signal; The eighth multiplexed pin is connected to the PCIe system wake-up signal; The ninth multiplexed pin is connected to the positive terminal of the PCIe reference clock differential signal.
7. The wireless communication module according to claim 5, characterized in that, When the interface type selection pin input is low, the first multiplexed pin is connected to the negative terminal of the SGMII transmit data differential signal pair. The second multiplexed pin is connected to the positive terminal of the SGMII transmit data differential signal pair; The third multiplexed pin is connected to the negative terminal of the SGMII receive data differential signal pair; The fourth multiplexed pin is connected to the positive terminal of the SGMII receive data differential signal pair; The fifth multiplexed pin is connected to the SGMII reset signal; The seventh multiplexed pin is connected to the SGMII management data clock signal; The eighth multiplexed pin is connected to the SGMII interrupt signal; The ninth multiplexed pin is connected to the SGMII management data input / output signals.
8. The wireless communication module according to claim 1, characterized in that, The wireless communication module also includes: a radio frequency chip, an antenna, and a storage unit.
9. A wireless communication system, characterized in that, The wireless communication system includes the wireless communication module as described in any one of claims 1-8.