Mini-LED chip and display screen

Abstract

The utility model discloses a Mini-LED chip and a display screen, and relates to the field of semiconductor photoelectric devices. The Mini-LED chip comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate, and a transparent conductive layer and a P-type electrode are sequentially stacked on the P-type semiconductor layer; the Mini-LED chip further comprises a passivation reflection layer, an N-type bonding pad, a P-type bonding pad and a tin blocking layer. The tin blocking layer is made of insulating materials, the top of the tin blocking layer comprises a plurality of blocking strips arranged between the P-type bonding pad and the N-type bonding pad, and the top faces of the blocking strips are higher than the top face of the P-type bonding pad and the top face of the N-type bonding pad. According to the utility model, the barrier grooves between the barrier strips can effectively prevent the solder paste layers on the N-type bonding pad and the P-type bonding pad from being connected, and the welding yield is improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor optoelectronic devices, and in particular to a Mini-LED chip and display screen. Background Technology

[0002] Flip-chip mini LEDs can be used in COB direct-view solutions, achieving high-definition, high-resolution displays through individual control of the RGB three-primary-color chips. They offer advantages such as rich colors, energy efficiency, long lifespan, and lightweight design, gradually becoming mainstream in the display market. Currently, the smallest mini LED chip sizes are 3*6mil and 2*4mil. As the size decreases, the spacing between the solder pads also decreases. This makes the pads prone to solder bridging, causing N-type pads (connected to the negative electrode) and P-type pads (connected to the positive electrode) to connect together, resulting in a short circuit. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a Mini-LED chip that can effectively prevent solder bridging on the pads and improve the soldering yield.

[0004] The technical problem that this utility model also needs to solve is to provide a display screen with a high yield rate.

[0005] To address the aforementioned issues, this utility model discloses a Mini-LED chip, comprising: a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer sequentially stacked on the substrate, wherein a transparent conductive layer and a P-type electrode are sequentially stacked on the P-type semiconductor layer; and a stepped portion is formed on the N-type semiconductor layer, wherein an N-type electrode is provided on the stepped portion.

[0006] The Mini-LED chip further includes a passivation reflective layer, an N-type pad, a P-type pad, and a solder resist layer; the passivation reflective layer covers the P-type semiconductor layer, the transparent conductive layer, the P-type electrode, the step portion, and the N-type electrode, and the solder resist layer covers the passivation reflective layer;

[0007] The passivation reflective layer and the solder resist layer have N-type connection holes above the N-type electrode and P-type connection holes above the P-type electrode; the N-type pad is located above the N-type electrode and is connected to the N-type electrode through the N-type connection holes; the P-type electrode is located above the P-type electrode and is connected to the P-type electrode through the P-type connection holes.

[0008] The solder resist layer is made of insulating material, and its top includes multiple barrier strips disposed between the P-type pad and the N-type pad. A barrier groove is formed between adjacent barrier strips, and the top surface of the barrier strip is higher than the top surface of the P-type pad and the top surface of the N-type pad.

[0009] As an improvement to the above technical solution, the solder resist layer includes a bottom cover layer and a plurality of barrier strips disposed on the bottom cover layer, wherein the bottom cover layer covers the passivation reflective layer.

[0010] As an improvement to the above technical solution, the spacing between the multiple barrier strips may be the same or different;

[0011] The difference between the height of the barrier strip and the thickness of the N-type pad is 1.5 to 5 μm, and the thickness of the P-type pad is the same as the thickness of the N-type pad.

[0012] As an improvement to the above technical solution, the thickness of the covering layer is less than the thickness of the N-type pad and the thickness of the P-type pad;

[0013] The thickness of the P-type pad is the same as the thickness of the N-type pad.

[0014] As an improvement to the above technical solution, the thickness of both the N-type pad and the P-type pad is 1-5 μm;

[0015] The height of the barrier strip is 3–8 μm.

[0016] As an improvement to the above technical solution, multiple barrier strips are evenly distributed between the N-type pad and the P-type pad;

[0017] The spacing between adjacent barrier strips is 3 to 30 μm, and the width of the barrier strip is 4 to 20 μm.

[0018] As an improvement to the above technical solution, the distance between the barrier strip closest to the N-type pad and the N-type pad is 5 to 30 μm, and the distance between the barrier strip closest to the P-type pad and the P-type pad is 5 to 30 μm.

[0019] As an improvement to the above technical solution, the thickness of the covering layer is 0.1 to 0.8 μm.

[0020] As an improvement to the above technical solution, the tin resist layer is a SiO2 layer, a SiN layer, a SiON layer, or an Al2O3 layer.

[0021] Accordingly, this utility model also discloses a display screen, which includes the aforementioned Mini-LED chip.

[0022] Implementing this utility model has the following beneficial effects:

[0023] In one embodiment of the present invention, a solder resist layer is formed on the passivation reflective layer. The resist layer is made of insulating material and has multiple barrier strips on its top, which are located between the P-type pads and the N-type pads. The top surface of the barrier strip is higher than the top surface of the P-type pads and the top surface of the N-type pads. When solder paste is formed subsequently, the barrier grooves between the barrier strips can effectively prevent the solder paste layer on the N-type pads and the P-type pads from connecting, thereby improving the soldering yield. Attached Figure Description

[0024] Figure 1 This is a cross-sectional view of a Mini-LED chip in one embodiment of the present invention;

[0025] Figure 2 This is a top view of the Mini-LED chip in one embodiment of the present invention;

[0026] In the figure, 11 is the substrate, 12 is the N-type semiconductor layer, 13 is the active layer, 14 is the P-type semiconductor layer, 15 is the step portion, 2 is the transparent conductive layer, 3 is the N-type electrode, 4 is the P-type electrode, 5 is the passivation reflective layer, 6 is the N-type pad, 7 is the P-type pad, 8 is the barrier layer, 81 is the bottom cover layer, and 82 is the barrier strip. Detailed Implementation

[0027] To make the objectives, technical solutions and advantages of this utility model clearer, the utility model will be described in further detail below.

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0029] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0031] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0032] See Figure 1 , Figure 2 This embodiment discloses a Mini-LED chip, which includes a substrate 11, an N-type semiconductor layer 12, an active layer 13, and a P-type semiconductor layer 14 sequentially stacked on the substrate 11. A transparent conductive layer 2 and a P-type electrode 4 are sequentially stacked on the P-type semiconductor layer 14. A step portion 15 is formed on the N-type semiconductor layer 12, and an N-type electrode 3 is disposed on the step portion 15. The Mini-LED chip also includes a passivation reflective layer 5, an N-type pad 6, a P-type pad 7, and a solder resist layer 8. The passivation reflective layer 5 covers the P-type semiconductor layer 14, the transparent conductive layer 2, the P-type electrode 4, the step portion 15, and the N-type electrode 3, and the solder resist layer 8 covers the passivation reflective layer. 5. The passivation reflective layer 5 and the solder resist layer 8 have N-type connection holes above the N-type electrode 3 and P-type connection holes above the P-type electrode 4. The N-type pad 6 is located above the N-type electrode 3 and connected to the N-type electrode 3 through the N-type connection holes. The P-type electrode 4 is located above the P-type electrode 4 and connected to the P-type electrode 4 through the P-type connection holes. The solder resist layer 8 is made of insulating material, and its top includes multiple barrier strips 82 disposed between the P-type pad 7 and the N-type pad 6. The top surface of the barrier strips 82 is higher than the top surface of the P-type pad 7 and the top surface of the N-type pad 6. Based on the above embodiment, during subsequent solder paste formation, the grooves formed between the barrier strips 82 can effectively prevent the solder paste layer on the N-type pad 6 and the P-type pad 7 from connecting, thereby improving the soldering yield.

[0033] Specifically, substrate 11 can be a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited to these. Preferably, substrate 11 is a sapphire substrate. N-type semiconductor layer 12 can be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited to these. Active layer 13 can be an InGaN-GaN type multiple quantum well layer, an InGaN-AlGaN type multiple quantum well layer, or an AlGaN-AlGaN type multiple quantum well layer, but is not limited to these. P-type semiconductor layer 14 can be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited to these.

[0034] Preferably, in one embodiment of the present invention, the Mini-LED chip may further include one or more of the buffer layer, intrinsic semiconductor layer, stress buffer layer, electron blocking layer, and ohmic contact layer commonly used in the art, but is not limited thereto.

[0035] Specifically, the transparent conductive layer 2 can be a commonly used ITO layer, IZO layer, AZO layer, ATO layer, or FTO layer, but is not limited to these. Preferably, in one embodiment, the transparent conductive layer 2 is an ITO layer, which has strong conductivity, optimizes current spread, and has high light transmittance, thereby improving light extraction efficiency and thus improving the luminous efficiency of the Mini-LED chip. Specifically, the thickness of the transparent conductive layer 2 is [not specified in the original text]. Preferably The transparent conductive layer 2 at least partially covers the P-type semiconductor layer 14 to ensure uniform current distribution, reduce resistance loss, and improve the overall performance of the Mini-LED chip. Preferably, the ends of the transparent conductive layer 2 have at least partially exposed P-type semiconductor layer 14, which can then be completely wrapped by the passivation reflective layer 5 and the solder resist layer 8 to form a complete protective structure, effectively preventing interference from the external environment and further improving the stability and lifespan of the Mini-LED chip.

[0036] Specifically, the N-type electrode 3 and the P-type electrode 4 are common metal stacked structures in the art, such as stacked structures composed of one or more of Cr, Al, Ti, Pt, Au, and Ag, but are not limited thereto. The structures of the N-type electrode 3 and the P-type electrode 4 may be the same or different. The N-type electrode 3 is disposed on the stepped portion 15 exposing the N-type semiconductor layer 12 to form an electrical connection with the N-type semiconductor layer 12, and the P-type electrode 4 is disposed on the transparent conductive layer 2 to form an electrical connection with the P-type semiconductor layer 14. The thickness of the N-type electrode 3 and the P-type electrode 4 is [missing information].

[0037] Specifically, the passivation reflective layer 5 is a DBR layer commonly used in the art, such as SiO2 / TiO2, Ta2O5 / SiO2, or SiO2 / HfO2, but not limited to these. Specifically, the thickness of the passivation reflective layer 5 is...

[0038] Specifically, N-type pad 6 and P-type pad 7 are common metal pad structures in the art, such as a stacked structure composed of one or more of Cu, Ni, and Au, but are not limited thereto. The structures of N-type pad 6 and P-type pad 7 can be the same or different. Preferably, both N-type pad 6 and P-type pad 7 are Au layers.

[0039] Specifically, the thickness of the N-type pad 6 and the P-type pad 7 is 1–5 μm, exemplarily 1.5 μm, 2.2 μm, 2.9 μm, 3.5 μm, or 4.0 μm, but not limited thereto. The thickness of the N-type pad 6 and the P-type pad 7 may be the same or different. Preferably, in some embodiments, the thickness of the N-type pad 6 and the P-type pad 7 is the same, both being 2–4 μm.

[0040] Preferably, in some embodiments, the Mini-LED chip further includes a current blocking layer, which is a SiO2 layer or a SiN layer. x A current blocking layer is disposed below the P-type electrode 4 and above the P-type semiconductor layer 14, specifically between the P-type semiconductor layer 14 and the transparent conductive layer 2. This current blocking layer further optimizes the current distribution.

[0041] Specifically, the tin-blocking layer 8 is a common insulating material layer in the art, such as, but not limited to, a SiO2 layer, a SiN layer, a SiON layer, or an Al2O3 layer. Preferably, it is a SiO2 layer, which can effectively block tin diffusion and ensure electrode stability.

[0042] Specifically, in some embodiments, the solder resist layer 8 includes a bottom cover layer 81 and a plurality of barrier strips 82 disposed on the bottom cover layer 81, the bottom cover layer 81 covering the passivation reflective layer 5. Specifically, the thickness of the cover layer is less than the thickness of the N-type pad 6 and the P-type pad 7 to optimize heat dissipation of the Mini-LED chip. More specifically, the thickness of the bottom cover layer 81 is 0.1–1 μm. If its thickness is too large, it will affect the heat dissipation performance of the chip. If its thickness is too small, it cannot effectively block solder diffusion, leading to a decrease in electrode stability. Exemplarily, the thickness of the bottom cover layer 81 is 0.2 μm, 0.4 μm, 0.6 μm, or 0.8 μm, but is not limited thereto. Preferably, in some embodiments, the thickness of the bottom cover layer 81 is 0.1–0.8 μm.

[0043] Specifically, the barrier strips 82 are distributed in the form of elongated strips, concentric rings, or a grid, but are not limited to these. Preferably, in some embodiments, the barrier strips 82 are distributed in the form of elongated strips or concentric rings, and the spacing between adjacent barrier strips 82 may be the same or different. Based on this distribution, the conductive spacing of solder paste between N-type pads 6 and P-type pads 7 can be further improved, further reducing the occurrence of solder bridging. More preferably, the spacing between adjacent barrier strips 82 is the same. Specifically, it is 3 to 30 μm, and exemplary examples are 5 μm, 7 μm, 11 μm, 14 μm, or 19 μm, but are not limited to these.

[0044] A certain gap is provided between the barrier strip 82 and the N-type pad 6 / P-type pad 7 to prevent solder paste from flowing along the barrier strip 82 towards the other pad. Specifically, the distance between the barrier strip 82 closest to the N-type pad 6 and the N-type pad 6 is 5-30 μm, and the distance between the barrier strip 82 closest to the P-type pad 7 and the P-type pad 7 is 5-30 μm.

[0045] Specifically, the width of the barrier strip 82 is 3 to 20 μm, exemplarily 4 μm, 7 μm, 11 μm, 14 μm, 16 μm or 18 μm, but not limited thereto. Preferably it is 4 to 20 μm.

[0046] Specifically, in order to optimize the solder resisting effect, the difference between the height of the barrier strip 82 and the thickness of the N-type pad 6 is controlled to be 1.5 to 5 μm, more preferably 2 to 5 μm.

[0047] Specifically, the height of the barrier strip 82 is 2 to 8 μm, exemplarily 2.5 μm, 4 μm, 5.5 μm or 7 μm, but not limited thereto. Preferably, it is 3 to 8 μm.

[0048] Accordingly, in another embodiment of this utility model, a display screen is also disclosed, which includes the Mini-LED chip of the above embodiment, and has a high welding yield.

[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the described embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0050] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A Mini-LED chip, characterized in that, include: A substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially stacked on the substrate, a transparent conductive layer and a P-type electrode are sequentially stacked on the P-type semiconductor layer; a stepped portion is formed on the N-type semiconductor layer, and an N-type electrode is provided on the stepped portion; The Mini-LED chip further includes a passivation reflective layer, an N-type pad, a P-type pad, and a solder resist layer; the passivation reflective layer covers the P-type semiconductor layer, the transparent conductive layer, the P-type electrode, the step portion, and the N-type electrode, and the solder resist layer covers the passivation reflective layer; The passivation reflective layer and the solder resist layer have N-type connection holes above the N-type electrode and P-type connection holes above the P-type electrode; the N-type pad is located above the N-type electrode and is connected to the N-type electrode through the N-type connection holes; the P-type electrode is located above the P-type electrode and is connected to the P-type electrode through the P-type connection holes. The solder resist layer is made of insulating material, and its top includes multiple barrier strips disposed between the P-type pad and the N-type pad. The top surface of the barrier strips is higher than the top surface of the P-type pad and the top surface of the N-type pad.

2. The Mini-LED chip as described in claim 1, characterized in that, The tin resist layer includes a bottom cover layer and a plurality of barrier strips on the bottom cover layer, wherein the bottom cover layer covers the passivation reflective layer.

3. The Mini-LED chip as described in claim 1, characterized in that, The spacing between the multiple barrier strips may be the same or different; The difference between the height of the barrier strip and the thickness of the N-type pad is 1.5 to 5 μm, and the thickness of the P-type pad is the same as the thickness of the N-type pad.

4. The Mini-LED chip as described in claim 2, characterized in that, The thickness of the overlay layer is less than the thickness of the N-type pad and the thickness of the P-type pad; The thickness of the P-type pad is the same as the thickness of the N-type pad.

5. The Mini-LED chip as described in claim 1, characterized in that, The thickness of both the N-type pad and the P-type pad is 1–5 μm; The height of the barrier strip is 3–8 μm.

6. The Mini-LED chip as described in claim 1, characterized in that, Multiple barrier strips are evenly distributed between the N-type pad and the P-type pad; The spacing between adjacent barrier strips is 3 to 30 μm, and the width of the barrier strip is 4 to 20 μm.

7. The Mini-LED chip as described in claim 1, characterized in that, The distance between the barrier strip closest to the N-type pad and the N-type pad is 5 to 30 μm, and the distance between the barrier strip closest to the P-type pad and the P-type pad is 5 to 30 μm.

8. The Mini-LED chip as described in claim 2, characterized in that, The thickness of the covering layer is 0.1 to 0.8 μm.

9. The Mini-LED chip as described in claim 1, characterized in that, The tin resist layer is a SiO2 layer, an SVN layer, a SiON layer, or an Al2O3 layer.

10. A display screen, characterized in that, Includes the Mini-LED chip as described in any one of claims 1 to 9.

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