Display panel and display device

Abstract

The utility model provides a display panel and a display device.The display panel of one embodiment comprises a display area and a non-display area, the non-display area comprises a gate drive circuit and a selection circuit, the display area comprises N refresh areas, the gate drive circuit comprises N gate drive sub-circuits, each gate drive sub-circuit comprises a plurality of cascaded shifting register circuits, N is a positive integer, N is a positive integer, N is a positive integer, and N is a positive integer. The selection circuit comprises N selection sub-circuits, each selection sub-circuit comprises a first power signal end, an output end and at least two selection ends, the first power signal end is electrically connected to a first power line, and the output end is electrically connected to the input end of a first-stage shift register circuit of the gate driving sub-circuit corresponding to the selection sub-circuit; the at least two selection ends are electrically connected to one selection signal line respectively, and the first power supply signal end is electrically connected with the output end based on the fact that signals accessed by the at least two selection ends are effective levels. According to the embodiment of the invention, the narrow frame design can be realized while the display panel with multiple refresh regions is realized.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Currently, e-paper screens are finding increasingly wider applications due to their low power consumption, wide viewing angles, and eye-friendly features. Long, rectangular e-paper screens are frequently used in billboards, product labels, and signs. However, using a multi-screen splicing module approach leads to increased costs due to the need for multiple driver chips, while using a multi-refresh-area setup results in more signal lines and a limited number of refresh areas. Utility Model Content

[0003] To address at least one of the aforementioned problems, a first aspect of this disclosure provides a display panel, comprising: a display area and a non-display area, wherein the non-display area includes a gate driving circuit and a selection circuit, and the display area includes N refresh areas.

[0004] The gate driving circuit includes N gate driving sub-circuits, each of which includes multiple cascaded shift register circuits. The shift register circuits provide scan signals to the pixel circuits of the corresponding rows in the display area. The selection circuit includes N selection sub-circuits.

[0005] The selection sub-circuit includes a first power supply signal terminal, an output terminal, and at least two selection terminals. The first power supply signal terminal is electrically connected to a first power supply line, the output terminal is electrically connected to the input terminal of the first-stage shift register circuit of the gate drive sub-circuit corresponding to the selection sub-circuit, and the at least two selection terminals are each electrically connected to a selection signal line. The first power supply signal terminal is configured to be electrically connected to the output terminal based on the signals connected to the at least two selection terminals being at an effective level.

[0006] Where N is an integer greater than or equal to 2.

[0007] Optionally, the selection sub-circuit includes M selection switches connected in series. The first terminal of the (n+1)th selection switch is electrically connected to the second terminal of the nth selection switch, the first terminal of the first selection switch is electrically connected to a first power signal terminal, and the second terminal of the Mth selection switch is electrically connected to the output terminal of the selection sub-circuit. The control terminals of the M selection switches are respectively electrically connected to at least two selection terminals.

[0008] Where n is an integer greater than or equal to 1 and less than M, and M is an integer greater than or equal to 2.

[0009] Optionally, at least two selection switches are either N-type transistors or both are P-type transistors.

[0010] Optionally, the display panel also includes: K selection signal lines, where K satisfies:

[0011] Optionally, the shift register circuit includes: an input sub-circuit, a pull-up sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit.

[0012] The input sub-circuit is electrically connected between the input of the shift register circuit and the pull-up node, and is configured to transmit the valid level signal to the pull-up node based on the signal at the input of the shift register circuit.

[0013] The pull-up sub-circuit is electrically connected to the first clock signal terminal, the output terminal of the shift register circuit, and the pull-up node, and is configured to electrically connect the first clock signal terminal and the output terminal based on the signal from the pull-up node.

[0014] The pull-down control sub-circuit is electrically connected between the second power signal terminal and the first pull-down node, and is configured to electrically connect the second power signal terminal and the first pull-down node based on the first power signal of the second power signal terminal.

[0015] The pull-down sub-circuit is electrically connected to the first pull-down node, the third power signal terminal, and the pull-up node, and is configured to electrically connect the third power signal terminal to the first pull-down node based on the signal from the pull-up node.

[0016] Optionally, the shift register circuit includes: an input sub-circuit, a first control sub-circuit, and an output sub-circuit.

[0017] An input sub-circuit is electrically connected to the input terminal of the shift register circuit, the first node, and the second clock signal terminal, and is configured to electrically connect the input terminal of the shift register circuit to the first node based on the signal from the second clock signal terminal.

[0018] The first control sub-circuit is electrically connected to the fourth power signal terminal, the second node and the second clock signal terminal, and is configured to electrically connect the fourth power signal terminal and the second node based on the signal of the second clock signal terminal.

[0019] An output sub-circuit is electrically connected to a third node, a third clock signal terminal, and an output terminal, and is configured to output the signal of the third clock signal terminal to the output terminal of the shift register circuit based on the signal of the third node.

[0020] An output control sub-circuit is electrically connected to the second node, the fifth power signal terminal, and the output terminal, and is configured to electrically connect the fifth power signal terminal to the output terminal of the shift register circuit based on the signal from the second node.

[0021] Optionally, the transistor in the shift register circuit is an N-type transistor, and the first power supply signal terminal is connected to a high-level signal.

[0022] Optionally, a high-level signal is connected to the first power signal terminal, and the transistor in the display panel is a metal-oxide-slim transistor.

[0023] Optionally, the selector circuit includes two selector switches.

[0024] A second aspect of this disclosure provides a display device including the display panel described above. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram illustrating a display panel according to an embodiment of the present disclosure;

[0027] Figure 2 This is a partial schematic diagram illustrating a display panel according to an embodiment of the present disclosure;

[0028] Figure 3 To illustrate the circuit schematic of a selection sub-circuit in a display panel according to an embodiment of the present disclosure;

[0029] Figure 4 Showing satisfaction Figure 3 A schematic timing diagram of the selection signal line for the structure shown;

[0030] Figure 5 To illustrate the circuit schematic of a selection sub-circuit in a display panel according to an embodiment of the present disclosure;

[0031] Figure 6 To show a comparison of the Idd-Vth characteristics of different types of transistors;

[0032] Figure 7 A schematic circuit diagram illustrating a pixel sub-circuit in a display panel according to an embodiment of the present disclosure;

[0033] Figure 8 This is a schematic circuit diagram of a pixel sub-circuit in a display panel according to another embodiment of the present disclosure.

[0034] The beneficial effects of this disclosure are as follows:

[0035] This disclosure addresses existing problems by providing a display panel and display device. It achieves a multi-refresh-area display panel by providing a selection sub-circuit and a gate drive sub-circuit corresponding to each refresh area, and by combining signals from at least two selection terminals of the selection sub-circuit, using minimal data signal lines and a simplified circuit structure. This allows for a greater number of refresh areas with fewer wiring steps, reduces leakage current between refresh areas, balances display quality with narrow bezel requirements, and lowers product costs, thus demonstrating broad application prospects. Detailed Implementation

[0036] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0037] It should be noted that the ordinal numbers such as "first," "second," "third," etc., used in this article are not intended to restrict the order of individual units, nodes, elements, or components, but only to distinguish them. The terms "including," "containing," and "having" in this article are open-ended; for example, when describing the inclusion of units, nodes, elements, or components, other units, nodes, elements, or components may also be included in addition to those included.

[0038] In related technologies, when using elongated display products, especially elongated electronic paper displays with a large aspect ratio, multiple independently controlled and displayed electronic paper displays with smaller aspect ratios are typically spliced ​​together to form a display module. This type of multi-display splicing module with independent control and driving requires multiple control chips. For example, it can be divided along the length of the display into multiple splicing modules with the same width but different lengths. A Data IC providing data signals is placed on one side of the overall width of the splicing module, and a Gate IC providing scanning signals is placed in each area on the long side of the splicing module. Of course, the Gate IC can also be placed on the same side as the Data IC. For example, electronic paper products exceeding 1.5m in length, such as signs and billboards, often require more than 10 Gate ICs. It is evident that with this approach, the larger the aspect ratio and size of the display product, the more chips need to be bonded or soldered, resulting in higher costs; simultaneously, bonding driver chips to the bezel also increases the bezel width.

[0039] However, currently, if a separate Gate IC is not used for each zone, and instead a zoned refresh method is used to provide scan signals to the display panel, each refresh zone's scan circuit often draws an independent input signal line to start scanning independently. The number of refresh zones is equal to the number of additional signal lines. The inventors' experiments revealed that the fewer the number of refresh zones, the more pronounced the display crosstalk between zones.

[0040] Further research revealed that, as a reflective display, electronic paper displays require multiple frames and tens of seconds to refresh a single image. A single data signal line writes data to pixels in multiple refresh zones within the same column. While one refresh zone refreshes, this data signal line repeatedly writes data. Unrefreshed areas are affected by this data signal, and the coupling capacitor Cpd between the pixel and the data signal line needs to be influenced by the voltage of the data signal to store charge. Simultaneously, the off-state leakage current Ioff in the unrefreshed area causes the data signal voltage to leak into the pixel, thus affecting the original reset pixel voltage within the unrefreshed area. The fewer the number of refresh zones, the longer the unrefreshed area is affected by the refresh zones, resulting in more charge written to the coupling capacitor Cpd and a larger off-state leakage current Ioff voltage.

[0041] It is evident that current elongated display products, especially elongated electronic paper displays, face challenges in balancing narrow bezel design requirements, refresh rate crosstalk, and product cost.

[0042] In view of this, the embodiments of the present disclosure display panel includes a display area and a non-display area. The non-display area includes a gate driving circuit and a selection circuit, and the display area includes N refresh areas.

[0043] The gate driving circuit includes N gate driving sub-circuits, each of which includes multiple cascaded shift register circuits. The shift register circuits provide scan signals to the pixel circuits of the corresponding rows in the display area. The selection circuit includes N selection sub-circuits.

[0044] The selection sub-circuit includes a first power supply signal terminal, an output terminal, and at least two selection terminals. The first power supply signal terminal is electrically connected to a first power supply line, the output terminal is electrically connected to the input terminal of the first-stage shift register circuit of the gate drive sub-circuit corresponding to the selection sub-circuit, and the at least two selection terminals are each electrically connected to a selection signal line. The first power supply signal terminal is configured to be electrically connected to the output terminal based on the signals connected to the at least two selection terminals being at an effective level.

[0045] Where N is an integer greater than or equal to 2.

[0046] In this embodiment, by providing a selection sub-circuit and a gate drive sub-circuit that correspond one-to-one with the refresh area, and by combining the signals of at least two selection terminals of the selection sub-circuit, a display panel with multiple refresh areas can be realized with very few data signal lines and a simplified circuit structure. This allows for the realization of more refresh areas with fewer wirings, reduces the impact of leakage current between refresh areas, balances display effect and narrow bezel requirements, and reduces product costs.

[0047] In one specific embodiment, refer to Figure 1 As shown, the display panel 1 includes a display area AA and a non-display area NA. The non-display area NA is located around the display area AA. In this example, the non-display area NA surrounds the display area AA.

[0048] In this example, the display area AA includes 10 refresh areas AA1-AA10, which are arranged in one direction, as shown by the arrow in the figure. The display area AA includes multiple pixel circuits arranged in an array. The pixel circuits include multiple rows arranged along the refresh area's arrangement direction and multiple rows arranged along a direction intersecting with the arrangement direction of the 10 refresh areas.

[0049] Optionally, in this example, the arrangement direction of the 10 refresh areas AA1-AA10 is the long side extension direction of the display panel 1. The display panel 1 also includes a driver chip IC, which is disposed on the short side of the display panel 1 to provide data signals, power signals, etc. to each column of pixel circuits in the display panel 1, and to provide clock signals, power signals, etc. to the gate drive circuits in the non-display area NA.

[0050] Optionally, the display panel 1 may also be connected to the flexible circuit board 2 on one side of the driver chip IC so as to obtain power signals from the driver board such as the printed circuit board through the flexible circuit board 2. This will not be elaborated in this article.

[0051] It should be understood that, although Figure 1 The diagram shows a display panel 1 comprising 10 refresh zones. However, this disclosure is not intended to limit the number of refresh zones; the specific number can be set as needed. Under the same conditions, a higher number of refresh zones generally results in less crosstalk between them. For ease of description, the following description uses a display panel with 10 refresh zones as an example. Of course, in the embodiments of this disclosure, the number of refresh zones should be greater than or equal to 2.

[0052] Reference Figure 2As shown, the non-display area NA includes a gate drive circuit 10 and a selection circuit 11. The gate drive circuit 10 includes 10 gate drive sub-circuits, each including multiple cascaded shift register circuits. The number of gate drive sub-circuits is the same as the number of refresh areas, or in other words, they are configured in a one-to-one correspondence. The selection circuit 11 includes 10 selection sub-circuits 11_1 to 11_10. The number of selection sub-circuits is the same as the number of gate drive sub-circuits; that is, one refresh area corresponds to one gate drive sub-circuit and one selection circuit.

[0053] In this example, the arrangement direction of the 10 gate drive sub-circuits is the same as that of the 10 refresh areas AA1-AA10, so as to connect with the signal lines, such as gate lines, of the pixel circuits in the corresponding refresh areas, thereby providing scan signals to the pixel circuits in the corresponding rows.

[0054] In this example, refer to Figure 2 As shown, each of the 10 shift register sub-circuits includes the same number of cascaded shift register circuits. For example, the first gate drive sub-circuit includes cascaded shift register circuits G1-Gk, the second gate drive sub-circuit includes cascaded shift register circuits G(k+1)-G2k, the third gate drive sub-circuit includes cascaded shift register circuits G(2k+1)-G3k, the fourth gate drive sub-circuit includes cascaded shift register circuits G(3k+1)-G4k, the fifth gate drive sub-circuit includes cascaded shift register circuits G(4k+1)-G5k, and the sixth... The gate driver sub-circuit includes cascaded shift register circuits G(5k+1)-G6k, the 7th gate driver sub-circuit includes cascaded shift register circuits G(6k+1)-G7k, the 8th gate driver sub-circuit includes cascaded shift register circuits G(7k+1)-G8k, the 9th gate driver sub-circuit includes cascaded shift register circuits G(8k+1)-G9k, and the 10th gate driver sub-circuit includes cascaded shift register circuits G(9k+1)-G10k.

[0055] By setting the number of cascaded shift registers in each gate driver sub-circuit to be the same, the mutual influence between adjacent refresh areas is balanced when refreshing each area, thereby improving the display uniformity of the display area.

[0056] Of course, this disclosure is not intended to be limited thereto. The number of cascaded shift registers in the gate driver sub-circuit may vary when the balance between regions is not a concern or when the distribution cannot be even in some cases.

[0057] It should also be noted that this disclosure is not intended to limit the scan signal output by the shift register in each gate driver sub-circuit to correspond to the row-by-row pixel circuit of the corresponding refresh area. In other words, the cascaded shift registers may be electrically connected only to the row-by-row sequential scan refresh area, or they may be electrically connected only to the pixel circuits of even-numbered rows, odd-numbered rows, or multiple rows spaced apart. Furthermore, when multiple scan signals are required for the pixel circuits, the display panel may include multiple gate driver circuits 10 and corresponding selection circuits 11.

[0058] In other words, optionally, the display panel may include one or more sets of gate driving circuits 10, the specific number of which depends on the driving mode of the pixel circuits in the display panel and the scanning method of the gate driving circuits on the pixel circuits in the scanning area.

[0059] Reference Figure 2 As shown, each of the selection sub-circuits 11_1 to 11_10 includes a first power supply signal terminal Vgh, an output terminal out, and two selection terminals C-1 and C-2. The first power supply signal terminal Vgh is electrically connected to the first power supply line Vgh1, and the output terminal out is electrically connected to the input terminal of the first-stage shift register circuit of the gate drive sub-circuit corresponding to the selection sub-circuit. The two selection terminals C-1 and C-2 are respectively electrically connected to a selection signal line, and are configured to electrically connect the first power supply signal terminal Vgh and the output terminal out based on the signals connected to the two selection terminals C-1 and C-2 being at an effective level.

[0060] It should be noted that, Figure 2 The position of the input terminal (Input) of the shift register circuit connected to the output terminal (out) of the selector circuit is not used to limit the number of stages of the electrically connected shift register. Figure 2 This is only intended to illustrate electrical connections and will not be elaborated upon further in this article.

[0061] It should also be noted that, although Figure 2 The diagram shows a selector circuit with two select terminals, but this disclosure is not intended to be limited thereto, and the selector circuit may also include more select terminals.

[0062] Figure 3 Showing satisfaction Figure 2 The circuit schematic is shown as an example of a selector circuit structure. (Refer to...) Figure 3 As shown, the selection sub-circuit includes two selection switches, T1 and T2, connected in series.

[0063] The first pole of the second selector switch T2 is electrically connected to the second pole of the first selector switch T1. The first pole of the first selector switch T1 is electrically connected to the first power supply signal terminal Vgh. The second pole of the second selector switch T2 is electrically connected to the output terminal out of the selector circuit. That is, the second pole of selector switch T2, as the output terminal out of the selector circuit, is electrically connected to the input terminal Input of the first stage shift register circuit of the corresponding gate drive sub-circuit. The control pole of selector switch T1 is electrically connected to the selection terminal C-1, and the control pole of selector switch T2 is electrically connected to the selection terminal C-2.

[0064] Combination Figure 2 and Figure 3 As shown, the non-display area NA of the display panel 1 is provided with 5 selection signal lines, specifically the first selection signal line C1, the second selection signal line C2, the third selection signal line C3, the fourth selection signal line C4, and the fifth selection signal line C5.

[0065] Specifically, the first selection terminal C-1 of selection sub-circuit 11_1 is electrically connected to the first selection signal line C1, and the second selection terminal C-2 is electrically connected to the second selection signal line C2; ​​the first selection terminal C-1 of selection sub-circuit 11_2 is electrically connected to the first selection signal line C1, and the second selection terminal C-2 is electrically connected to the third selection signal line C3; the first selection terminal C-1 of selection sub-circuit 11_3 is electrically connected to the first selection signal line C1, and the second selection terminal C-2 is electrically connected to the fourth selection signal line C4; the first selection terminal C-1 of selection sub-circuit 11_4 is electrically connected to the first selection signal line C1, and the second selection terminal C-2 is electrically connected to the fifth selection signal line C5; the first selection terminal C-1 of selection sub-circuit 11_5 is electrically connected to the second selection signal line C2, and the second selection terminal C-2 is electrically connected to the third selection signal line C3. 3; The first selection terminal C-1 of the selection sub-circuit 11_6 is electrically connected to the second selection signal line C2, and the second selection terminal C-2 is electrically connected to the fourth selection signal line C4; The first selection terminal C-1 of the selection sub-circuit 11_7 is electrically connected to the second selection signal line C2, and the second selection terminal C-2 is electrically connected to the fifth selection signal line C5; The first selection terminal C-1 of the selection sub-circuit 11_8 is electrically connected to the third selection signal line C3, and the second selection terminal C-2 is electrically connected to the fourth selection signal line C4; The first selection terminal C-1 of the selection sub-circuit 11_9 is electrically connected to the third selection signal line C3, and the second selection terminal C-2 is electrically connected to the fifth selection signal line C5; The first selection terminal C-1 of the selection sub-circuit 11_10 is electrically connected to the fourth selection signal line C4, and the second selection terminal C-2 is electrically connected to the fifth selection signal line C5.

[0066] As can be seen, in this example, the combination of selection signal lines connected to the two selection terminals of each selector circuit is different, and only 5 signal lines are needed to provide 10 different signal line combinations. Of course, those skilled in the art should understand that for... Figure 2 The number of partitions and the number of select terminals of the selector circuits, as well as the number of signal lines, can provide 10 different signal line connection combinations, and the minimum number of selector signal lines is 5.

[0067] Optionally, in embodiments of this disclosure, when the selection sub-circuit includes two selection switches connected in series, the display panel includes: K selection signal lines, where K satisfies:

[0068] Additionally, it should be noted that if the number of selection switches connected in series in the selection sub-circuit is M, then the display panel includes K selection signal lines, where K satisfies: M is an integer greater than or equal to 2.

[0069] It should be understood that the smallest integer value K that satisfies the above relationship is the minimum number of selection signal lines required to realize the selection end combination relationship.

[0070] Reference Figure 3 As shown, both selector switches T1 and T2 are N-type transistors. Figure 4 The timing diagram for selecting signal lines C1, C2, C3, C4, and C5 is shown.

[0071] Reference Figure 2 and Figure 4 As shown, during the time period t1 at the beginning of the nth frame, the first selection signal line C1 and the second selection signal line C2 are at a high level, while the third selection signal line C3, the fourth selection signal line C4, and the fifth selection signal line C5 are all at a low level. During time period t1, only the selection switches T1 and T2 in the selection sub-circuit 11_1 are turned on, thus electrically connecting the first power supply signal terminal Vgh to the output terminal out. That is, the high-level signal of the first power supply signal terminal Vgh is transmitted to the input terminal Input of the shift register circuit G1, which starts the cascaded shift register circuits G1 to Gk to sequentially output scanning signals to the corresponding row pixel circuits in the refresh area AA1. At the same time, because the third selection signal line C3, the fourth selection signal line C4, and the fifth selection signal line C5 are all at a low level, at least one of the selection switches T1 and T2 in the selection sub-circuits 11_1 to 11_10 that have a selection terminal electrically connected to these three selection signal lines is turned off. The other refresh areas AA2 to AA10 do not refresh during the time period when refresh area AA1 is refreshed.

[0072] It should be noted that, in order to ensure that each gate driver sub-circuit correctly outputs the scan signal during the refresh period of the corresponding refresh area, the timing of the effective level output of the selection signal line electrically connected to the selection terminal of the selection sub-circuit corresponding to the gate driver sub-circuit should be consistent with the time period of the effective level input of the first-stage shift register circuit in the gate driver sub-circuit, and the effective level signal is only output during this time period to ensure that no effective signal is output after an initial signal is input.

[0073] Of course, it should be noted that the cascaded shift register circuits are independent of each other; that is, there is no cascading relationship between the gate driver sub-circuits. However, the gate driver sub-circuits can share signal lines.

[0074] Optionally, the selector switches in the selector sub-circuit can also all be P-type transistors. For example, refer to... Figure 5 The selector switches T1 and T2 shown can also be applied to Figure 2 The selector circuit shown is connected to a high-level voltage signal at the first power supply signal terminal Vgh.

[0075] Specifically, refer to Figure 5 As shown, when both selection switches T1 and T2 are P-type transistors, the first terminal of selection switch T1 corresponding to the source is electrically connected to the first power supply signal terminal Vgh, and the second terminal corresponding to the drain is electrically connected to the first terminal of selection switch T2 corresponding to the source. The second terminal of selection switch T2 corresponding to the drain is electrically connected to the output terminal out. In this example, when the selection terminals C-1 and C-2 are connected to a low-level signal, the high-level voltage signal of the first power supply signal terminal Vgh is transmitted to the input terminal Input of the first-stage shift register circuit of the gate drive sub-circuit corresponding to the selection sub-circuit.

[0076] It should be noted that although this disclosure does not limit the conductivity type of the selection switches in the selection circuit, in order to ensure that multiple selection combinations consisting of a few selection signal lines select only one selection switch in the selection sub-circuit and all of them are turned on at one time without logic errors, the embodiments of this disclosure require that all selection switches in the selection sub-circuit have the same conductivity type.

[0077] It should also be noted that, although Figure 3 and Figure 5 The diagram shows a high-level voltage signal connected to the first power supply signal terminal Vgh, but this disclosure is not limited thereto. Because the selector switch is typically a thin-film transistor (TFT), the TFT can perform the switching function without distinguishing the specific polarities of the first and second terminals. Therefore, regardless of whether the selector switch is an N-type or P-type transistor, as long as the level connected to the control terminal meets the conduction condition, and the first power supply signal terminal is a low-level voltage signal, the selector switch can conduct to electrically connect the first signal terminal to the output terminal out.

[0078] In the embodiments of this disclosure, whether the signal connected to the first power supply signal terminal Vgh is a high-level voltage signal or a low-level voltage signal depends on the circuit structure in the shift register circuit electrically connected to it, and further depends on the type of transistor in the pixel circuit of the refresh area that receives the scan signal.

[0079] With the above settings, the display area is divided into multiple refresh areas, and a gate drive sub-circuit and a selection sub-circuit electrically connected to the input of the first-stage shift register circuit in the gate drive sub-circuit are set in the non-display area, each corresponding to a refresh area. The selection sub-circuit is composed of selection switches connected in series. Thus, only a few selection signal lines are needed to form a unique combination of selection signal lines corresponding to the selection sub-circuit. The time-division refresh selection of the refresh area is achieved by using the logical combination of signals connected to the selection signal lines. Moreover, the number of selection signal lines in this setting is much smaller than the number of refresh areas. For example, only 5 selection signals are needed for 10 refresh areas, reducing the number of input signal lines by half, so that it is not necessary to add an input signal line for each refresh area.

[0080] In other words, by significantly reducing the number of signal lines needed to select the refresh area through the above-described configuration, it is possible to divide the display into far more than two refresh areas while maintaining the same narrow bezel size. That is, by increasing the number of refresh areas, the refresh time of each refresh area on a display panel of the same size is greatly shortened, and the voltage impact of Cpd and Ioff on other unrefreshed areas is significantly reduced, thereby improving the display effect of the display panel. Of course, the above structure eliminates the need for multiple gate scanning chips. Therefore, the above-described configuration of this disclosure can simultaneously meet the requirements of narrow bezel design, reduce crosstalk in the refresh area, and meet low-cost requirements, and has broad application prospects.

[0081] Further research by the inventors revealed that transistors made of different semiconductor materials have different inherent characteristics, and the type of semiconductor material in the transistor also affects the magnitude of the voltage impact of Cpd and Ioff during crosstalk between refresh regions. (See reference...) Figure 6The Idd-Vth characteristic diagram shown represents the value of the transistor drain current Idd as the threshold voltage increases. Idd during TFT-off represents the off-state drain current, and Idd during TFT-on represents the on-state current. As can be seen from the diagram, the low-temperature polysilicon (LTPS) transistor has the largest on-state current, but also the largest off-state drain current. The amorphous silicon (a-Si) transistor has the smallest on-state current, but its off-state drain current is not small. In contrast, the indium gallium zinc oxide (IGZO) transistor has an on-state current close to that of the LTPS transistor, while its off-state drain current is much lower than the other two types of transistors. Numerically, the on-state drain current and off-state drain current Ion / Ioff of the IGZO transistor are greater than 10. 9 The on-state leakage current and off-state leakage current of the transistor, Ion / Ioff, are approximately equal to 10. 7 The on-state leakage current and off-state leakage current Ion / Ioff of an a-Si transistor are approximately equal to 10. 6 A larger off-state leakage current results in a greater voltage impact from Ioff caused by crosstalk between refresh areas, while a smaller off-state leakage current results in a smaller voltage impact from Ioff caused by crosstalk between refresh areas. We want the transistors in the refresh areas of the display panel to have large on-state current and small off-state current. Therefore, using IGZO transistors in the display panel can further reduce the crosstalk between refresh areas.

[0082] In this case, when the transistors in the display panel are IGZO transistors, the effective level scan signal of the shift register circuit needs to be a high-level signal. Therefore, the transistors in the shift register circuit are N-type transistors. When the selection switch in the selection sub-circuit is turned on, the first power supply signal terminal Vgh transmits a high-level signal to the input terminal Input of the corresponding electrically connected shift register circuit.

[0083] Optionally, Figure 7 The circuit schematic of a shift register circuit is shown, in which all transistors are N-type transistors.

[0084] from Figure 7 As shown, by way of example, the shift register circuit of this disclosure embodiment may include: input sub-circuit 101, pull-up sub-circuit 102, pull-down control sub-circuit 103 and pull-down sub-circuit 104.

[0085] The input sub-circuit 101 is electrically connected between the input terminal Input of the shift register circuit and the pull-up node PU, and is configured to transmit the valid level signal to the pull-up node PU based on the signal of the input terminal Input of the shift register circuit.

[0086] Pull-up sub-circuit 102 is electrically connected to the first clock signal terminal CLK of the shift register circuit, the output terminal Output of the shift register circuit, and the pull-up node PU, and is configured to electrically connect the first clock signal terminal CLK and the output terminal Output based on the signal of the pull-up node PU.

[0087] The pull-down control sub-circuit 103 is electrically connected between the second power supply signal terminal GCH of the shift register circuit and the first pull-down node PD, and is configured to electrically connect the second power supply signal terminal GCH and the first pull-down node PD based on the first power supply signal of the second power supply signal terminal GCH.

[0088] The pull-down sub-circuit 104 is electrically connected to the first pull-down node PD, the third power signal terminal VGL, and the pull-up node PU of the shift register circuit, and is configured to electrically connect the third power signal terminal VGL to the first pull-down node PD based on the signal of the pull-up node PU.

[0089] Specifically, the input sub-circuit 101 includes a first transistor M1. The first electrode of the first transistor M1 is electrically connected to the sixth power supply signal terminal VDS, the second electrode is electrically connected to the pull-up node PU, and the control electrode is electrically connected to the input terminal Input. When a high-level signal is received at the input terminal Input, the high-level signal of the sixth power supply signal terminal VDS is transmitted to the pull-up node PU. Of course, the structure of the input sub-circuit 101 is not limited to this. The first electrode and the control electrode of the first transistor M1 can be electrically connected to the input terminal Input simultaneously, which will not be elaborated in this article.

[0090] The pull-up circuit 102 includes a first capacitor C1 and a second transistor M2. The first stage of the second transistor M2 is electrically connected to the first clock signal terminal CLK, the second stage is electrically connected to the output terminal Output of the shift register circuit, and the control stage is electrically connected to the pull-up node PU. The first stage of the first capacitor is electrically connected to the pull-up node PU, and the second stage is electrically connected to the output terminal Output. When a high-level input signal is written to the pull-up node PU, the first capacitor C1 is charged. Then, using the bootstrap function of the first capacitor C1, when the first clock signal terminal CLK is high, the output terminal Output outputs a high-level scan signal.

[0091] The pull-down control sub-circuit 103 may include a third transistor M3. The first terminal and the control terminal of the third transistor M3 are electrically connected to the second power supply signal terminal GCH, and the second terminal is electrically connected to the first pull-down node PD. When the second power supply signal terminal GCH is high, the high-level signal of the second power supply signal terminal GCH is transmitted to the first pull-down node PD. Of course, this disclosure is not intended to limit the specific structure of the circuit; any structure that can set the first pull-down node PD to a high level at an appropriate time via a switch is acceptable.

[0092] The pull-down sub-circuit 104 includes a fourth transistor M4. The first electrode of the fourth transistor M4 is electrically connected to the first pull-down node PD, the control electrode is electrically connected to the pull-up node PU, and the second electrode is electrically connected to the third power supply signal terminal VGL. When the pull-up node PU is high, the first pull-down node PD is pulled low by the low-level signal of the third power supply signal terminal VGL.

[0093] It should be understood that this disclosure is not intended to be limited to a branch consisting of only one pull-down control subcircuit and a pull-down subcircuit. In some cases, it may also include a branch consisting of two pull-down control subcircuit and a pull-down subcircuit, thereby improving the leakage current of the branch and enhancing circuit stability.

[0094] Continue to refer to Figure 7 As shown, optionally, in addition to the above basic structure, the shift register circuit may also include a first reset sub-circuit 105, a second reset sub-circuit 106, a first noise reduction sub-circuit 107 and a second noise reduction sub-circuit 108 controlled by the first pull-down node PD. Additionally, optionally, a stabilization circuit 109 may also be included.

[0095] For example, the first reset sub-circuit 105 includes a fifth transistor M5, which, in response to the first reset control terminal Reset being high, transmits a low-level signal from the fifth power supply signal terminal VSD to the pull-up node PU to reset it. Optionally, the first reset control terminal Reset can be electrically connected to the output terminal of the next stage to form a partial reset. The second reset sub-circuit 106 includes a sixth transistor M6, which, in response to the second reset control terminal STV0 being high, transmits a low-level signal from the third power supply signal terminal VGL to the pull-up node PU to reset it. Optionally, the second reset control terminal STV0 can be a global reset terminal. Of course, the specific functions of the first reset sub-circuit 105 and the second reset sub-circuit 106 can be interchanged.

[0096] The first noise reduction sub-circuit 107 includes a seventh transistor M7, and the second noise reduction sub-circuit 108 includes an eighth transistor M8. Both respond to the high level of the signal at the first pull-down node PD by using the low level of the third power supply signal terminal VGL to pull down the pull-up node PU and the output terminal Output, respectively, for noise reduction. The stabilization circuit 109 further ensures the normal output of the output terminal Output through the ninth transistor M9.

[0097] It should be noted that this disclosure is not intended to limit the specific function of the shift register circuit to this; other circuits with similar main frame structures that can satisfy the function of the shift register circuit are all protected by this disclosure.

[0098] Optionally, Figure 8 The circuit schematic of another typical shift register circuit is shown, in which all transistors are N-type transistors. Note that, in order to... Figure 7 The transistors within the circuit are distinguished, and transistors with similar serial numbers are represented by different labels.

[0099] Reference Figure 8 As shown, the shift register circuit includes: an input sub-circuit 111, a first control sub-circuit 112, and an output sub-circuit 113.

[0100] The input sub-circuit 111 is connected to the input terminal Input of the shift register circuit, the first node N1, and the second clock signal terminal CK, and is configured to electrically connect the input terminal Input and the first node N1 based on the signal of the second clock signal terminal CK.

[0101] The first control sub-circuit 112 is electrically connected to the fourth power supply signal terminal VGH, the second node N2, and the second clock signal terminal CK of the shift register circuit, and is configured to electrically connect the fourth power supply signal terminal VGH and the second node N2 based on the signal of the second clock signal terminal CK.

[0102] The output sub-circuit 113 is electrically connected to the third node N3, the third clock signal terminal CB, and the output terminal Output of the shift register circuit, and is configured to output the signal of the third clock signal terminal CB to the output terminal Output based on the signal of the third node N3.

[0103] Specifically, the input sub-circuit 111 includes a second transistor M02. The first electrode of the second transistor M02 is electrically connected to the input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the second clock signal terminal CK. When the second clock signal terminal CK is connected to a high-level signal, the second transistor M02 is turned on, and the signal of the input terminal Input is input to the first node N1.

[0104] Specifically, the first control sub-circuit 112 includes a third transistor M03. The first electrode of the third transistor M03 is electrically connected to the fourth power supply signal terminal VGH, the second electrode is electrically connected to the second node N2, and the control terminal is electrically connected to the second clock signal terminal CK. In response to a high-level signal being applied to the second clock signal terminal CK, the third transistor M03 is turned on, inputting the potential of the fourth power supply signal terminal VGH to the second node N2.

[0105] The output sub-circuit 113 includes a fourth transistor M04 and a second capacitor C2. The first electrode of the fourth transistor M04 is electrically connected to the third clock signal terminal CB, the second electrode is electrically connected to the output terminal Output, and the control electrode is electrically connected to the third node N3. The first electrode of the second capacitor C2 is electrically connected to the third node N3, and the second electrode is electrically connected to the output terminal Output. In response to the high level of the third node N3, the fourth transistor M04 is turned on and transmits the signal connected to the third clock signal terminal CB to the output terminal Output. In addition, the second capacitor C2 is used to maintain the potential of the control electrode of the fourth transistor M04.

[0106] Optionally, the shift register circuit also includes an output control sub-circuit 114 electrically connected to the second node N2, the fifth power supply signal terminal VGL, and the output terminal Output, configured to electrically connect the fifth power supply signal terminal VGL to the output terminal Output of the shift register circuit based on the signal of the second node N2.

[0107] The output control sub-circuit 114 includes a fifth transistor M05 and a third capacitor C3. The first electrode of the fifth transistor M05 is electrically connected to the output terminal Output, the second electrode is electrically connected to the fifth power supply signal terminal VGL, and the control electrode is electrically connected to the second node N2. The first electrode of the third capacitor C3 is electrically connected to the second node N2, and the second electrode is electrically connected to the fifth power supply signal terminal VGL. In response to the high level of the second node N2, the fifth transistor M05 is turned on and transmits the signal connected to the fifth power supply signal terminal VGL to the output terminal Output. In addition, the third capacitor C3 is used to maintain the potential of the control electrode of the fifth transistor M05.

[0108] Optionally, the shift register further includes a second control sub-circuit 115, electrically connected to the third clock signal terminal CB, the fifth power supply signal terminal VGL, the second node N2, and the first node N1, configured to electrically connect the fifth power supply signal terminal VGL to the second node N2 based on the signals of the third clock signal terminal CB and the first node N1.

[0109] Specifically, the second control sub-circuit 115 may include a sixth transistor M06 and a seventh transistor M07. The first electrode of the sixth transistor M06 is electrically connected to the first node N1, the second electrode is electrically connected to the first electrode of the seventh transistor M07, and the control electrode is electrically connected to the third clock signal terminal CB. The second electrode of the seventh transistor M07 is electrically connected to the fifth power supply signal terminal VGL, and the control electrode is electrically connected to the second node N2. When the signal at the third clock signal terminal CB is high, the sixth transistor M06 is turned on, transferring the potential of the first node N1 to the fourth node N4. When the potential at the second node N2 is high, the seventh transistor M07 is turned on, transferring the potential of the fifth power supply signal terminal VGL to the fourth node N4. When both the sixth transistor M06 and the seventh transistor M07 are turned on, the potential of the fifth power supply signal terminal VGL is written to the first node N1.

[0110] Optionally, the shift register further includes a third control sub-circuit 116, which is electrically connected to the first node N1, the second node N2, and the second clock signal terminal CK, and configured to electrically connect the second clock signal terminal CK to the second node N2 based on the signal from the first node N1. The third control sub-circuit includes an eighth transistor M08, which is turned on in response to the first node N1 being high, and writes the signal from the second clock signal terminal CK into the second node N2.

[0111] Optionally, the shift register also includes a voltage regulator circuit composed of the ninth transistor M09. Under the potential of the fourth power supply signal terminal VGH, the ninth transistor M09 is continuously turned on, which can prevent leakage current from the third node N3 through the path of the second transistor M02 and the sixth transistor M06, reduce the stress of the third node N3 on the first node N1, and help stabilize the voltage of the third node N3, making it less prone to fluctuation, so that the fourth transistor M04, which serves as the output transistor, can be fully turned on.

[0112] In this shift register circuit, there is a partial overlap between the active level period of the second clock signal terminal CK and the inactive level period of the clock signal connected to the third clock signal terminal CB.

[0113] It should be noted that this disclosure is not intended to limit the specific function of the shift register circuit to this; other circuits with similar main frame structures that can satisfy the function of the shift register circuit are all protected by this disclosure.

[0114] It should also be noted that, Figure 7 and Figure 8The examples shown are intended only to illustrate two typical architectures of transistors that can use IGZO materials. Those skilled in the art should understand that when the structure of IGZO material transistors (i.e., metal oxide thin film transistors) is not required, the transistors in the above circuits can also be P-type transistors. In this case, it is only necessary to reverse the power supply polarity in the circuit and simply adjust the signal polarity, which will not be elaborated upon in this article.

[0115] Based on the same inventive concept, embodiments of this disclosure also provide a display device, including the display panel described in the above embodiments.

[0116] Since the display panel included in the display device provided in this embodiment corresponds to the display panel provided in the above embodiments, the previous embodiments are also applicable to this embodiment, and will not be described in detail in this embodiment.

[0117] In this embodiment, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, in-vehicle display, digital photo frame, or navigator. In particular, long strip-shaped electronic paper display products with a large aspect ratio can achieve a uniform display effect with lower cost, narrower bezels, and lower refresh interval crosstalk by loading the above display panel, which has broad application prospects.

[0118] It is obvious that the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. All obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A display panel, characterized in that, include: The display area includes a display area and a non-display area. The non-display area includes a gate driving circuit and a selection circuit. The display area includes N refresh areas. The gate driving circuit includes N gate driving sub-circuits, each of which includes multiple cascaded shift register circuits. The shift register circuits provide scan signals to the pixel circuits of the corresponding rows in the display area. The selection circuit includes N selection sub-circuits. The selection sub-circuit includes a first power signal terminal, an output terminal, and at least two selection terminals. The first power signal terminal is electrically connected to a first power line, and the output terminal is electrically connected to the input terminal of the first-stage shift register circuit of the gate drive sub-circuit corresponding to the selection sub-circuit. The at least two selection terminals are respectively electrically connected to selection signal lines, and are configured to electrically connect the first power signal terminal and the output terminal based on the signals connected to the at least two selection terminals being at an effective level. Where N is an integer greater than or equal to 2.

2. The display panel according to claim 1, characterized in that, The selection sub-circuit includes M selection switches connected in series. The first terminal of the (n+1)th selection switch is electrically connected to the second terminal of the nth selection switch. The first terminal of the first selection switch is electrically connected to the first power signal terminal. The second terminal of the Mth selection switch is electrically connected to the output terminal of the selection sub-circuit. The control terminals of the M selection switches are respectively electrically connected to at least two selection terminals. Where n is an integer greater than or equal to 1 and less than M, and M is an integer greater than or equal to 2.

3. The display panel according to claim 2, characterized in that, All M selection switches are either N-type transistors or P-type transistors.

4. The display panel according to claim 2, characterized in that, The display panel includes K selection signal lines, where K satisfies: .

5. The display panel according to claim 1, characterized in that, The shift register circuit includes: an input sub-circuit, a pull-up sub-circuit, a pull-down control sub-circuit, and a pull-down circuit. The input sub-circuit is electrically connected between the input terminal of the shift register circuit and the pull-up node, and is configured to transmit a valid level signal to the pull-up node based on the signal at the input terminal of the shift register circuit. The pull-up sub-circuit is electrically connected to the first clock signal terminal, the output terminal of the shift register circuit, and the pull-up node, and is configured to electrically connect the first clock signal terminal and the output terminal based on the signal from the pull-up node. The pull-down control sub-circuit is electrically connected between the second power signal terminal and the first pull-down node, and is configured to electrically connect the second power signal terminal and the first pull-down node based on a first power signal from the second power signal terminal. The pull-down sub-circuit is electrically connected to the first pull-down node, the third power signal terminal, and the pull-up node, and is configured to electrically connect the third power signal terminal to the first pull-down node based on the signal from the pull-up node.

6. The display panel according to claim 1, characterized in that, The shift register circuit includes: an input sub-circuit, a first control sub-circuit, and an output sub-circuit. An input sub-circuit is electrically connected to the input terminal of the shift register circuit, the first node, and the second clock signal terminal, and is configured to electrically connect the input terminal of the shift register circuit to the first node based on the signal from the second clock signal terminal. The first control sub-circuit is electrically connected to the fourth power signal terminal, the second node and the second clock signal terminal, and is configured to electrically connect the fourth power signal terminal and the second node based on the signal of the second clock signal terminal. An output sub-circuit is electrically connected to a third node, a third clock signal terminal, and an output terminal, and is configured to output the signal of the third clock signal terminal to the output terminal of the shift register circuit based on the signal of the third node. An output control sub-circuit is electrically connected to the second node, the fifth power signal terminal, and the output terminal, and is configured to electrically connect the fifth power signal terminal to the output terminal of the shift register circuit based on the signal from the second node.

7. The display panel according to claim 4 or 5, characterized in that, The first power signal terminal is connected to a high-level signal, and the transistor in the display panel is a metal-oxide-slim transistor.

8. The display panel according to claim 7, characterized in that, The transistors in the shift register circuit are N-type transistors, and the first power supply signal terminal is connected to a high-level signal.

9. The display panel according to claim 2, characterized in that, The selector circuit includes two selector switches.

10. A display device, characterized in that, The display panel includes any one of claims 1-9.

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