Solar cell and photovoltaic module
By setting tunneling passivation structures on both the front and back sides of the solar cell, the problem of high reverse saturation current density in the front metal region of existing TOPCon cells is solved, resulting in a significant improvement in cell efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 扬州阿特斯太阳能电池有限公司
- Filing Date
- 2025-04-25
- Publication Date
- 2026-05-12
AI Technical Summary
The existing TOPCon battery has a large reverse saturation current density in the front metal region, which limits the improvement of battery efficiency.
The double-sided TOPCon structure is adopted, with tunneling passivation structures on both the front and back sides, including tunneling layers and doped layers stacked in sequence with opposite doping types. Combined with different surface treatments such as polished surfaces and light-trapping textured surfaces, the metal contact is optimized.
This effectively reduces the reverse saturation current density and significantly improves the efficiency of solar cells.
Smart Images
Figure CN224234077U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of solar cell technology, specifically relating to a solar cell and a photovoltaic module. Background Technology
[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in both domestic and international photovoltaic markets are constantly increasing, and industry manufacturers are focusing on the research and development of high-efficiency cells. TOPCon (Tunnel Oxide Passivated Contact) cells improve the surface passivation performance of the cell by sequentially preparing an ultra-thin tunnel oxide layer and a doped polycrystalline silicon layer on the back of the cell, reducing the metal contact recombination current and effectively improving the open-circuit voltage and short-circuit current of the cell.
[0003] Existing TOPCon cells are typically single-sided TOPCon structures. The emitter is usually fabricated using a boron diffusion process on the front side. After the front metal electrode is set, it directly contacts the silicon substrate. The reverse saturation current density in the metal region is relatively large, which limits the improvement of cell efficiency.
[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content
[0005] The purpose of this invention is to provide a solar cell and photovoltaic module that can improve the reverse saturation current density in the metal region and improve the battery efficiency.
[0006] To achieve the above objectives, the technical solution provided by a specific embodiment of this utility model is as follows:
[0007] A solar cell, comprising:
[0008] A silicon substrate having a first surface and a second surface disposed opposite to each other;
[0009] A first tunneling passivation structure is located on the first surface. The first tunneling passivation structure includes a first tunneling layer and a first doped layer stacked sequentially. The doping type of the first doped layer is the same as the doping type of the silicon substrate.
[0010] The first electrode is located on the first surface and is in electrical contact with the first doped layer;
[0011] A second tunneling passivation structure is located on the second surface. The second tunneling passivation structure includes a second tunneling layer and a second doped layer stacked sequentially. The doping type of the second doped layer is opposite to the doping type of the silicon substrate.
[0012] The second electrode is located on the second surface and is in electrical contact with the second doped layer.
[0013] In one or more embodiments of this utility model, the first surface is a polished surface or a textured surface with a light-trapping structure; and / or,
[0014] The second surface is a polished surface.
[0015] In one or more embodiments of this utility model, the first surface is a polished surface; and / or,
[0016] The second surface is a polished surface or a textured surface with a light-trapping structure.
[0017] In one or more embodiments of the present invention, the first surface includes a first region and a second region spaced apart, and the first tunneling passivation structure is located in the first region.
[0018] In one or more embodiments of this utility model, the first region of the first surface is a polished surface or a textured surface with a light-trapping structure; and / or,
[0019] The second region of the first surface is a light-trapping textured surface.
[0020] In one or more embodiments of this utility model, both the first and second regions of the first surface are polished surfaces.
[0021] In one or more embodiments of the present invention, the first surface is recessed in the second region relative to the first region.
[0022] In one or more embodiments of the present invention, the second surface includes a third region and a fourth region spaced apart, and the second tunneling passivation structure is located in the third region.
[0023] In one or more embodiments of this utility model, the third and fourth regions of the second surface are both polished surfaces.
[0024] In one or more embodiments of this utility model, the third region of the second surface is a polished surface or a textured surface with a light-trapping structure; and / or,
[0025] The fourth region of the second surface is a light-trapping textured surface.
[0026] In one or more embodiments of the present invention, the second surface is recessed in the fourth region relative to the third region.
[0027] In one or more embodiments of this utility model, the first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,
[0028] The thickness of the first tunneling layer is 1.5 nm to 2.5 nm or 1.8 nm to 2.2 nm; and / or,
[0029] The first doped layer is a doped polycrystalline silicon layer with a thickness of 80nm~400nm or 200nm~300nm;
[0030] The second tunneling layer is any one or more combinations of silicon oxide layer and silicon oxynitride layer; and / or,
[0031] The thickness of the second tunneling layer is 1.5 nm to 2.5 nm or 1.8 nm to 2.2 nm; and / or,
[0032] The second doped layer is a doped polycrystalline silicon layer with a thickness of 80 nm to 400 nm or 200 nm to 300 nm; and / or,
[0033] The silicon substrate is an N-type silicon substrate, the first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer.
[0034] In one or more embodiments of the present invention, a first passivation layer is provided on the first surface, and a second passivation layer is provided on the second surface.
[0035] In one or more embodiments of this utility model, the first passivation layer comprises one or more layers selected from silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride; and / or,
[0036] The thickness of the first passivation layer is 3nm to 6nm; and / or,
[0037] The second passivation layer includes one or more of the following: a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
[0038] A photovoltaic module includes the aforementioned solar cell.
[0039] Compared with the prior art, the solar cell of this invention is a bifacial TOPCon cell with tunneling passivation structure on both the front and back sides, which ensures passivation contact between the front and back metal regions, effectively reduces the reverse saturation current density, and significantly improves the cell efficiency. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is a schematic diagram of the structure of the solar cell in Embodiment 1 of this utility model;
[0042] Figure 2 This is a schematic diagram of the structure of the solar cell in Embodiment 2 of this utility model;
[0043] Figure 3 This is a schematic diagram of the structure of the solar cell in Embodiment 3 of this utility model;
[0044] Figure 4 This is a schematic diagram of the structure of the solar cell in Embodiment 5 of this utility model. Detailed Implementation
[0045] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.
[0046] This invention discloses a solar cell, comprising:
[0047] A silicon substrate having a first surface and a second surface disposed opposite to each other;
[0048] The first tunneling passivation structure is located on the first surface. The first tunneling passivation structure includes a first tunneling layer and a first doped layer stacked sequentially. The doping type of the first doped layer is the same as the doping type of the silicon substrate.
[0049] The first electrode is located on the first surface and is in electrical contact with the first doped layer;
[0050] The second tunneling passivation structure is located on the second surface. The second tunneling passivation structure includes a second tunneling layer and a second doped layer stacked sequentially. The doping type of the second doped layer is opposite to the doping type of the silicon substrate.
[0051] The second electrode is located on the second surface and is in electrical contact with the second doped layer.
[0052] The first surface is the front side (main light-receiving surface) of the solar cell, and the second surface is the back side (secondary light-receiving surface) of the solar cell.
[0053] In one embodiment, the first surface is a textured surface with a light-trapping structure, and the second surface is a polished surface; or, the first surface is a polished surface, and the second surface is a textured surface with a light-trapping structure; or, the first surface is a polished surface, and the second surface is a polished surface.
[0054] In one embodiment, the first surface includes a first region and a second region spaced apart, and a first tunneling passivation structure is located in the first region; the first region of the first surface is a polished surface or a textured surface with a light-trapping structure, and the second region of the first surface is a textured surface with a light-trapping structure. Alternatively, the first surface includes a first region and a second region spaced apart, and a first tunneling passivation structure is located in the first region; both the first region and the second region of the first surface are polished surfaces.
[0055] In one embodiment, the first surface is recessed in the second region relative to the first region.
[0056] In one embodiment, the second surface includes a third region and a fourth region spaced apart, and the second tunneling passivation structure is located in the third region; both the third and fourth regions of the second surface are polished surfaces. Alternatively, the second surface includes a third region and a fourth region spaced apart, and the second tunneling passivation structure is located in the third region; the third region of the second surface is a polished surface or a textured surface with a light-trapping structure, and the fourth region of the second surface is a textured surface with a light-trapping structure.
[0057] In one embodiment, the second surface is recessed in the fourth region relative to the third region.
[0058] The solar cell of this invention is a bifacial TOPCon cell with tunneling passivation structures on both the front and back sides, ensuring passivation contact between the front and back metal regions, effectively reducing the reverse saturation current density, and significantly improving the cell efficiency.
[0059] The present invention will be further described below with reference to specific embodiments.
[0060] Example 1:
[0061] like Figure 1 As shown, in this embodiment, the solar cell is a bifacial TOPCon cell, including a silicon substrate 10. The silicon substrate 10 includes a first surface S1 and a second surface S2 disposed opposite to each other. The first surface S1 is the front side (i.e. the main light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e. the secondary light-receiving surface) of the silicon substrate 10.
[0062] In this embodiment, the silicon substrate 10 is an N-type silicon substrate. The first surface S1 of the silicon substrate 10 is a light-trapping textured surface, for example, a pyramidal light-trapping textured surface can be formed by alkaline texturing. The second surface S2 of the silicon substrate 10 is entirely polished, with a reflectivity of 45% to 55%.
[0063] In the above technical solution, the light-trapping structure of the main light-receiving surface can reduce the reflection of light from the main light-receiving surface, make better use of reflected light, improve light absorption, and improve battery conversion efficiency.
[0064] It is understood that in other embodiments, the first surface S1 of the silicon substrate 10 may also be a polished surface or a textured surface with poor light trapping effect. For example, a textured surface with a small pyramid structure or a polished surface with a pyramid base and poor light trapping effect can be formed by alkaline texturing and alkaline polishing.
[0065] In the bifacial TOPCon solar cell of this embodiment, a first tunneling passivation structure is provided on the first surface S1, and a second tunneling passivation structure is provided on the second surface S2. Specifically, the first tunneling passivation structure includes a first tunneling layer 21 and a first doped layer 31 sequentially stacked on the first surface S1. The doping type of the first doped layer 31 is the same as the doping type of the silicon substrate 10. The second tunneling passivation structure includes a second tunneling layer 22 and a second doped layer 32 sequentially stacked on the second surface S2. The doping type of the second doped layer 32 is opposite to the doping type of the silicon substrate 10.
[0066] In the above technical solution, by setting the PN junction on the secondary light-receiving surface and setting a second tunneling layer in the PN junction, metal recombination is reduced and metal contact is improved; combined with the setting of the light-trapping structure on the main light-receiving surface, light absorption can be further improved and the battery conversion efficiency can be improved.
[0067] In this embodiment, the first tunneling layer 21 is any one or more of silicon oxide layer, silicon oxynitride layer, etc., with a thickness of 1.5nm to 2.5nm, preferably 1.8nm to 2.2nm; the second tunneling layer 22 is any one or more of silicon oxide layer, silicon oxynitride layer, etc., with a thickness of 1.5nm to 2.5nm, preferably 1.8nm to 2.2nm.
[0068] In this embodiment, both the first doped layer 31 and the second doped layer 32 can be a single doped polysilicon layer or multiple doped polysilicon layers with a doping concentration gradient from the inside out (i.e., along the direction away from the silicon substrate). The thickness of the first doped layer 31 is 80 nm to 400 nm, preferably 200 nm to 300 nm; the thickness of the second doped layer 32 is 80 nm to 400 nm, preferably 200 nm to 300 nm. The first doped layer 31 is an N-type doped polysilicon layer, such as phosphorus doping; the second doped layer 32 is a P-type doped polysilicon layer, such as boron doping.
[0069] In this embodiment, a first passivation layer 51 covering a first tunneling passivation structure is provided on the first surface S1 of the silicon substrate 10, and a second passivation layer 52 covering a second tunneling passivation structure is provided on the second surface S2 of the silicon substrate 10. Both the first passivation layer 51 and the second passivation layer 52 may comprise one or more layers selected from silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride. The thickness of the first passivation layer is 3 nm to 6 nm.
[0070] The solar cell of this embodiment also includes a first electrode 41 and a second electrode 42. The first electrode 41 is located on the first surface S1 and is in electrical contact with the first doped layer 31 located below it, but does not damage the bottommost first tunneling layer 21, thus ensuring the tunneling function of the first tunneling layer 21. The second electrode 42 is located on the second surface S2 and is in electrical contact with the second doped layer 32 located below it, but does not damage the bottommost second tunneling layer 22, thus ensuring the tunneling function of the second tunneling layer 22.
[0071] Example 2:
[0072] like Figure 2 As shown, the solar cell in this embodiment is a bifacial TOPCon cell. The solar cell in this embodiment is structurally similar to the solar cell in Embodiment 1. The first surface S1 of the silicon substrate 10 is the front surface (i.e., the main light-receiving surface), and the second surface S2 is the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10. The difference between the solar cell in this embodiment and the solar cell in Embodiment 1 is that, in this embodiment, the entire first surface S1 of the silicon substrate 10 is polished, with a reflectivity of 45% to 55%. The second surface S2 of the silicon substrate 10 is a light-trapping textured surface; for example, a pyramidal light-trapping textured surface can be formed by alkaline texturing.
[0073] It is understood that in other embodiments, the second surface S2 of the silicon substrate 10 may also be a polished surface or a textured surface with poor light trapping effect. For example, a textured surface with a small pyramid structure or a polished surface with a pyramid base and poor light trapping effect can be formed by alkaline texturing and alkaline polishing.
[0074] Example 3:
[0075] like Figure 3 As shown, in this embodiment, the solar cell is a bifacial TOPCon cell, including a silicon substrate 10. The silicon substrate 10 includes a first surface S1 and a second surface S2 disposed opposite to each other. The first surface S1 includes a first region S11 and a second region S12 distributed at intervals. The first region S11 is a front metal region, and the second region S12 is a front non-metal region. The first surface S1 is the front side (i.e., the main light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10.
[0076] In this embodiment, the silicon substrate 10 is an N-type silicon substrate. The first region S11 of the first surface S1 of the silicon substrate 10 has a light-trapping textured surface, and the second region S12 of the first surface S1 of the silicon substrate 10 also has a light-trapping textured surface; for example, a pyramidal light-trapping textured surface can be formed by alkaline texturing. The entire second surface S2 of the silicon substrate 10 is polished, with a reflectivity of 45%–55%.
[0077] In the above technical solution, the light-trapping structure of the main light-receiving surface can reduce the reflection of light from the main light-receiving surface, make better use of reflected light, improve light absorption, and improve battery conversion efficiency.
[0078] It is understood that in other embodiments, the first region S11 of the first surface S1 of the silicon substrate 10 may also be a polished surface or a textured surface with poor light-trapping effect. For example, a small pyramidal textured surface or a polished surface with a pyramidal base and poor light-trapping effect can be formed by alkaline texturing and alkaline polishing. The second region S12 of the first surface S1 of the silicon substrate 10 is a textured surface with a light-trapping structure. For example, a pyramidal light-trapping textured surface can be formed by alkaline texturing. The entire second surface S2 of the silicon substrate 10 is a polished surface with a reflectivity of 45% to 55%.
[0079] In the bifacial TOPCon cell of this embodiment, the first surface S1 is provided with spaced-apart first tunneling passivation structures. The second surface S2 is provided with a full-surface second tunneling passivation structure. The spaced arrangement of the first tunneling passivation structures can increase the utilization rate of light on the main light-receiving surface, reduce parasitic absorption, and increase current.
[0080] Specifically, the first region S11 of the first surface S1 has a first tunneling passivation structure, while the second region S12 does not have a first tunneling passivation structure, and the first surface S1 is recessed relative to the first region S11 in the second region S12 (not shown in the figure). The greater the depth of the recess, the larger the light-receiving area on the front of the solar cell, thereby further improving the cell efficiency.
[0081] Specifically, the first tunneling passivation structure includes a first tunneling layer 21 and a first doped layer 31 sequentially stacked on the first surface S1. The doping type of the first doped layer 31 is the same as that of the silicon substrate 10. The second tunneling passivation structure includes a second tunneling layer 22 and a second doped layer 32 sequentially stacked on the second surface S2. The doping type of the second doped layer 32 is opposite to that of the silicon substrate 10.
[0082] In the above technical solution, by setting the PN junction on the secondary light-receiving surface and setting a second tunneling layer in the PN junction, metal recombination is reduced and metal contact is improved; combined with the setting of the light-trapping structure on the main light-receiving surface, light absorption can be further improved and the battery conversion efficiency can be improved.
[0083] In this embodiment, the first tunneling layer 21 is any one or more of silicon oxide layer, silicon oxynitride layer, etc., with a thickness of 1.5nm to 2.5nm, preferably 1.8nm to 2.2nm; the second tunneling layer 22 is any one or more of silicon oxide layer, silicon oxynitride layer, etc., with a thickness of 1.5nm to 2.5nm, preferably 1.8nm to 2.2nm.
[0084] In this embodiment, both the first doped layer 31 and the second doped layer 32 can be a single doped polysilicon layer or multiple doped polysilicon layers with a doping concentration gradient from the inside out (i.e., along the direction away from the silicon substrate). The thickness of the first doped layer 31 is 80 nm to 400 nm, preferably 200 nm to 300 nm; the thickness of the second doped layer 32 is 80 nm to 400 nm, preferably 200 nm to 300 nm. The first doped layer 31 is an N-type doped polysilicon layer, such as phosphorus doping; the second doped layer 32 is a P-type doped polysilicon layer, such as boron doping.
[0085] In this embodiment, a first passivation layer 51 covering the first tunneling passivation structure and the second region S12 is provided on the first surface S1 of the silicon substrate 10, and a second passivation layer 52 covering the second tunneling passivation structure is provided on the second surface S2 of the silicon substrate 10. Both the first passivation layer 51 and the second passivation layer 52 may include one or more layers selected from silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride. The thickness of the first passivation layer is 3 nm to 6 nm.
[0086] The solar cell of this embodiment also includes a first electrode 41 and a second electrode 42. The first electrode 41 is located in a first region S11 of the first surface S1 and is in electrical contact with the first doped layer 31 located below it, but does not damage the bottom first tunneling layer 21, ensuring the tunneling function of the first tunneling layer 21. The first electrode 41 is distributed directly above the first region S11, and the projection of the first electrode 41 on the first surface S1 is within the first region S11. The second electrode 42 is located on the second surface S2 and is in electrical contact with the second doped layer 32 located below it, but does not damage the bottom second tunneling layer 22, ensuring the tunneling function of the second tunneling layer 22.
[0087] Example 4:
[0088] In this embodiment, the solar cell is a bifacial TOPCon cell. The solar cell in this embodiment is structurally similar to the solar cell in Embodiment 3. The first surface S1 of the silicon substrate 10 is the front side (i.e., the main light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10. The difference between this solar cell and the solar cell in Embodiment 3 is that in this embodiment, the first region S11 and the second region S12 of the first surface S1 of the silicon substrate 10 are both polished surfaces with a reflectivity of 45% to 55%. The second surface S2 of the silicon substrate 10 is a light-trapping textured surface; for example, a pyramidal light-trapping textured surface can be formed by alkaline texturing.
[0089] Example 5:
[0090] like Figure 4 As shown, in this embodiment, the solar cell is a bifacial TOPCon cell, including a silicon substrate 10. The silicon substrate 10 includes a first surface S1 and a second surface S2 disposed opposite to each other. The first surface S1 includes a first region S11 and a second region S12 spaced apart, where the first region S11 is a front-side metallic region and the second region S12 is a front-side non-metallic region. The second surface S2 includes a third region S21 and a fourth region S22 spaced apart, where the third region S21 is a back-side metallic region and the fourth region S22 is a back-side non-metallic region. The first surface S1 is the front side (i.e., the main light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10.
[0091] In this embodiment, the silicon substrate 10 is an N-type silicon substrate. The first region S11 of the first surface S1 of the silicon substrate 10 has a light-trapping textured surface, and the second region S12 of the first surface S1 of the silicon substrate 10 also has a light-trapping textured surface; for example, a pyramidal light-trapping textured surface can be formed by alkaline texturing. The entire second surface S2 of the silicon substrate 10 is polished, with a reflectivity of 45%–55%.
[0092] In the above technical solution, the light-trapping structure of the main light-receiving surface can reduce the reflection of light from the main light-receiving surface, make better use of reflected light, improve light absorption, and improve battery conversion efficiency.
[0093] The third region S21 and the fourth region S22 of the second surface S2 of the silicon substrate 10 are both polished surfaces with a reflectivity of 45% to 55%.
[0094] It is understood that in other embodiments, the first region S11 of the first surface S1 of the silicon substrate 10 may also be a polished surface or a textured surface with poor light-trapping effect. For example, a textured surface with a small pyramid structure or a polished surface with a pyramid base and poor light-trapping effect can be formed by alkaline texturing and alkaline polishing. The second region S12 of the first surface S1 of the silicon substrate 10 is a textured surface with a light-trapping structure. For example, a pyramidal light-trapping structure textured surface can be formed by alkaline texturing.
[0095] In the bifacial TOPCon battery of this embodiment, a first tunneling passivation structure is provided on the first surface S1 at intervals. The interval arrangement of the first tunneling passivation structure can increase the utilization rate of light on the main light-receiving surface, reduce parasitic absorption, and increase current. A second tunneling passivation structure is provided on the second surface S2 at intervals. The interval arrangement of the second tunneling passivation structure can increase the utilization rate of light on the secondary light-receiving surface, reduce parasitic absorption, and increase current.
[0096] Specifically, the first region S11 of the first surface S1 has a first tunneling passivation structure, while the second region S12 does not have a first tunneling passivation structure, and the first surface S1 is recessed relative to the first region S11 in the second region S12 (not shown in the figure). The greater the depth of the recess, the larger the light-receiving area on the front of the solar cell, thereby further improving the cell efficiency.
[0097] The second surface S2 has a second tunneling passivation structure in the third region S21, while it does not have a second tunneling passivation structure in the fourth region S22. The second surface S2 is recessed relative to the third region S21 in the fourth region S22 (not shown in the figure). The greater the depth of the recess, the larger the light-receiving area on the front of the solar cell, thereby further improving the cell efficiency.
[0098] Specifically, the first tunneling passivation structure includes a first tunneling layer 21 and a first doped layer 31 sequentially stacked on the first surface S1. The doping type of the first doped layer 31 is the same as that of the silicon substrate 10. The second tunneling passivation structure includes a second tunneling layer 22 and a second doped layer 32 sequentially stacked on the second surface S2. The doping type of the second doped layer 32 is opposite to that of the silicon substrate 10.
[0099] In the above technical solution, by setting the PN junction on the secondary light-receiving surface and setting a second tunneling layer in the PN junction, metal recombination is reduced and metal contact is improved; combined with the setting of the light-trapping structure on the main light-receiving surface, light absorption can be further improved and the battery conversion efficiency can be improved.
[0100] In this embodiment, the first tunneling layer 21 is any one or more of silicon oxide layer, silicon oxynitride layer, etc., with a thickness of 1.5nm to 2.5nm, preferably 1.8nm to 2.2nm; the second tunneling layer 22 is any one or more of silicon oxide layer, silicon oxynitride layer, etc., with a thickness of 1.5nm to 2.5nm, preferably 1.8nm to 2.2nm.
[0101] In this embodiment, both the first doped layer 31 and the second doped layer 32 can be a single doped polysilicon layer or multiple doped polysilicon layers with a doping concentration gradient from the inside out (i.e., along the direction away from the silicon substrate). The thickness of the first doped layer 31 is 80 nm to 400 nm, preferably 200 nm to 300 nm; the thickness of the second doped layer 32 is 80 nm to 400 nm, preferably 200 nm to 300 nm. The first doped layer 31 is an N-type doped polysilicon layer, such as phosphorus doping; the second doped layer 32 is a P-type doped polysilicon layer, such as boron doping.
[0102] In this embodiment, a first passivation layer 51 covering the first tunneling passivation structure and the second region S12 is provided on the first surface S1 of the silicon substrate 10, and a second passivation layer 52 covering the second tunneling passivation structure is provided on the second surface S2 of the silicon substrate 10. Both the first passivation layer 51 and the second passivation layer 52 may include one or more layers selected from silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride. The thickness of the first passivation layer is 3 nm to 6 nm.
[0103] The solar cell of this embodiment also includes a first electrode 41 and a second electrode 42. The first electrode 41 is located in a first region S11 of the first surface S1 and is in electrical contact with the first doped layer 31 located below it, but does not damage the bottommost first tunneling layer 21, ensuring the tunneling function of the first tunneling layer 21. The first electrode 41 is distributed directly above the first region S11, and the projection of the first electrode 41 on the first surface S1 is within the first region S11. The second electrode 42 is located in a third region S21 of the second surface S2 and is in electrical contact with the second doped layer 32 located below it, but does not damage the bottommost second tunneling layer 22, ensuring the tunneling function of the second tunneling layer 22. The second electrode 42 is distributed directly above the third region S21, and the projection of the second electrode 42 on the second surface S2 is within the third region S21.
[0104] The method for preparing the solar cell in this embodiment specifically includes the following steps:
[0105] 1. Double-sided polishing
[0106] A silicon substrate 10 is provided, comprising a first surface S1 and a second surface S2 disposed opposite to each other. The first surface S1 includes a first region S11 and a second region S12 spaced apart, wherein the first region S11 is a front-side metal region and the second region S12 is a front-side non-metal region. The second surface S2 includes a third region S21 and a fourth region S22 spaced apart, wherein the third region S21 is a back-side metal region and the fourth region S22 is a back-side non-metal region. The first surface S1 is the front side (i.e., the primary light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10.
[0107] In this embodiment, the silicon substrate 10 is an N-type silicon substrate. An alkaline polishing process is used to polish the first surface S1 and the second surface S2 of the silicon substrate 10 to form a polished surface with a reflectivity of 45% to 55%. The alkaline polishing solution may contain NaOH, KOH, TMAH, etc.
[0108] 2. Preparation of the first tunneling passivation structure
[0109] A first tunneling layer 21 and a first doped layer 31 are sequentially stacked in a first region S11 of the first surface S1. Specifically, the process includes the following steps:
[0110] A first tunneling layer 21 and a first intrinsic layer are deposited on the first surface S1 using LPCVD (Low Pressure Chemical Vapor Deposition). A first mask layer is then deposited on the first intrinsic layer using PECVD (Plasma Enhanced Chemical Vapor Deposition). The thickness is 20 nm to 100 nm, preferably 20 nm to 50 nm.
[0111] A laser process is used to pattern the first mask layer of the second region S12, exposing the first intrinsic layer of the second region S12. The patterned area is the area for printing electrode gate lines.
[0112] The first intrinsic layer and the first tunneling layer 21 of the second region S12 are removed by wet etching process to expose the silicon substrate 10 of the second region S12. Then, alkaline texturing is performed to form a textured surface with a pyramid light trapping structure in the second region S12. Finally, the first mask layer 61 of the first region S11 is removed to expose the first intrinsic layer of the first region S11, while removing the silicon oxide formed on the surface during the deposition process.
[0113] 3. Front diffusion process
[0114] A high-temperature phosphorus diffusion process is used to diffuse the first surface S1 and the first intrinsic layer of the silicon substrate 10, so that the first intrinsic layer is transformed into a first doped layer 31 and an N+ region is formed in the substrate of the second region S12. The diffusion temperature is 800℃~1200℃, preferably 800℃~1000℃.
[0115] 4. Backside enlargement and backside etching
[0116] The winding layer generated on the second surface S2 of the silicon substrate 10 during the diffusion process is removed by using an acid solution (such as HF solution) via a chain machine. Taking the phosphorus diffusion process as an example, the winding layer is phosphosilicate glass (PSG).
[0117] 5. Preparation of the second tunneling passivation structure
[0118] A second tunneling layer 22 and a second doped layer 32 are sequentially stacked in the third region S21 of the second surface S2. Specifically, the process includes the following steps:
[0119] A second tunneling layer 22 and a second intrinsic layer are deposited on the second surface S1 using LPCVD (Low Pressure Chemical Vapor Deposition). A second mask layer is then deposited on the second intrinsic layer using PECVD (Plasma Enhanced Chemical Vapor Deposition). The thickness is 20 nm to 100 nm, preferably 20 nm to 50 nm.
[0120] A laser process is used to pattern the second mask layer of the fourth region S22, exposing the second intrinsic layer of the fourth region S22. The patterned area is the area for printing electrode gate lines.
[0121] The second intrinsic layer and the second tunneling layer 22 of the fourth region S22 are removed by wet etching process to expose the silicon substrate 10 of the fourth region S22, and the second mask layer of the third region S21 is removed to expose the second intrinsic layer of the third region S21.
[0122] The second mask layer on the front side is removed using an acid solution. The second intrinsic layer and second tunneling layer 22 of the fourth region S22 are removed using an alkaline etching process, and a portion of the silicon substrate in the fourth region S22 is etched, forming a groove in the fourth region S22 of the second surface S2. Due to the obstruction of the second mask layer, the second intrinsic layer beneath the third region S21 is not etched. The fourth region S22 on the second surface S2 is polished using an alkaline polishing process. The second mask layer on the back side is removed using an acid solution, simultaneously removing the silicon oxide formed on the surface during the deposition process.
[0123] 6. Backside diffusion process
[0124] A high-temperature boron diffusion process is used to diffuse the second surface S2 and the second intrinsic layer of the silicon substrate 10, transforming the second intrinsic layer into a second doped layer 32, thereby generating a PN junction. The diffusion temperature is 800℃~1200℃, preferably 800℃~1000℃.
[0125] 7. Remove the wrapping and expand
[0126] An acid solution is used to remove the front-side BSG coating and to remove the front and back silicon oxides (BSG & PSG).
[0127] 8. Double-sided passivation
[0128] Al₂O₃ passivation layers were prepared on the first surface S1 and the second surface S2 using ALD (Atomic Layer Deposition). SiN₂ was then prepared on the Al₂O₃ passivation layers on the first surface S1 and the second surface S2 using PECVD (Plasma Enhanced Chemical Vapor Deposition). X Passivation layer.
[0129] 9. Preparation of metal electrodes
[0130] A first electrode 41 in contact with the first doped layer 31 is prepared in a first region S11 of the first surface S1, and a second electrode 42 in contact with the second doped layer 32 is prepared in a third region S21 of the second surface S2.
[0131] In this embodiment, both the first electrode 41 and the second electrode 42 are silver grid line electrodes.
[0132] 10. LIF process
[0133] Using LIF (Laser Induced Firing) process to sinter the electrodes can increase the contact between the electrodes and the doped layer, and significantly reduce the contact resistance between the metal and the doped layer.
[0134] Example 6:
[0135] In this embodiment, the solar cell is a bifacial TOPCon cell. The solar cell in this embodiment is structurally similar to the solar cell in Embodiment 5. The first surface S1 of the silicon substrate 10 is the front side (i.e., the main light-receiving surface), and the second surface S2 is the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10. The difference between this embodiment and the solar cell in Embodiment 5 is that in this embodiment, the first region S11 and the second region S12 of the first surface S1 of the silicon substrate 10 are both polished surfaces with a reflectivity of 45%–55%. The third region S21 of the second surface S2 of the silicon substrate 10 is a light-trapping textured surface, and the fourth region of the second surface S2 of the silicon substrate 10 is also a light-trapping textured surface. For example, a pyramidal light-trapping textured surface can be formed by alkaline texturing.
[0136] Alternatively, in this embodiment, both the first region S11 and the second region S12 of the first surface S1 of the silicon substrate 10 are polished surfaces with a reflectivity of 45% to 55%. The third region S21 of the second surface S2 of the silicon substrate 10 is a polished surface or a textured surface with poor light-trapping effect. For example, it can be formed by alkaline texturing and alkaline polishing to create a small pyramid structure textured surface or a polished surface with a pyramid base and poor light-trapping effect. The fourth region S22 of the second surface S2 of the silicon substrate 10 is a textured surface with a light-trapping structure. For example, it can be formed by alkaline texturing to create a pyramid light-trapping structure textured surface.
[0137] Example 7:
[0138] In this embodiment, the solar cell is a bifacial TOPCon cell. The solar cell in this embodiment is structurally similar to the solar cell in Embodiment 6. The first surface S1 of the silicon substrate 10 is the front side (i.e., the main light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10. The difference between the solar cell in this embodiment and the solar cell in Embodiment 6 is that, in this embodiment, the third region S21 and the fourth region S22 of the second surface S2 of the silicon substrate 10 are both polished surfaces with a reflectivity of 45% to 55%.
[0139] The polished surface of the second surface S2 results in smaller composite material and improved battery efficiency.
[0140] This invention also provides a photovoltaic module equipped with the aforementioned solar cells.
[0141] Compared with the prior art, the solar cell of this invention is a bifacial TOPCon cell with tunneling passivation structure on both the front and back sides, which ensures passivation contact between the front and back metal regions, effectively reduces the reverse saturation current density, and significantly improves the cell efficiency.
[0142] The solar cell of this invention is a bifacial TOPCon cell, with the PN junction located on the back of the cell and a second tunneling layer added, which can improve metal contact and reduce reverse saturation current density.
[0143] The solar cell of this invention is a bifacial TOPCon cell. It has a Poly-finger structure with tunneling passivation contacts only in the metal region, which increases light utilization, reduces parasitic absorption in the second region on the front and the fourth region on the back, and improves current.
[0144] The solar cell of this invention is a bifacial TOPCon cell. The back side can adopt a textured structure, which has a larger area and is more conducive to separating electron-hole pairs, thereby improving the cell efficiency.
[0145] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0146] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A solar cell, characterized in that, include: A silicon substrate having a first surface and a second surface disposed opposite to each other; A first tunneling passivation structure is located on the first surface. The first tunneling passivation structure includes a first tunneling layer and a first doped layer stacked sequentially. The doping type of the first doped layer is the same as the doping type of the silicon substrate. The first electrode is located on the first surface and is in electrical contact with the first doped layer; A second tunneling passivation structure is located on the second surface. The second tunneling passivation structure includes a second tunneling layer and a second doped layer stacked sequentially. The doping type of the second doped layer is opposite to the doping type of the silicon substrate. The second electrode is located on the second surface and is in electrical contact with the second doped layer.
2. The solar cell according to claim 1, characterized in that, The first surface is a polished surface or a textured surface with a light-trapping structure; and / or, The second surface is a polished surface.
3. The solar cell according to claim 1, characterized in that, The first surface is a polished surface; and / or, The second surface is a polished surface or a textured surface with a light-trapping structure.
4. The solar cell according to claim 1, characterized in that, The first surface includes a first region and a second region spaced apart, and the first tunneling passivation structure is located in the first region.
5. The solar cell according to claim 4, characterized in that, The first region of the first surface is a polished surface or a textured surface with a light-trapping structure; and / or, The second region of the first surface is a light-trapping textured surface.
6. The solar cell according to claim 4, characterized in that, Both the first and second regions of the first surface are polished surfaces.
7. The solar cell according to claim 4, characterized in that, The first surface is recessed in the second region relative to the first region.
8. The solar cell according to claim 1, characterized in that, The second surface includes a third region and a fourth region spaced apart, and the second tunneling passivation structure is located in the third region.
9. The solar cell according to claim 8, characterized in that, The third and fourth regions of the second surface are both polished surfaces.
10. The solar cell according to claim 8, characterized in that, The third region of the second surface is a polished surface or a textured surface with a light-trapping structure; and / or, The fourth region of the second surface is a light-trapping textured surface.
11. The solar cell according to claim 8, characterized in that, The second surface is recessed in the fourth region relative to the third region.
12. The solar cell according to claim 1, characterized in that, The first tunneling layer is any one or more combinations of silicon oxide layer and silicon oxynitride layer; and / or, The thickness of the first tunneling layer is 1.5 nm to 2.5 nm or 1.8 nm to 2.2 nm; and / or, The first doped layer is a doped polycrystalline silicon layer with a thickness of 80nm~400nm or 200nm~300nm; The second tunneling layer is any one or more combinations of silicon oxide layer and silicon oxynitride layer; and / or, The thickness of the second tunneling layer is 1.5 nm to 2.5 nm or 1.8 nm to 2.2 nm; and / or, The second doped layer is a doped polycrystalline silicon layer with a thickness of 80 nm to 400 nm or 200 nm to 300 nm; and / or, The silicon substrate is an N-type silicon substrate, the first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer.
13. The solar cell according to claim 1, characterized in that, A first passivation layer is provided on the first surface, and a second passivation layer is provided on the second surface.
14. The solar cell according to claim 13, characterized in that, The first passivation layer comprises one or more layers selected from silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride; and / or, The thickness of the first passivation layer is 3nm to 6nm; and / or, The second passivation layer includes one or more of the following: a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
15. A photovoltaic module, characterized in that, Including the solar cell as described in any one of claims 1 to 14.