Solar cell and photovoltaic module

Abstract

The utility model discloses a solar cell and a photovoltaic assembly, the solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface which are oppositely arranged, the second surface comprises a first area and a second area which are distributed at an interval, the first area is provided with a tunneling passivation contact structure, and the second area is provided with a second passivation contact structure. A first suede structure is formed on the surface of the silicon substrate in the first area, a second suede structure is formed on the surface of the silicon substrate in the second area, and the specific surface area of the second suede structure is smaller than that of the first suede structure. According to the utility model, the textured structures with different specific surface areas are formed in different areas of the back surface of the silicon substrate, so that the contact performance of the back electrode can be ensured, the passivation performance and the double-sided rate are considered, and the cell efficiency can be remarkably improved by optimizing the back surface structure.

Description

Technical Field

[0001] This utility model belongs to the field of solar cell technology, specifically relating to a solar cell and a photovoltaic module. Background Technology

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in both domestic and international photovoltaic markets are constantly increasing, prompting industry manufacturers to focus on the research and development of high-efficiency cells. TOPCon (Tunnel Oxide Passivated Contact) cells improve surface passivation performance and reduce metal contact recombination current by sequentially fabricating an ultrathin tunnel oxide layer and a doped polycrystalline silicon layer on the back of a silicon substrate, effectively increasing the cell's open-circuit voltage and short-circuit current. In recent years, the market share of TOPCon cells has risen rapidly, gradually surpassing PERC cells to become the mainstream technology for solar cells.

[0003] The back of the TOPCon cell uses a tunneling oxide layer and a doped polysilicon layer to form a tunneling passivation structure, which significantly improves the cell efficiency. The thicker the doped polysilicon on the back, the larger the window for resistance to metal paste burn-through, but the higher the parasitic absorption. Therefore, one of the solutions to improve the efficiency of TOPCon cells is the back SE (Selective Emitter) structure, which reduces the parasitic absorption in the long wavelength band on the back by reducing the thickness of the doped polysilicon in the non-metallic region.

[0004] In existing solar cells with a back-side SE structure, in order to reduce parasitic absorption on the back side and improve the back-side passivation performance, the back side of the silicon substrate is usually alkaline polished to form a polished surface. However, the contact performance under the metal region electrode is poor, the contact resistivity of the electrode is large, and the bifaciality is low, which limits the improvement of cell efficiency.

[0005] Therefore, in order to address the aforementioned technical problems, it is necessary to provide a solar cell and a photovoltaic module. Utility Model Content

[0006] The purpose of this invention is to provide a solar cell and photovoltaic module that improves bifaciality and cell efficiency while taking into account both metal contact performance and passivation performance.

[0007] To achieve the above objectives, the technical solution provided by an embodiment of this utility model is as follows:

[0008] A solar cell includes a silicon substrate, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including a first region and a second region spaced apart, the first region having a tunneling passivation contact structure, the silicon substrate surface of the first region having a first textured structure, the silicon substrate surface of the second region having a second textured structure, and the specific surface area of ​​the second textured structure being smaller than the specific surface area of ​​the first textured structure.

[0009] In one embodiment, the specific surface area of ​​the first velvet structure is greater than or equal to 1.1 and less than or equal to 1.5; and / or,

[0010] The specific surface area of ​​the second velvet structure is greater than 1 and less than or equal to 1.1.

[0011] In one embodiment, both the first and second velvet structures are pyramidal velvet structures.

[0012] In one embodiment, the average size of the pyramids in the first velvet structure is larger than the average size of the pyramids in the second velvet structure; and / or,

[0013] The density of the pyramids in the first velvet structure is less than the density of the pyramids in the second velvet structure.

[0014] In one embodiment, the width of the pyramid in the first velvet structure is 0.1 μm to 5 μm, the height is 0.1 μm to 5 μm, and the density is 5E4mm. -2 ~2E5mm -2 ; and / or,

[0015] In the second velvet structure, the width of the pyramids ranges from 0.1 μm to 2 μm, the height ranges from 0.1 μm to 2 μm, and the density is 5E4mm. -2 ~2.5E5mm -2 .

[0016] In one embodiment, the width of the first region is 20 μm to 600 μm; and / or,

[0017] The area of ​​the first region accounts for 5% to 10% of the total area of ​​the second surface.

[0018] In one embodiment, the second surface of the silicon substrate is recessed in the second region.

[0019] In one embodiment, the tunneling passivation contact structure includes a tunneling layer in direct contact with the silicon substrate and a second doped layer disposed on the tunneling layer. The doping type of the second doped layer is the same as that of the silicon substrate. The first region is provided with a second electrode in contact with the second doped layer.

[0020] In one embodiment, a second passivation layer and / or a second antireflection layer are stacked on the tunneling passivation contact structure in the first region and / or the second textured structure in the second region.

[0021] In one embodiment, a first doped layer and a first electrode are formed on a first surface of the silicon substrate, wherein the doping type of the first doped layer is opposite to the doping type of the silicon substrate, and the first electrode is in contact with the first doped layer.

[0022] In one embodiment, a first passivation layer and / or a first antireflection layer are stacked on the first doped layer.

[0023] The technical solution provided by one embodiment of this utility model is as follows:

[0024] A photovoltaic module comprising the aforementioned solar cell.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] This invention forms textured structures with different specific surface areas in different regions on the back side of a silicon substrate. The first region uses a textured structure with a larger specific surface area to ensure the contact performance of the back electrode, while the second region uses a textured structure with a smaller specific surface area to balance passivation performance and bifaciality. By optimizing the back structure, the battery efficiency can be significantly improved. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of the solar cell in Embodiment 1 of this utility model;

[0029] Figure 2 for Figure 1 A schematic diagram of the local structure at point A in the middle;

[0030] Figures 3a-3m This is a flowchart illustrating the fabrication process of the solar cell in Embodiment 1 of this utility model;

[0031] Figure 4 This is a planar schematic diagram of the second surface of the silicon substrate in Embodiment 1 of this utility model;

[0032] Figure 5 This is a schematic diagram of the structure of the solar cell in Comparative Example 1 of this utility model.

[0033] Explanation of key figure labels:

[0034] 10-Substrate, 11-First doped layer, 12-Tunneling layer, 13-Second doped layer, 14-Mask layer, 21-First passivation layer, 31-First antireflection layer, 22-Second passivation layer, 32-Second antireflection layer, 41-First electrode, 42-Second electrode, S1-First surface, S2-Second surface, S21-First region, S22-Second region, 101-First sub-region, 102-Second sub-region. Detailed Implementation

[0035] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0036] In this utility model, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0037] This utility model discloses a solar cell, including a silicon substrate. The silicon substrate includes a first surface and a second surface disposed opposite to each other. The second surface includes a first region and a second region distributed at intervals. A tunneling passivation contact structure is provided on the first region. A first textured structure is formed on the silicon substrate surface of the first region. A second textured structure is formed on the silicon substrate surface of the second region. The specific surface area of ​​the second textured structure is smaller than that of the first textured structure.

[0038] This invention forms textured structures with different specific surface areas in different regions on the back side of a silicon substrate. The first region uses a textured structure with a larger specific surface area to ensure the contact performance of the back electrode, while the second region uses a textured structure with a smaller specific surface area to balance passivation performance and bifaciality. By optimizing the back structure, the battery efficiency can be significantly improved.

[0039] In addition, only the first region on the back surface of the solar cell of the present utility model is laminated with a tunneling passivation contact structure, and there is no tunneling passivation contact structure on the second region, which can reduce the parasitic absorption on the back surface of the cell, significantly improve the current, and at the same time does not affect the contact performance of the back electrode, significantly improving the cell efficiency and bifacial ratio while increasing the process window.

[0040] The present utility model will be further described below in conjunction with specific embodiments.

[0041] Embodiment 1:

[0042] Refer Figure 1 、 Figure 2 As shown in the figure, it is a schematic structural diagram of the solar cell in this embodiment. The solar cell is a TOPCon cell, including a silicon substrate 10. The silicon substrate 10 includes a first surface S1 and a second surface S2 arranged opposite to each other. The second surface S2 includes a first region S21 and a second region S22 distributed at intervals. The first surface S1 is the front surface (i.e., the main light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10. The first region S11 is the front metal region, and the second region S12 is the front non-metal region. Of course, in other embodiments, the first surface S1 can also be the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10, the second surface S2 is the front surface (i.e., the main light-receiving surface) of the silicon substrate 10, the first region S11 is the back metal region, and the second region S12 is the back non-metal region.

[0043] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0044] On both the first surface S1 and the second surface S2 of the silicon substrate 10 in this embodiment of the solar cell, a textured structure for light trapping is formed. For example, a pyramid textured structure formed by alkaline texturing, but the textured structures on the two surfaces are different, which will be described in detail below.

[0045] On the first surface S1 of the silicon substrate 10, a pyramid textured structure is formed through a conventional alkaline texturing process. The pyramids in the pyramid textured structure are frustum-shaped, such as triangular frustum, quadrangular frustum, etc. Define the width of the pyramid as the bottom width of the frustum, and the height of the pyramid as the distance between the bottom and the top of the frustum. Then the average width of all pyramids is the average value of the widths of all pyramids, and the average height is the average value of the heights of all pyramids. Exemplarily, in this embodiment, the specific surface area of the textured structure on the first surface S1 is greater than or equal to 1.1 and less than or equal to 1.5, the width of the pyramid is 0.1 μm to 5 μm, the height is 0.1 μm to 5 μm, and the density is 5E4mm -2 ~2E5mm -2 .

[0046] A pyramidal textured structure is formed on the second surface S2 of the silicon substrate 10 through an alkaline texturing process, but the pyramidal textured structures in the first region S21 and the second region S22 are slightly different. The first region S21 and the second region S22 are respectively formed with a first textured structure and a second textured structure. Both the first textured structure and the second textured structure are pyramidal textured structures, but the specific surface area of ​​the second textured structure is smaller than that of the first textured structure.

[0047] Specific surface area refers to the ratio of the surface area of ​​a textured structure to the surface area of ​​the original flat surface (such as a polished surface). The specific surface area of ​​a silicon substrate can be increased through texturing processes. Different types of textured structures have different specific surface areas. Taking a pyramid-shaped textured surface as an example, its specific surface area is related to parameters such as the pyramid size (width and height) and pyramid density, while the specific surface area of ​​a polished surface is 1.

[0048] The specific surface area of ​​the velvet structure is controlled by the velvet process parameters. In the velvet process, the velvet structure is affected by the mass fraction of the velvet solution (i.e., the concentration of acid or alkali), the reaction temperature, and the reaction time. The higher the mass fraction of the velvet solution, the higher the reaction temperature, and the longer the reaction time, the larger the size of the velvet structure and the larger the corresponding specific surface area.

[0049] In practical processes, the specific surface area of ​​a velvet surface can be indirectly measured using techniques such as optical measurement or scanning electron microscopy (SEM). For example, the specific surface area can be estimated by measuring the dimensions of the velvet surface (such as the height and base width of a pyramid). The specific measurement methods for specific surface area will not be elaborated here.

[0050] In this invention, the first textured surface structure in the first region (back metal region) S21 has a large specific surface area, preferably 1.1 to 1.5. Within this specific surface area range, the contact performance of the electrode can be improved and the contact resistivity of the electrode can be reduced. In addition, the second textured surface structure in the second region (back non-metal region) S21 has a small specific surface area, thereby balancing the back passivation performance and the bifaciality. If the second region S21 is a polished surface (i.e., specific surface area is 1), it has good passivation performance, but the bifaciality is low. If the specific surface area of ​​the second region S21 is too large (e.g., greater than 1.1), its bifaciality is high, but the passivation performance is poor. In order to balance passivation performance and bifaciality, in this embodiment, the specific surface area of ​​this region is controlled within the range of 1 to 1.1 (excluding 1) by controlling the size, density, etc. of the textured surface structure.

[0051] In this embodiment, the size and density of the pile structure are controlled by adjusting the alkaline pile forming process parameters. The first pile structure is a pyramid pile structure, with a pyramid width of 0.1μm to 5μm, a height of 0.1μm to 5μm, and a density of 5E4mm. -2~2E5 mm -2 , the second suede structure is a pyramid suede structure, the width of the pyramid is 0.1 μm to 2 μm, the height is 0.1 μm to 2 μm, and the density is 5E4 mm -2 ~2.5E5 mm -2 .

[0052] In addition, in this embodiment, the second surface S2 of the silicon substrate 10 is recessed in the second region S22, that is, there is a height difference between the bottom surface of the pyramid in the second suede structure and the bottom surface of the pyramid in the first suede structure. This height difference can be 0.05 μm to 8 μm, preferably 3 μm to 6 μm.

[0053] In other embodiments, the first region S21 and the second region S22 can also be flush, that is, the bottom surface of the pyramid in the second suede structure and the bottom surface of the pyramid in the first suede structure are on the same plane, or the second surface S2 of the silicon substrate 10 is recessed in the first region S21. Examples are not given here one by one.

[0054] Refer Figure 1 As shown, in this embodiment, a first doping layer 11 is formed on the first surface S1 of the silicon substrate 10 through a diffusion process, and then a PN junction is formed, generating minority carriers - electron-hole pairs after illumination. Exemplarily, the first doping layer 11 is a P-type doping layer (i.e., P+ emitter) deposited by a boron diffusion process, with a surface doping concentration of 3E18 cm -3 ~3E19 cm -3 , and the sheet resistance is 40 Ω / sq to 300 Ω / sq, preferably 150 Ω / sq to 250 Ω / sq.

[0055] Refer Figure 1 And in combination with Figure 2 As shown, in this embodiment, a tunneling passivation contact structure is provided in the first region S21 on the second surface S2 of the silicon substrate 10. The tunneling passivation contact structure includes a tunneling layer 12 and a second doping layer 13 stacked in sequence. The tunneling layer 12 is in direct contact with the second surface S2 of the silicon substrate 10. The tunneling layer 12 can provide a good interface passivation effect, and the second doping layer 13 can provide a field passivation effect. At the same time, because the doping concentration of this layer is relatively high, it can improve the contact and reduce the resistance.

[0056] Among them, the tunneling layer 12 is one or a combination of two of a silicon oxide (SiO X ) layer and a silicon oxynitride (SiO X N Y ) layer, preferably a silicon oxide layer, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm; the second doping layer 13 is a phosphorus-doped polysilicon layer, with a surface doping concentration of 2E20 cm -3 ~3E21 cm -3 , preferably 5E20 cm-3 ~2E21cm -3 The thickness is 1nm to 150nm, preferably 50nm to 100nm. In this embodiment, the thickness of the second doped layer 13 is further reduced, which can reduce parasitic absorption, increase the short-circuit current density of the battery, and significantly improve the battery efficiency and bifaciality without affecting the metallization contact performance.

[0057] It should be understood that this embodiment uses an N-type silicon substrate as an example for illustration. The first doped layer 11 is a P-type doped layer (such as a boron-doped polycrystalline silicon layer), and the second doped layer 13 is an N-type doped layer (such as a phosphorus-doped polycrystalline silicon layer). In other embodiments, a P-type silicon substrate can also be used, in which case the first doped layer 11 is an N-type doped layer and the second doped layer 13 is a P-type doped layer.

[0058] In addition, in this embodiment, a passivation layer and an anti-reflection layer are respectively stacked on the first surface S1 and the second surface S2 of the silicon substrate.

[0059] Specifically, in this embodiment, a first passivation layer 21 and a first antireflection layer 31 are sequentially stacked on the first surface S1 of the silicon substrate 10, and a second passivation layer 22 and a second antireflection layer 32 are sequentially stacked on the second surface S2 of the silicon substrate 10. The second passivation layer 22 and the second antireflection layer 32 cover the second doped layer 13 and extend to the surface of the silicon substrate 10 within the second region S22. The first passivation layer 21 provides excellent field passivation and chemical passivation effects, the second passivation layer 22 provides chemical passivation effects, and the first antireflection layer 31 can reduce reflectivity and increase light utilization.

[0060] For example, the first passivation layer 21 and the second passivation layer 22 are both aluminum oxide passivation layers with a thickness of 2nm to 7nm, preferably 3nm to 6nm; the first antireflection layer 31 and the second antireflection layer 32 can be a stacked film formed by any one or more of silicon nitride, silicon oxynitride, and silicon oxide layers, with a thickness of 60nm to 130nm, preferably silicon nitride. Silicon nitride is chemically inactive and has strong resistance to acid and alkali corrosion, which can reduce the battery's sensitivity to the environment.

[0061] In addition, in this embodiment, the first electrode 41 is located on the first surface S1 of the silicon substrate 10 and is in contact with the first doped layer 11, but cannot penetrate the first doped layer 11 to contact the silicon substrate 10; the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically on the first region S21 in the second surface S2, and is in contact with the second doped layer 13, but cannot damage the bottommost tunneling layer 12, thus ensuring the tunneling function of the tunneling layer 12.

[0062] Exemplarily, in this embodiment, the second electrode 42 is distributed directly above the first region S11, and the projection of the second electrode 42 on the first surface S1 is within the first region S11, that is, the width of the second electrode 42 is less than or equal to the width of the first region S11. Taking the gate line electrode as an example, the gate line electrode may include multiple main gate lines and multiple sub-gate lines (or called thin gate lines) distributed vertically. The main gate lines are usually prepared using non-burn-through paste. In the present utility model, the second electrode 42 is described by taking the sub-gate line in the gate line electrode as an example. The first region S11 includes multiple linearly distributed regions spaced apart from each other, and the width of the second electrode 42 is less than the width of the first region S11.

[0063] As shown Figure 4 in the figure, the first region S21 in this embodiment includes multiple first sub-regions 101 that are parallel and equally spaced apart, the second region S22 includes multiple second sub-regions 102 that are parallel and equally spaced apart, and the first sub-regions 101 and the second sub-regions 102 are staggered, and the width of the first sub-region 101 is less than the width of the second sub-region 102.

[0064] Since the first region S21 needs to ensure the contact performance of the second electrode 42, the first texture structure of the first region S21 requires a larger specific surface area, such as a texture structure with a larger pyramid size. However, a larger specific surface area will affect the passivation performance of the back surface and reduce the open-circuit voltage Voc. Therefore, it is necessary to reduce the area ratio of the first region S21. For example, the width ratio of the first sub-region 101 to the second sub-region 102 can be 1:(5 - 20). Preferably, the width of the first region S21 is 20 μm - 300 μm, and the area of the first region S21 accounts for 2% - 30% of the entire area of the second surface S2.

[0065] The preparation method of the solar cell in this embodiment specifically includes the following steps:

[0066] 1. Double-sided texturing

[0067] As shown Figure 3a in the figure, a silicon substrate 10 is provided. The silicon substrate 10 includes a first surface S1 and a second surface S2 that are opposite to each other. The second surface S2 includes a first region S21 and a second region S22 that are spaced apart from each other. The first surface S1 is the front surface (i.e., the main light-receiving surface) of the silicon substrate 10, the second surface S2 is the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10, the first region S11 is the front metal region, and the second region S12 is the front non-metal region.

[0068] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm - 7 Ω·cm, preferably 0.5 Ω·cm - 3.5 Ω·cm.

[0069] As shown Figure 3bAs shown, in this embodiment, the first surface S1 and the second surface S2 of the silicon substrate 10 are formed with a pyramid texture structure through a conventional alkali texturing process. The alkali solution in the alkali texturing process is a mixed solution of NaOH solution and TMAH or a mixed solution of KOH solution and TMAH. The mass fraction of TMAH is 1% - 5%, the mass fraction of NaOH solution or KOH solution is 0.2% - 2%, the reaction temperature is 70°C - 85°C, the reaction time is 200s - 800s, the width of the pyramids in the texture structure is 0.1μm - 5μm, the height is 0.1μm - 5μm, and the density is 5E4mm -2 ~2E5mm -2 .

[0070] 2. Preparation of P+ emitter

[0071] Refer Figure 3c As shown, a P-type doped first doping layer (i.e., P+ emitter) 11 is prepared on the first surface S1 of the silicon substrate 10 through a diffusion process. The surface doping concentration of the first doping layer 11 is 3E18cm -3 ~3E19cm -3 , and the sheet resistance is 40Ω / sq - 300Ω / sq, preferably 150Ω / sq - 250Ω / sq.

[0072] Exemplarily, a P-type doped first doping layer (i.e., P+ emitter) 11 is formed at the first surface S1 of the silicon substrate 10 through a boron diffusion process. Specifically, in a high-temperature furnace tube, a boron source (such as BCl3 or BBr3, etc.) deposition and push method is used for diffusion. After diffusion, the surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3 , and the sheet resistance is 40Ω / sq - 300Ω / sq, preferably 150Ω / sq - 250Ω / sq. In the boron diffusion process, a BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0073] In this embodiment, the outer layer silicon of the first surface S1 of the silicon substrate 10 is transformed into a boron diffusion layer. After boron diffusion, the total thickness of the silicon substrate 10 and the first doping layer 11 is equal to the thickness of the silicon substrate 10 before boron diffusion.

[0074] 3. Back surface texturing

[0075] Refer Figure 3d and Figure 3e As shown, the second surface S2 of the silicon substrate 10 is wet-etched to prepare a first texture structure on the second surface S2 of the silicon substrate 10.

[0076] First, the silicon wafer after preparing the P+ emitter is passed through a single-sided chain equipment, and the silicon oxide on the back surface is removed using an acid solution (such as hydrofluoric acid);

[0077] Then, a wet etching process is carried out to prepare a first textured structure on the second surface S2 of the silicon substrate 10, while removing the edge junction and the backside plating, and finally a cleaning treatment is performed.

[0078] The wet etching process in this embodiment specifically includes:

[0079] The first alkali polishing process, as shown in [reference figure], polishes the second surface S2 of the silicon substrate 10 with a first alkali solution. Among them, the first alkali solution is a NaOH solution or a KOH solution, with a mass fraction of 1% - 10%, a reaction temperature of 60°C - 85°C, and a reaction time of 100s - 500s; Exemplarily, the first alkali solution is a NaOH solution, with a mass fraction of 5%, a reaction temperature of 70°C, and a reaction time of 200s. Figure 3d Shown as follows, a first alkali solution is used to polish the second surface S2 of the silicon substrate 10. Among them, the first alkali solution is a NaOH solution or a KOH solution, with a mass fraction of 1% - 10%, a reaction temperature of 60°C - 85°C, and a reaction time of 100s - 500s; Exemplarily, the first alkali solution is a NaOH solution, with a mass fraction of 5%, a reaction temperature of 70°C, and a reaction time of 200s.

[0080] The first alkali texturing process, as shown in [reference figure], textures the second surface S2 of the silicon substrate 10 with a second alkali solution to form a first textured structure. The first textured structure is a pyramid textured structure. Among them, the second alkali solution is a mixed solution of a NaOH solution and TMAH or a mixed solution of a KOH solution and TMAH, the mass fraction of TMAH is 1% - 5%, the mass fraction of the NaOH solution or the KOH solution is 0.2% - 5%, the reaction temperature is 70°C - 85°C, and the reaction time is 200s - 800s; Exemplarily, the second alkali solution is a mixed solution of a NaOH solution and TMAH, the mass fraction of TMAH is 3%, the mass fraction of the NaOH solution is 3%, the reaction temperature is 80°C, and the reaction time is 400s. Figure 3e Shown as follows, a second alkali solution is used to texture the second surface S2 of the silicon substrate 10 to form a first textured structure. The first textured structure is a pyramid textured structure. Among them, the second alkali solution is a mixed solution of a NaOH solution and TMAH or a mixed solution of a KOH solution and TMAH, the mass fraction of TMAH is 1% - 5%, the mass fraction of the NaOH solution or the KOH solution is 0.2% - 5%, the reaction temperature is 70°C - 85°C, and the reaction time is 200s - 800s; Exemplarily, the second alkali solution is a mixed solution of a NaOH solution and TMAH, the mass fraction of TMAH is 3%, the mass fraction of the NaOH solution is 3%, the reaction temperature is 80°C, and the reaction time is 400s.

[0081] Through the above wet etching process, the width of the pyramid in the prepared first textured structure is 0.1μm - 5μm, the height is 0.1μm - 5μm, and the density is 5E4 mm -2 ~2E5 mm -2 .

[0082] In the wet etching process of this step, the second surface S2 of the silicon substrate 10 is first alkali polished to remove the original pyramid textured structure on the second surface S2 and form a polished surface. At this time, multiple tower bases (the tower base is the base left after the pyramid textured structure is polished) will be formed on the polished surface, and then alkali texturing is performed on this polished surface to form a pyramid textured structure.

[0083] 4. Preparation of the backside tunneling passivated contact structure

[0084] As shown in [reference figure], a tunneling layer 12, a second doping layer 13, and a mask layer 14 are sequentially stacked on the second surface S2. Figure 3f Shown as follows, a tunneling layer 12, a second doping layer 13, and a mask layer 14 are sequentially stacked on the second surface S2.

[0085] Exemplarily, in this embodiment, a silicon oxide tunneling layer is first deposited on the back surface by PECVD process, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm;

[0086] Then, a phosphorus-doped amorphous silicon layer is deposited by PECVD process, with a surface doping concentration of 2E20 cm -3 ~3E21 cm -3 , preferably 5E20 cm -3 ~2E21 cm -3 , and a thickness of 1 nm to 150 nm, preferably 50 nm to 100 nm;

[0087] Finally, a mask layer 14 is deposited. The mask layer is any one or a combination of silicon oxide (SiO X ) layer, silicon oxynitride (SiO X N Y ) layer and silicon nitride (SiN X ) layer, with a thickness of 1 nm to 100 nm, preferably 5 nm to 30 nm.

[0088] Finally, the silicon substrate with the tunneling passivation contact structure deposited on the back surface is placed in a high-temperature annealing furnace for high-temperature annealing. The annealing temperature is 850 °C to 950 °C, preferably 890 °C to 920 °C. During the annealing process, phosphorus is activated, thereby converting the doped amorphous silicon layer into a doped polycrystalline silicon layer.

[0089] 5. Laser opening of the film

[0090] As shown in the figure Figure 3g , the mask layer 14 on the second region (non-metal region) S22 is pattern-opened by laser process.

[0091] The energy required for laser opening of the film is affected by the thickness of the mask layer. In this embodiment, the laser is a green picosecond laser or a violet picosecond laser, the laser power is 5 W to 120 W, preferably 10 W to 50 W, the laser frequency is 100 kHz to 1000 kHz, preferably 300 kHz to 600 kHz, the laser scanning rate is 10000 mm / s to 100000 mm / s, preferably 10000 mm / s to 60000 mm / s, and the laser spot overlap rate is 0% to 80%, preferably 0% to 20%.

[0092] 6. Wet etching

[0093] As shown in the figure Figures 3h to 3j , the second surface S2 of the silicon substrate 10 is wet-etched to remove all the tunneling passivation contact structures in the second region S22 and form a second textured structure on the surface of the silicon substrate in the second region S22.

[0094] First, the PSG (phosphosilicate glass) on the front and edges is removed using a single-sided chain equipment with hydrofluoric acid.

[0095] Then, a wet etching process is performed to remove the tunneling layer 12 and the second doped layer 13 on the second region S22, and to form a second textured structure on the silicon substrate surface of the second region S22, while removing the front and edge plating.

[0096] The wet etching process in this embodiment specifically includes:

[0097] The second alkali polishing process, refer to Figure 3h As shown, the second region S22 of the second surface S2 of the silicon substrate 10 is polished using a third alkaline solution to remove all tunneling passivation contact structures in the second region S22. The third alkaline solution is a NaOH solution or a KOH solution with a mass fraction of 1% to 10%, a reaction temperature of 60°C to 85°C, and a reaction time of 100s to 500s. For example, the first alkaline solution is a NaOH solution with a mass fraction of 5%, a reaction temperature of 70°C, and a reaction time of 200s.

[0098] The second alkali-based fabrication process, refer to Figure 3i As shown, a fourth alkaline solution is used to texturize the second surface S2 of the silicon substrate 10 to form a first textured structure, which is a pyramid textured structure. The fourth alkaline solution is a mixture of NaOH solution and TMAH or a mixture of KOH solution and TMAH, with a mass fraction of TMAH of 1% to 5% and a mass fraction of NaOH solution or KOH solution of 0.2% to 2%. The reaction temperature is 60℃ to 85℃, and the reaction time is 50s to 500s. For example, the second alkaline solution is a mixture of NaOH solution and TMAH, with a mass fraction of TMAH of 3% and a mass fraction of NaOH solution of 1%. The reaction temperature is 70℃, and the reaction time is 200s.

[0099] Finally, refer to Figure 3j As shown, hydrofluoric acid is used to remove the mask layer 14 on the first region S21 on the back side, while the BSG (borosilicate glass) on the front side is also removed, and RCA cleaning is performed.

[0100] Using the aforementioned wet etching process, the width of the pyramids in the prepared second textured structure is 0.1 μm to 2 μm, the height is 0.1 μm to 2 μm, and the density is 5E4 mm². -2 ~2.5E5mm -2 .

[0101] In the wet etching process of this step, an alkali polishing process is first used to perform alkali polishing on the second region S22 in the second surface S2 of the silicon substrate 10 to remove the first textured structure of the original second region S22. Optionally, after the alkali polishing process removes the first textured structure, it will further etch part of the silicon substrate 10 downward. The silicon substrate 10 in the first region S21 and the tunneling passivation contact structure will not be etched due to the protection of the mask layer 14. Therefore, the second surface S2 of the silicon substrate 10 is recessed in the second region S22. That is, there is a height difference between the bottom surface of the pyramid in the second textured structure and the bottom surface of the pyramid in the first textured structure. This height difference can be 0.05 μm to 8 μm, preferably 3 μm to 6 μm.

[0102] The first alkali polishing process in step S3 is basically the same as the second alkali polishing process in this step. Their purposes are to polish the silicon substrate 10 on the back side, the front side or locally to form a polished surface. However, compared with the first alkali texturing process in step S3 and the second alkali texturing process in this step, the mass fraction of the alkali solution in this step is smaller, the texturing temperature is lower, and the texturing time is shorter. In this way, a pyramid structure with smaller size and higher density can be formed, thereby reducing the specific surface area of the second region S22.

[0103] It should be understood that in other embodiments, the process parameters of alkali polishing and alkali texturing can be adjusted according to actual situations. Any technical solution that can obtain a textured structure with a smaller specific surface area in the second region S22 belongs to the scope protected by the present invention.

[0104] In this embodiment, since the first region S1 of the second surface S2 only undergoes one wet etching (alkali polishing + alkali texturing) process, while the second region S22 undergoes two wet etching (alkali polishing + alkali texturing) processes, the second region S22 is recessed. That is, there is a height difference between the bottom surface of the pyramid in the second textured structure and the bottom surface of the pyramid in the first textured structure. This height difference is related to the process parameters of wet etching and can be 0.05 μm to 8 μm, preferably 3 μm to 6 μm.

[0105] 7. Prepare the passivation layer

[0106] As shown in reference Figure 3k The first passivation layer 21 and the second passivation layer 22 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate by using the ALD process. The first passivation layer 21 and the second passivation layer 22 are both alumina passivation layers with a thickness of 2 nm to 7 nm, preferably 3 nm to 6 nm.

[0107] After the wet etching process, the tunneling layer and the doped polysilicon layer in the first region S21 can still ensure the passivation effect, while there is no passivation layer protection on the second region S22. Therefore, while preparing the first passivation layer 21 on the front side, it is necessary to simultaneously prepare the second passivation layer 22 on the back side.

[0108] 8. Preparation of antireflection layer

[0109] As shown Figure 3l in the figure, the first antireflection layer 31 and the second antireflection layer 32 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate by the PECVD process. The first antireflection layer 31 and the second antireflection layer 32 can be a stacked film formed by any one or more of silicon nitride layer, silicon oxynitride layer, and silicon oxide layer, and the thickness is 60nm - 130nm.

[0110] 9. Printing metal electrodes

[0111] As shown Figure 3m in the figure, the first electrode 41 and the second electrode 42 are respectively printed on the first surface S1 and the second surface S2 by the screen printing process, and then sintering and optical injection or electrical injection treatment are carried out to form an ohmic contact.

[0112] The first electrode 41 and the second electrode 42 are grid line electrodes in the prior art, and usually include main grid lines and fine grid lines. It should be noted that since the fine grid lines in the second electrode 42 need to be printed on the first region S21, the width of the first region S21 needs to be greater than the width of the fine grid lines in the second electrode 42, so that the alignment of the fine grid lines can be achieved.

[0113] The TOPCon battery can be prepared through the above steps, and finally the battery wafers are tested, sorted and stored in the warehouse.

[0114] Example 2:

[0115] The solar cell and its preparation method in this example are substantially the same as those in Example 1, except that the first doping layer 11 in Example 1 is prepared by the diffusion process, while the first doping layer 11 in this example is prepared by the PECVD process and the annealing process.

[0116] [[ID=3**]]Specifically, a P-type doped first doping layer (i.e., P+ emitter) 11 is formed on the first surface S1 of the silicon substrate 10 by the PECVD process and the annealing process. The surface doping concentration of the first doping layer 11 is 3E18cm -3 ~3E19cm -3 , the sheet resistance is 40Ω / sq - 300Ω / sq, preferably 150Ω / sq - 250Ω / sq.

[0117] Exemplarily, first, a boron-doped amorphous silicon layer is deposited on the first surface S1 by PECVD process, with a deposition thickness of 10 nm to 100 nm, and then the boron-doped amorphous silicon layer is transformed into a boron-doped polycrystalline silicon layer by high-temperature oxidation annealing. In the high-temperature oxidation annealing process, a silicon oxide layer will be formed on the second surface S2 of the silicon substrate 10, and this silicon oxide layer can serve as the front protection layer in the subsequent back wet etching process.

[0118] A P-type doped polycrystalline silicon layer is prepared on the surface of the silicon substrate by PECVD process and annealing process. During this process, the thickness of the silicon substrate remains constant. After annealing, the total thickness of the silicon substrate and the boron-doped polycrystalline silicon layer is equal to the total thickness of the silicon substrate and the boron-doped amorphous silicon layer before annealing, and is greater than the thickness of the silicon substrate before the PECVD process.

[0119] Comparative Example 1:

[0120] Ref Figure 5 The structure schematic diagram of the solar cell in this comparative example is shown. This solar cell is a TOPCon cell, and its cell structure is roughly the same as that of Example 1. The difference is that the second surface S2 of the silicon substrate 10 in this comparative example is a polished surface formed by an alkali polishing process.

[0121] As discussed in Example 1, although the polished surface has good passivation performance, the contact performance under the first region electrode is poor, and the contact resistivity of the electrode is large, resulting in lower bifaciality and conversion efficiency of the cell. Compared with Comparative Example 1, Example 1 can significantly improve the bifaciality, and finally the cell efficiency Eff can be increased by more than 0.15%.

[0122] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any regard, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0123] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that, The solar cell includes a silicon substrate, which includes a first surface and a second surface disposed opposite to each other. The second surface includes a first region and a second region distributed at intervals. The first region is provided with a tunneling passivation contact structure. The silicon substrate surface of the first region is formed with a first textured structure. The silicon substrate surface of the second region is formed with a second textured structure. The specific surface area of ​​the second textured structure is smaller than that of the first textured structure.

2. The solar cell according to claim 1, characterized in that, The specific surface area of ​​the first velvet structure is greater than or equal to 1.1 and less than or equal to 1.5; and / or, The specific surface area of ​​the second velvet structure is greater than 1 and less than or equal to 1.

1.

3. The solar cell according to claim 1, characterized in that, Both the first and second velvet structures are pyramid velvet structures.

4. The solar cell according to claim 3, characterized in that, The average size of the pyramids in the first velvet structure is greater than the average size of the pyramids in the second velvet structure; and / or, The density of the pyramids in the first velvet structure is less than the density of the pyramids in the second velvet structure.

5. The solar cell according to claim 3, characterized in that, In the first velvet structure, the width of the pyramids ranges from 0.1 μm to 5 μm, the height ranges from 0.1 μm to 5 μm, and the density is 5E4mm. -2 ~2E5mm -2 ; and / or, In the second velvet structure, the width of the pyramids ranges from 0.1 μm to 2 μm, the height ranges from 0.1 μm to 2 μm, and the density is 5E4mm. -2 ~2.5E5mm -2 .

6. The solar cell according to claim 1, characterized in that, The width of the first region is 20 μm to 600 μm; and / or, The area of ​​the first region accounts for 5% to 10% of the total area of ​​the second surface.

7. The solar cell according to claim 1, characterized in that, The second surface of the silicon substrate is recessed in the second region.

8. The solar cell according to claim 1, characterized in that, The tunneling passivation contact structure includes a tunneling layer in direct contact with the silicon substrate and a second doped layer disposed on the tunneling layer. The doping type of the second doped layer is the same as that of the silicon substrate. The first region is provided with a second electrode in contact with the second doped layer.

9. The solar cell according to claim 1, characterized in that, A second passivation layer and / or a second antireflection layer are stacked on the tunneling passivation contact structure in the first region and / or the second textured structure in the second region.

10. The solar cell according to claim 1, characterized in that, A first doped layer and a first electrode are formed on the first surface of the silicon substrate. The doping type of the first doped layer is opposite to that of the silicon substrate. The first electrode is in contact with the first doped layer.

11. The solar cell according to claim 10, characterized in that, The first doped layer is stacked with a first passivation layer and / or a first antireflection layer.

12. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell according to any one of claims 1 to 11.

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