Charging pile control panel

Abstract

The utility model discloses a charging pile control panel, which relates to the technical field of electric automobile charging equipment, and comprises a main control module used for analyzing a charging pile system protocol and dispatching charging pile equipment by using a chip set; the communication interface module is used for performing information interaction with external equipment and a network through an interface; the power supply management module is used for supplying power to the charging pile control panel by taking a direct-current power supply and target voltage analog input mode as a power supply source; the input detection circuit is used for detecting an external switching value and a power-on state of the charging pile control panel; and the analog-to-digital converter acquisition circuit is used for acquiring analog quantity signals and realizing power supply control in a motor control outlet mode. According to the utility model, through the innovation of the hardware structure, the bottleneck of the charging pile control panel in the aspects of multi-device communication, protocol compatibility and integration level is solved, and a reliable hardware basis is provided for the mass production of high-power charging piles.

Description

Technical Field

[0001] This utility model relates to the field of electric vehicle charging equipment technology, and more specifically, to a charging pile control board. Background Technology

[0002] Currently, the control boards for electric vehicle charging stations typically employ general-purpose embedded hardware solutions, with core functions including power management, communication interfaces (such as RS485 and CAN), and digital input / output (DI / DO) control. However, existing control board designs suffer from the following problems:

[0003] (1) Dispersed interfaces and poor scalability: The peripheral interfaces of traditional control boards are scattered and need to be expanded by flying wires or adapter boards, resulting in high circuit complexity and reduced reliability. A single CAN (a communication protocol) interface cannot meet the parallel communication requirements of multiple charging piles, requiring external expansion modules, which increases cost and potential failure points.

[0004] (2) Low hardware reuse rate: Different models of charging piles require customized circuits, which cannot achieve broad compatibility and result in high cost of repeated development.

[0005] (3) Insufficient electrical performance: Insufficient heat dissipation design in high-power scenarios, weak power supply anti-interference ability, which can easily lead to failure.

[0006] (4) Difficult to maintain: The low degree of modularity means that a single point of failure requires the replacement of the entire board.

[0007] (5) Insufficient signal compatibility: The fixed baud rate design is difficult to adapt to the BMS (Battery Management System) communication protocols of different vehicle models, causing communication timeout failures.

[0008] (6) Low structural integration: The peripheral interfaces are scattered and the wiring is complicated, which is not conducive to the miniaturization design of the charging pile cabinet. The power module lacks protection mechanism, and the device is at risk of burning out under high power conditions.

[0009] No effective solutions have yet been proposed to address the problems in the relevant technologies. Utility Model Content

[0010] In view of the problems in the related technologies, this utility model proposes a charging pile control board to overcome the above-mentioned technical problems existing in the existing related technologies.

[0011] Therefore, the specific technical solution adopted by this utility model is as follows:

[0012] A charging pile control board includes:

[0013] The main control module, communication interface module, and power management module are integrated within the single-board structure. The main control module is connected to the input detection circuit and has a built-in analog-to-digital converter (ADC) acquisition circuit. Specifically, the main control module uses the chipset to parse the charging pile system protocol and schedule charging pile equipment; the communication interface module interacts with external devices and networks via an interface; the power management module supplies power to the charging pile control board using DC power and target voltage analog input; the input detection circuit detects external switching quantities and power-on status of the charging pile control board; and the ADC acquisition circuit acquires analog signals and implements power control through the motor control output.

[0014] Furthermore, the main control module includes chips P1, P2, P3, and P4, diode D136, capacitor C50, resistors R23, C51, and C478, diode D137, resistors R285, R286, R288, R289, R24, and R25. One end of diode D137 is connected to one end of capacitor C478 and one end of capacitor C51. The other end of diode D137 is sequentially connected to the 79th terminal of chip P3, the other end of capacitor C478, the other end of capacitor C51, the 77th terminal of chip P3, and the 70th terminal of chip P3. One end of the five terminals and one end of the resistor R23 are connected. The other end of the resistor R23 is connected to one end of the capacitor C50 and one end of the diode D136 in sequence. The other end of the diode D136 is connected to the other end of the capacitor C50. The forty-eighth terminal of the chip P3 is connected to the resistor R285. The fiftieth terminal of the chip P3 is connected to the resistor R286. The fifty-fourth terminal of the chip P3 is connected to the resistor R289. The fifty-sixth terminal of the chip P3 is connected to the resistor R288. The third terminal of the chip P4 is connected to the resistor R24. The fifth terminal of the chip P4 is connected to the resistor R25. Chips P1 and P2 are arranged sequentially on the sides of the chips P4 and P3.

[0015] Furthermore, the communication interface module is integrated into the J9 terminal block, including several CAN channels.

[0016] Furthermore, the power management module includes: chip U2, capacitors C19, C20, and C21, resistors R7 and R8, capacitors C22, C23, and C11, diode D4, resistor R10, capacitor C24, and capacitor C25, inductor L1, capacitors C13, C14, C15, C16, and C18, resistors R6, R9, and R3, diode D3, and capacitor C17; wherein, the first terminal of chip U2 is connected to one terminal of capacitor C11. The second terminal of chip U2 is connected in sequence to one end of resistor R7, one end of capacitor C21, one end of capacitor C20, and one end of capacitor C19. The other end of capacitor C19 is connected in sequence to the other end of capacitor C20 and the other end of capacitor C21. The third terminal of chip U2 is connected in sequence to one end of capacitor C22, one end of resistor R8, and the other end of resistor R7. The fourth terminal of chip U2 is connected to one end of capacitor C23. The other end of capacitor C23 is connected in sequence to the ninth terminal of chip U2, the other end of capacitor C22, and resistor R8. The other end is connected; the eighth terminal of chip U2 is connected in sequence to the other end of capacitor C11, the negative terminal of diode D4, and the first terminal of inductor L1; the seventh terminal of chip U2 is connected in sequence to the positive terminal of diode D4, one end of capacitor C13, one end of capacitor C14, one end of capacitor C15, and one end of capacitor C16; the second terminal of inductor L1 is connected in sequence to the other end of capacitor C13, the other end of capacitor C14, the other end of capacitor C15, the other end of capacitor C16, one end of resistor R6, one end of capacitor C18, and the other end of inductor L1. One end of resistor R3 is connected to the capacitor. The other end of resistor R6 is connected in sequence to the other end of capacitor C18, one end of resistor R9, and the fifth terminal of chip U2. The other end of resistor R3 is connected in sequence to one end of diode D3 and one end of capacitor C17. The other end of diode D3 is connected to the other end of capacitor C17. The sixth terminal of chip U2 is connected in sequence to one end of resistor R10 and one end of capacitor C25. The other end of resistor R10 is connected to one end of capacitor C24. The other end of capacitor C24 is connected to the other end of capacitor C25.

[0017] Furthermore, the power management module also includes: chip U3, capacitors C34, C35, and C36, resistors R16 and R17, capacitors C37, C38, and C27, diode D6, resistor R19, capacitor C39, and capacitor C40, inductor L2, capacitors C26, C29, C30, C31, and C33, resistors R15, R18, and R12, diode D5, and capacitor C32; wherein, the first terminal of chip U3 is connected to one terminal of capacitor C27. The second terminal of chip U3 is connected sequentially to one end of capacitor C36, one end of capacitor C35, and one end of capacitor C34. The other end of capacitor C34 is connected sequentially to the other end of capacitor C35 and the other end of capacitor C36. The third terminal of chip U3 is connected sequentially to one end of capacitor C37, one end of resistor R17, and one end of resistor R16. The fourth terminal of chip U3 is connected to one end of capacitor C38. The other end of capacitor C38 is connected sequentially to the ninth terminal of chip U3, the other end of capacitor C37, and the other end of resistor R17. Terminal connections: The eighth terminal of chip U3 is connected in sequence to the other end of capacitor C27, the cathode of diode D6, and the first terminal of inductor L2. The seventh terminal of chip U3 is connected in sequence to the anode of diode D6, one end of capacitor C26, one end of capacitor C29, one end of capacitor C30, and one end of capacitor C31. The second terminal of inductor L2 is connected in sequence to the other ends of capacitors C26, C29, C30, and C31, one end of resistor R15, one end of capacitor C33, and resistor R1 One end of 2 is connected, and the other end of resistor R15 is connected in sequence to the other end of capacitor C33, one end of resistor R18 and the fifth end of chip U3. The other end of resistor R12 is connected in sequence to one end of diode D5 and one end of capacitor C32, and the other end of diode D5 is connected to the other end of capacitor C32. The sixth end of chip U3 is connected in sequence to one end of resistor R19 and one end of capacitor C40. The other end of resistor R19 is connected to one end of capacitor C39, and the other end of capacitor C39 is connected to the other end of capacitor C40.

[0018] Furthermore, the input detection circuit includes chip U90, resistors R472 and R474, capacitor C371, resistors R475 and R473; wherein, the first terminal of chip U90 is connected to one end of resistor R474 and one end of resistor R472 in sequence, the second terminal of chip U90 is connected to the other end of resistor R474; the fourth terminal of chip U90 is connected to one end of resistor R475, one end of resistor R473 and one end of capacitor C371 in sequence, and the other end of capacitor C371 is connected to the third terminal of chip U90.

[0019] Furthermore, the analog-to-digital converter acquisition circuit includes chip IC1, resistors R830, R829, R831, capacitors C100 and C99, resistors R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, and R94; wherein, the thirteenth terminal of chip IC1 is connected to one end of resistor R830, the twelfth terminal of chip IC1 is connected to one end of resistor R829, the eleventh terminal of chip IC1 is connected to one end of resistor R831, and the other end of resistor R830 is connected sequentially to the other ends of resistors R829 and R831; chip IC1 The seventh terminal of IC1 is connected to one end of resistor R84, the other end of resistor R84 is connected to the eighth terminal of IC1, the thirty-fourth terminal of IC1 is connected to resistor R86, the thirty-third terminal of IC1 is connected to resistor R87, the thirty-second terminal of IC1 is connected to resistor R88, the thirty-first terminal of IC1 is connected to one end of resistor R89, the other end of resistor R89 ​​is connected to resistor R85, the thirty-eighth terminal of IC1 is connected to resistor R91, and the thirty-seventh terminal of IC1 is connected to resistor R92. On the side of IC1, capacitors C100 and C99, resistors R90, R93, and R94 are also sequentially arranged, with resistors R90 and R93 connected in series.

[0020] Furthermore, the analog-to-digital converter acquisition circuit also includes: diodes D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, and D25; wherein diodes D13, D14, D15, and D16 are connected in parallel, diodes D17, D18, D19, and D20 are connected in parallel, diodes D21, D22, D23, and D24 are connected in parallel, and diode D25 is provided on one side of diode D24.

[0021] The beneficial effects of this utility model are as follows:

[0022] (1) Improved communication efficiency: Multiple CAN channels support parallel data transmission, increasing data throughput by 40% and reducing communication conflict rate by 90% compared to a single CAN interface, meeting the needs of multi-gun fast charging.

[0023] (2) Improved compatibility: Protocol adaptation enables communication compatibility to cover mainstream BMS standards.

[0024] (3) Cost and reliability optimization: Interface reuse reduces external expansion modules, reduces single board cost by 25%, reduces failure points by 60%, and power protection response time ≤5ms.

[0025] (4) Ease of installation: The compact structure and standardized interface layout improve installation efficiency by 50% and are compatible with mainstream charging pile cabinets.

[0026] (5) This utility model solves the bottlenecks of multi-device communication, protocol compatibility and integration of the charging pile control board through hardware structure innovation, and provides a reliable hardware foundation for the mass production of high-power charging piles. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a module block diagram of a charging pile control board according to an embodiment of the present utility model;

[0029] Figure 2 This is one of the circuit schematic diagrams of the main control module in a charging pile control board according to an embodiment of the present utility model;

[0030] Figure 3 This is the second circuit schematic diagram of the main control module in a charging pile control board according to an embodiment of the present utility model;

[0031] Figure 4 This is the third circuit schematic diagram of the main control module in a charging pile control board according to an embodiment of the present utility model;

[0032] Figure 5 This is the fourth circuit schematic diagram of the main control module in a charging pile control board according to an embodiment of the present utility model;

[0033] Figure 6 This is the fifth circuit schematic diagram of the main control module in a charging pile control board according to an embodiment of the present utility model;

[0034] Figure 7 This is a circuit diagram of a communication interface module in a charging pile control board according to an embodiment of the present utility model;

[0035] Figure 8 This is one of the circuit schematic diagrams of the power management module in a charging pile control board according to an embodiment of the present utility model;

[0036] Figure 9 This is a second circuit schematic diagram of the power management module in a charging pile control board according to an embodiment of the present utility model;

[0037] Figure 10 This is a circuit diagram of the power management module in a charging pile control board according to an embodiment of the present utility model;

[0038] Figure 11 This is one of the circuit schematic diagrams of the analog-to-digital converter acquisition circuit in a charging pile control board according to an embodiment of the present utility model;

[0039] Figure 12 This is the second circuit schematic diagram of the analog-to-digital converter acquisition circuit in a charging pile control board according to an embodiment of the present utility model;

[0040] Figure 13 This is the third circuit schematic diagram of the analog-to-digital converter acquisition circuit in a charging pile control board according to an embodiment of the present utility model;

[0041] Figure 14 This is a hardware overall block diagram according to an embodiment of the present utility model;

[0042] Figure 15 This is a block diagram of the charging function according to an embodiment of the present utility model;

[0043] Figure 16 This is a block diagram of a master-slave processor according to an embodiment of the present utility model;

[0044] Figure 17 This is a human-computer interaction block diagram according to an embodiment of the present utility model;

[0045] Figure 18 This is a block diagram of the input and output according to an embodiment of the present utility model;

[0046] Figure 19 This is an ADC acquisition block diagram according to an embodiment of the present utility model;

[0047] Figure 20 This is a network communication block diagram according to an embodiment of the present utility model.

[0048] In the picture:

[0049] 1. Main control module; 2. Communication interface module; 3. Power management module; 4. Input detection circuit; 5. Analog-to-digital converter acquisition circuit. Detailed Implementation

[0050] To further illustrate the various embodiments, the present invention provides accompanying drawings, which are part of the disclosure of the present invention. These drawings are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, those skilled in the art should be able to understand other possible implementation methods and the advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are usually used to represent similar components.

[0051] According to an embodiment of this utility model, a charging pile control board is provided. In particular, it is an embedded control hardware for electric vehicle charging piles, including power management, communication interfaces, and terminating resistor control structures.

[0052] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figure 1 As shown, the charging pile control board according to an embodiment of this utility model includes: a main control module 1, a communication interface module 2, and a power management module 3 integrated within a single board structure. The main control module 1 is connected to an input detection circuit 4, and the main control module 1 has a built-in analog-to-digital converter (ADC) acquisition circuit 5. The main control module 1 is used to parse the charging pile system protocol and schedule charging pile equipment using the chipset. The communication interface module 2 is used to interact with external devices and networks through an interface. The power management module 3 is used to power the charging pile control board using DC power and a target voltage analog input as the power source. The input detection circuit 4 is used to detect the external switching quantities and power-on status of the charging pile control board. The analog-to-digital converter acquisition circuit 5 is used to acquire analog signals and realize power control through a motor control output.

[0053] By utilizing the above-mentioned solution, this utility model solves the bottlenecks in multi-device communication, protocol compatibility, and integration of the charging pile control board through hardware structural innovation, providing a reliable hardware foundation for the mass production of high-power charging piles.

[0054] like Figures 2-6As shown, in one embodiment, the main control module 1 includes chips P1, P2, P3, P4, diode D136, capacitor C50, resistor R23, capacitor C51, capacitor C478, diode D137, resistor R285, resistor R286, resistor R288, resistor R289, resistor R24, and resistor R25; wherein, one end of diode D137 is connected to one end of capacitor C478 and one end of capacitor C51, and the other end of diode D137 is sequentially connected to the seventy-ninth terminal of chip P3, the other end of capacitor C478, the other end of capacitor C51, the seventy-seventh terminal of chip P3, and the other end of chip P478. The 75th terminal of chip P3 is connected to one end of resistor R23. The other end of resistor R23 is connected to one end of capacitor C50 and one end of diode D136 in sequence. The other end of diode D136 is connected to the other end of capacitor C50. The 48th terminal of chip P3 is connected to resistor R285. The 50th terminal of chip P3 is connected to resistor R286. The 54th terminal of chip P3 is connected to resistor R289. The 56th terminal of chip P3 is connected to resistor R288. The third terminal of chip P4 is connected to resistor R24. The fifth terminal of chip P4 is connected to resistor R25. Chips P1 and P2 are arranged sequentially on the sides of chips P4 and P3.

[0055] like Figure 7 As shown, in one embodiment, the communication interface module 2 is integrated into the J9 terminal block and includes several CAN channels.

[0056] like Figure 8As shown, in one embodiment, the power management module 3 includes: chip U2, capacitors C19, C20, and C21, resistors R7 and R8, capacitors C22, C23, and C11, diode D4, resistor R10, capacitor C24, and capacitor C25, inductor L1, capacitors C13, C14, C15, C16, and C18, resistors R6, R9, and R3, diode D3, and capacitor C17; wherein, the first terminal of chip U2 is connected to one terminal of capacitor C11. The second terminal of chip U2 is connected sequentially to one end of resistor R7, one end of capacitor C21, one end of capacitor C20, and one end of capacitor C19. The other end of capacitor C19 is connected sequentially to the other end of capacitor C20 and the other end of capacitor C21. The third terminal of chip U2 is connected sequentially to one end of capacitor C22, one end of resistor R8, and the other end of resistor R7. The fourth terminal of chip U2 is connected to one end of capacitor C23. The other end of capacitor C23 is connected sequentially to the ninth terminal of chip U2, the other end of capacitor C22, and the other end of capacitor C19. The other end of resistor R8 is connected; the eighth terminal of chip U2 is connected in sequence to the other end of capacitor C11, the cathode of diode D4, and the first terminal of inductor L1; the seventh terminal of chip U2 is connected in sequence to the anode of diode D4, one end of capacitor C13, one end of capacitor C14, one end of capacitor C15, and one end of capacitor C16; the second terminal of inductor L1 is connected in sequence to the other ends of capacitor C13, C14, C15, and C16, one end of resistor R6, and one end of capacitor C18. One end of resistor R3 is connected to the capacitor. The other end of resistor R6 is connected in sequence to the other end of capacitor C18, one end of resistor R9, and the fifth terminal of chip U2. The other end of resistor R3 is connected in sequence to one end of diode D3 and one end of capacitor C17. The other end of diode D3 is connected to the other end of capacitor C17. The sixth terminal of chip U2 is connected in sequence to one end of resistor R10 and one end of capacitor C25. The other end of resistor R10 is connected to one end of capacitor C24. The other end of capacitor C24 is connected to the other end of capacitor C25.

[0057] like Figure 9As shown, in one embodiment, the power management module 3 further includes: chip U3, capacitors C34, C35, and C36, resistors R16 and R17, capacitors C37, C38, and C27, diode D6, resistor R19, capacitor C39, and capacitor C40, inductor L2, capacitors C26, C29, C30, C31, and C33, resistors R15, R18, and R12, diode D5, and capacitor C32; wherein, the first terminal of chip U3 is connected to capacitor C32. One end of C27 is connected. The second end of chip U3 is connected sequentially to one end of capacitor C36, one end of capacitor C35, and one end of capacitor C34. The other end of capacitor C34 is connected sequentially to the other ends of capacitor C35 and capacitor C36. The third end of chip U3 is connected sequentially to one end of capacitor C37, one end of resistor R17, and one end of resistor R16. The fourth end of chip U3 is connected to one end of capacitor C38. The other end of capacitor C38 is connected sequentially to the ninth end of chip U3, the other end of capacitor C37, and resistor R16. The other end of 7 is connected; the eighth end of chip U3 is connected in sequence to the other end of capacitor C27, the cathode of diode D6, and the first end of inductor L2; the seventh end of chip U3 is connected in sequence to the anode of diode D6, one end of capacitor C26, one end of capacitor C29, one end of capacitor C30, and one end of capacitor C31; the second end of inductor L2 is connected in sequence to the other end of capacitor C26, the other end of capacitor C29, the other end of capacitor C30, the other end of capacitor C31, one end of resistor R15, one end of capacitor C33, and resistor R15. One end of R12 is connected, and the other end of resistor R15 is connected in sequence to the other end of capacitor C33, one end of resistor R18, and the fifth end of chip U3. The other end of resistor R12 is connected in sequence to one end of diode D5 and one end of capacitor C32, and the other end of diode D5 is connected to the other end of capacitor C32. The sixth end of chip U3 is connected in sequence to one end of resistor R19 and one end of capacitor C40. The other end of resistor R19 is connected to one end of capacitor C39, and the other end of capacitor C39 is connected to the other end of capacitor C40.

[0058] like Figure 10 As shown, in one embodiment, the input detection circuit 4 includes a chip U90, resistors R472 and R474, a capacitor C371, resistors R475 and R473; wherein, the first terminal of the chip U90 is connected to one end of resistor R474 and one end of resistor R472 in sequence, the second terminal of the chip U90 is connected to the other end of resistor R474; the fourth terminal of the chip U90 is connected to one end of resistor R475, one end of resistor R473 and one end of capacitor C371 in sequence, and the other end of capacitor C371 is connected to the third terminal of the chip U90.

[0059] like Figure 11As shown, in one embodiment, the analog-to-digital converter acquisition circuit 5 includes a chip IC1, resistors R830, R829, R831, capacitors C100 and C99, resistors R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, and R94; wherein, the thirteenth terminal of chip IC1 is connected to one end of resistor R830, the twelfth terminal of chip IC1 is connected to one end of resistor R829, the eleventh terminal of chip IC1 is connected to one end of resistor R831, and the other end of resistor R830 is sequentially connected to the other ends of resistors R829 and R831; the chip The seventh terminal of IC1 is connected to one end of resistor R84, and the other end of resistor R84 is connected to the eighth terminal of IC1. The thirty-fourth terminal of IC1 is connected to resistor R86, the thirty-third terminal of IC1 is connected to resistor R87, the thirty-second terminal of IC1 is connected to resistor R88, the thirty-first terminal of IC1 is connected to one end of resistor R89, the other end of resistor R89 ​​is connected to resistor R85, the thirty-eighth terminal of IC1 is connected to resistor R91, and the thirty-seventh terminal of IC1 is connected to resistor R92. On the side of IC1, capacitor C100, capacitor C99, resistor R90, resistor R93, and resistor R94 are also arranged in sequence, and resistors R90 and R93 are connected in series.

[0060] like Figures 12-13 As shown, in one embodiment, the analog-to-digital converter acquisition circuit 5 further includes: diodes D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, and D25; wherein diodes D13, D14, D15, and D16 are connected in parallel, diodes D17, D18, D19, and D20 are connected in parallel, diodes D21, D22, D23, and D24 are connected in parallel, and diode D25 is disposed on one side of diode D24.

[0061] To facilitate understanding of the above-mentioned technical solutions of this utility model, the working principle or operation method of this utility model in actual process will be described in detail below.

[0062] Multi-channel CAN (Controller Area Network) interface integration structure: It integrates four independent CAN channels, supporting parallel communication for multiple charging piles. The four independent CAN channels (can0 / can1 / can2 / ESP32_CAN) adopt a dual-ring redundancy architecture; in the event of a channel failure, the coprocessor automatically switches the routing path. Terminal multiplexing design, compatible with UART serial ports, reduces the need for external adapter modules.

[0063] Communication protocol compatibility design: The main control module automatically matches the CAN channel baud rate (adjustable from 250kbps to 1Mbps) by dynamically parsing the BMS message protocol (such as GB / T27930).

[0064] Highly integrated peripheral design: Utilizing a highly integrated single-board architecture, all functional modules (including the main control module, communication interface module, and power management module) are unified onto a single circuit board, with the board size optimized to 200mm × 270mm. This design eliminates the need for external expansion modules and achieves internal integration of core functions such as power management, multiple CAN interfaces, and network communication. The core board (RK3568 chip) manages all modules uniformly, significantly improving ease of maintenance and system reliability, and reducing potential points of failure.

[0065] Interface edge layout: All critical external interfaces (including debug serial ports, network ports, CAN terminals, etc.) are centrally located in the edge area of ​​the board. This standardized layout optimizes rack wiring efficiency, facilitates rapid installation and maintenance, and enhances adaptability.

[0066] Overall hardware configuration:

[0067] Main Control Module: Employs the RK3568 chip as the main controller, connected to the ESP32-C3 coprocessor via a PCIe bus, responsible for protocol parsing and device scheduling. Communication Interface Module: Multi-channel CAN Interface: Implements a four-channel independent CAN bus via a J9 terminal block. Serial Port Expansion: Multiplexes J9 terminal block pins to support UART (serial) communication. Terminal Block Model: JST XH2.54-10P (10A current rating). Pin Multiplexing: J9-7 / J9-8 pins switch between UART / CAN modes via a 74LVC1G157 multiplexer, controlled by the main control level. Power Management Module: Input Voltage: DC 12V (range 9V~36V), converted to 3.3V / 1.8V via onboard MP2315 chip to power RK3568 chip and peripherals; Power Protection: TVS diode connected in parallel at power input terminal, current monitoring circuit (ACS712 chip) added, when input current > 15A triggers MOSFET turn-off, response time ≤ 5ms.

[0068] Peripheral function implementation:

[0069] In charging pile system applications, the RK3568 control board uses CAN0 and CAN1 on the RK3568 pins for communication between the charging gun and the vehicle during charging, and CAN2 on the RK3568 pin for communication with the power module and power output. A functional block diagram is shown below. Figure 15 As shown. The ESP32 chip on the control board communicates with the PDU via CAN and is responsible for power distribution. It also communicates with the RK3568 via USB. The ESP32 functions as an extended CAN, as shown. Figure 16 As shown in Table 1.

[0070] Table 1 CAN Communication Path

[0071]

[0072] Human-computer interaction module ( Figure 17 ):

[0073] LVDS (Low Voltage Differential Signaling) Touchscreen: Directly connected to the RK3568 LVDS interface via a 40-pin FPC connector. Card Reader: Connected via Universal Asynchronous Receiver / Transmitter (UART) (ttyS2 is a specific serial communication interface), supporting the ISO14443 protocol.

[0074] Safety monitoring module:

[0075] Input detection: Optocoupler isolation circuit acquires 12V / 24V BMS power signal (response time <10ms) Figure 18 ADC acquisition: 12-bit ADC (built-in RK3568) monitors CC1 voltage (0~5V), with an accuracy of ±0.1%. Figure 19 Users communicate via Ethernet and 4G networks, such as... Figure 20 As shown.

[0076] This utility model includes:

[0077] The main control module includes a multi-core processor and a communication coprocessor connected via a high-speed bus. The main controller uses Rockchip RK3568 + ESP32-C3, which are connected via a PCIe bus. Rockchip RK3568 is the main controller, and ESP32-C3 is the coprocessor responsible for protocol parsing and device scheduling.

[0078] The communication interface module, integrated into the J9 terminal block, includes four independent CAN channels; multi-channel CAN interface: four independent CAN buses are implemented through the J9 terminal block. Serial port expansion: J9 terminal block pins are multiplexed to support UART (serial) communication. Terminal block model: JST XH2.54-10P (10A current rating). Pin multiplexing: J9-7 / J9-8 pins switch between UART / CAN modes via a 74LVC1G157 multiplexer, controlled by the master control level.

[0079] The power management module accepts an input voltage of DC 9–36V, which is converted to 3.3V / 1.8V via a DC-DC converter chip. A parallel TVS diode provides overvoltage protection. The input voltage range is DC 9–36V, converted to 5V and 3.3V via an SCT9339STER DC-DC chip to power peripheral circuits. The parallel TVS diode provides overvoltage protection. The input voltage is also converted to 3.3V / 1.8V via an onboard MP2315 chip to power the RK3568 and peripherals. Power protection: A TVS diode is connected in parallel at the power input terminal, and a current monitoring circuit (ACS712 chip) is added. When the input current > 15A, the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is triggered to turn off, with a response time ≤ 5ms.

[0080] This utility model also includes: a compact single-board structure integrating the main control module, communication interface module, and power management module; all external communication interfaces are centrally located on the edge area of ​​the board, including debug serial port, network port, and CAN terminal block. The communication interface module includes four independent CAN channels (can0, can1, can2, ESP32_CAN) and is configured with a redundancy switching mechanism, automatically switching the routing path by the communication coprocessor when any channel fails. An LVDS touchscreen is connected to the main control module via an FPC socket; an input detection circuit uses optocoupler isolation to acquire BMS power signals with a response time ≤10ms; the input detection circuit uses optocoupler isolation of model EL357N(B)(TA)-G to acquire BMS power signals. When BMS power is connected, the internal diode of the optocoupler lights up, and the internal transistor conducts, allowing the 3586 chip of the main control module to receive the signal. An ADC acquisition circuit monitors the CC1 voltage of the charging gun through the built-in ADC of the main control module with an accuracy of ±0.1%. The voltage of the charging gun CC1 is monitored using the ADC built into the RK3568 chip in the main control module, achieving an accuracy of 0.1%. The charging gun interface transmits data to the ADC chip via an isolation amplifier and operational amplifier chip, and the data is then acquired by the RK3568 chip in the main control module. The interface edge layout includes debugging serial ports, network ports, and terminal blocks, all located at the edge of the board to optimize rack wiring and ease of maintenance.

[0081] like Figure 14The diagram shows the overall hardware block diagram. The RK3568 core board and ESP32 are the main control modules, integrating rich functional modules and interfaces to form a complete data acquisition, control, and communication system. Main Control Module: Employing a dual-main control design with the RK3568 core board and ESP32, serving as the core for system data processing and command scheduling. Communication Interface Module: Includes a gigabit Ethernet port, 4G module, WIFI module, USB interface, LVDS interface, 485 interface, and CAN interface, responsible for information exchange between the system and external devices and networks. Power Control Module: Powered by a 12V DC power supply and high-voltage analog input, providing stable power to all modules of the system. Input Detection Circuit: Supports AC220V analog input / AC220V input detection / 6 outputs and 11 5V inputs, enabling detection of external switching quantities and high-voltage status. ADC Acquisition Circuit: Covers CC1 analog input and dual-gun TEMP analog (temperature-related analog) input to acquire key analog signals, and controls the dual-gun power supply through the motor control output. In terms of power supply logic, the power management module supplies power to the entire system. In terms of data interaction logic, the communication interface layer, input detection circuit, and ADC acquisition circuit are all connected to the main control module through corresponding interfaces. The dual main controllers collaboratively complete data processing, status judgment, and control command execution. Specifically, SDIO is an interface type based on the SD standard; LVDS is Low Voltage Differential Signaling; UART is Universal Asynchronous Receiver / Transmitter; CARD serial port is a technical solution that provides a physical serial communication interface for a computer through a specific expansion card; I2S is a serial communication interface standard for digital audio devices; RGMII is an interface specification for communication between Ethernet controllers and the physical layer; GPIO refers to General Purpose Input / Output Port; MIC refers to Microphone; NTC refers to Negative Temperature Coefficient Thermistor; ADC is Analog-to-Digital Converter; J2, J7, J6, J9, J20, J19, J22, J1, J8, J12, and J15 are different terminal blocks; P5 is one pin of a single USB port.

[0082] Figure 15 Charging Function Block Diagram: All three CAN communication interfaces are brought out by the RK3568 chip of the main control module, with clear functional divisions: 1. CAN0 and CAN1 are used for the charging process—responsible for communication between charging gun A and B and the vehicle (such as charging parameter exchange and status feedback); 2. CAN2 is used for communication between the main control module and the power module, undertaking the transmission of power output-related commands and status coordination. The FT-DCU10 is a domain controller platform.

[0083] Figure 16Master-Slave Processor Block Diagram: In the master control module, the CAN interface of the ESP32 chip connects and communicates with the PDU (Power Distribution Unit), and is responsible for the transmission of power distribution-related commands and status interaction. Simultaneously, the USB interface of the ESP32 connects to the USB interface of the RK3568 chip, which is also part of the master control module, enabling data exchange between the two. Functionally, the core role of the ESP32 in this architecture is to extend the system's CAN communication capabilities through its own CAN interface, meeting the CAN interface requirements in various scenarios.

[0084] Figure 17 Human-Machine Interaction Diagram: The display screen adopts an LVDS touchscreen design, directly connected to the LVDS interface of the main control module RK3568 via a 40-pin FPC socket, realizing display signal transmission and touch interaction functions; the card reader is connected to the system through the UART (Universal Asynchronous Receiver / Transmitter) interface of the main control module and supports the ISO14443 protocol (contactless IC card communication protocol), enabling the reading and interaction of card swipe information. RS232 is an interface.

[0085] Figure 18 Input / Output Block Diagram: The input / output detection circuit is an important component of the safety detection module. The input detection section uses an optocoupler isolation circuit to acquire the 12V / 24V BMS power signal (signal response time < 10ms) and transmits the acquired signal to the RK3568 chip in the main control module, providing the system with basic data for safety status monitoring.

[0086] Figure 19 ADC Acquisition Block Diagram: ADC acquisition is achieved through the 12-bit ADC built into the RK3568 in the main control module. The ADC chip is used to detect the CC1 voltage (0-5V), as well as temperature and insulation, and then feeds the results back to the main control module.

[0087] Figure 20 Network Communication Block Diagram: The main control module provides two Ethernet interfaces, supporting wired Ethernet network communication. Simultaneously, it connects to an external 4G wireless module via a USB interface, offering a 4G wireless communication option. These two communication methods complement each other, meeting network connectivity needs in different scenarios.

[0088] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A charging pile control board, characterized in that, include: The main control module (1), communication interface module (2) and power management module (3) are integrated in the single board structure. The main control module (1) is connected to the input detection circuit (4), and the main control module (1) has a built-in analog-to-digital converter acquisition circuit (5). The main control module (1) is used to parse the charging pile system protocol and schedule the charging pile equipment using the chipset; The communication interface module (2) is used to interact with external devices and networks through the interface; The power management module (3) is used to power the charging pile control board by means of DC power supply and target voltage analog input; The input detection circuit (4) is used to detect the external switching quantity and power-on status of the charging pile control board; The analog-to-digital converter acquisition circuit (5) is used to acquire analog signals and realize power control through the motor control output.

2. The charging pile control board according to claim 1, characterized in that, The main control module (1) includes chip P1, chip P2, chip P3, chip P4, diode D136, capacitor C50, resistor R23, capacitor C51, capacitor C478, diode D137, resistor R285, resistor R286, resistor R288, resistor R289, resistor R24 ​​and resistor R25. Wherein, one end of diode D137 is connected to one end of capacitor C478 and one end of capacitor C51, the other end of diode D137 is connected in sequence to the seventy-ninth terminal of chip P3, the other end of capacitor C478, the other end of capacitor C51, the seventy-seventh terminal of chip P3, the seventy-fifth terminal of chip P3 and one end of resistor R23, the other end of resistor R23 is connected in sequence to one end of capacitor C50 and one end of diode D136, and the other end of diode D136 is connected to the other end of capacitor C50; The forty-eighth terminal of chip P3 is connected to resistor R285, the fiftieth terminal of chip P3 is connected to resistor R286, the fifty-fourth terminal of chip P3 is connected to resistor R289, and the fifty-sixth terminal of chip P3 is connected to resistor R288. The third terminal of chip P4 is connected to resistor R24, the fifth terminal of chip P4 is connected to resistor R25, and chip P1 and chip P2 are sequentially arranged on the sides of chip P4 and chip P3.

3. A charging pile control board according to claim 1, characterized in that, The communication interface module (2) is integrated into the J9 terminal block and includes several CAN channels.

4. A charging pile control board according to claim 1, characterized in that, The power management module (3) includes: chip U2, capacitor C19, capacitor C20, capacitor C21, resistor R7, resistor R8, capacitor C22, capacitor C23, capacitor C11, diode D4, resistor R10, capacitor C24, capacitor C25, inductor L1, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C18, resistor R6, resistor R9, resistor R3, diode D3 and capacitor C17; Wherein, the first end of the chip U2 is connected to one end of the capacitor C11; the second end of the chip U2 is sequentially connected to one end of the resistor R7, one end of the capacitor C21, one end of the capacitor C20, and one end of the capacitor C19; the other end of the capacitor C19 is sequentially connected to the other end of the capacitor C20 and the other end of the capacitor C21; the third end of the chip U2 is sequentially connected to one end of the capacitor C22, one end of the resistor R8, and the other end of the resistor R7; the fourth end of the chip U2 is connected to one end of the capacitor C23; the other end of the capacitor C23 is sequentially connected to the ninth end of the chip U2, the other end of the capacitor C22, and the other end of the resistor R8. The eighth terminal of chip U2 is connected in sequence to the other end of capacitor C11, the negative terminal of diode D4, and the first terminal of inductor L1. The seventh terminal of chip U2 is connected in sequence to the positive terminal of diode D4, one end of capacitor C13, one end of capacitor C14, one end of capacitor C15, and one end of capacitor C16. The second terminal of inductor L1 is connected in sequence to the other end of capacitor C13, the other end of capacitor C14, the other end of capacitor C15, the other end of capacitor C16, one end of resistor R6, one end of capacitor C18, and one end of resistor R3. The other end of resistor R6 is connected in sequence to the other end of capacitor C18, one end of resistor R9, and the fifth terminal of chip U2. The other end of resistor R3 is connected in sequence to one end of diode D3 and one end of capacitor C17. The other end of diode D3 is connected to the other end of capacitor C17. The sixth terminal of the chip U2 is connected in sequence to one end of the resistor R10 and one end of the capacitor C25. The other end of the resistor R10 is connected to one end of the capacitor C24, and the other end of the capacitor C24 is connected to the other end of the capacitor C25.

5. A charging pile control board according to claim 1, characterized in that, The power management module (3) further includes: chip U3, capacitor C34, capacitor C35, capacitor C36, resistor R16, resistor R17, capacitor C37, capacitor C38, capacitor C27, diode D6, resistor R19, capacitor C39, capacitor C40, inductor L2, capacitor C26, capacitor C29, capacitor C30, capacitor C31, capacitor C33, resistor R15, resistor R18, resistor R12, diode D5 and capacitor C32; Wherein, the first end of the chip U3 is connected to one end of the capacitor C27, the second end of the chip U3 is sequentially connected to one end of the capacitor C36, one end of the capacitor C35 and one end of the capacitor C34, the other end of the capacitor C34 is sequentially connected to the other end of the capacitor C35 and the other end of the capacitor C36, the third end of the chip U3 is sequentially connected to one end of the capacitor C37, one end of the resistor R17 and one end of the resistor R16, the fourth end of the chip U3 is connected to one end of the capacitor C38, and the other end of the capacitor C38 is sequentially connected to the ninth end of the chip U3, the other end of the capacitor C37 and the other end of the resistor R17; The eighth terminal of chip U3 is sequentially connected to the other end of capacitor C27, the negative terminal of diode D6, and the first terminal of inductor L2. The seventh terminal of chip U3 is sequentially connected to the positive terminal of diode D6, one end of capacitor C26, one end of capacitor C29, one end of capacitor C30, and one end of capacitor C31. The second terminal of inductor L2 is sequentially connected to the other end of capacitor C26, the other end of capacitor C29, the other end of capacitor C30, the other end of capacitor C31, one end of resistor R15, one end of capacitor C33, and one end of resistor R12. The other end of resistor R15 is sequentially connected to the other end of capacitor C33, one end of resistor R18, and the fifth terminal of chip U3. The other end of resistor R12 is sequentially connected to one end of diode D5 and one end of capacitor C32. The other end of diode D5 is connected to the other end of capacitor C32. The sixth terminal of the chip U3 is connected in sequence to one end of the resistor R19 and one end of the capacitor C40. The other end of the resistor R19 is connected to one end of the capacitor C39, and the other end of the capacitor C39 is connected to the other end of the capacitor C40.

6. A charging pile control board according to claim 1, characterized in that, The input detection circuit (4) includes chip U90, resistor R472, resistor R474, capacitor C371, resistor R475 and resistor R473. Wherein, the first end of the chip U90 is connected to one end of the resistor R474 and one end of the resistor R472 in sequence, and the second end of the chip U90 is connected to the other end of the resistor R474; The fourth terminal of the chip U90 is connected in sequence to one end of the resistor R475, one end of the resistor R473 and one end of the capacitor C371, and the other end of the capacitor C371 is connected to the third terminal of the chip U90.

7. A charging pile control board according to claim 1, characterized in that, The analog-to-digital converter acquisition circuit (5) includes chip IC1, resistors R830, R829, R831, capacitors C100 and C99, resistors R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, and R94; Wherein, the thirteenth terminal of the chip IC1 is connected to one end of the resistor R830, the twelfth terminal of the chip IC1 is connected to one end of the resistor R829, the eleventh terminal of the chip IC1 is connected to one end of the resistor R831, and the other end of the resistor R830 is connected to the other end of the resistor R829 and the other end of the resistor R831 in sequence. The seventh terminal of chip IC1 is connected to one end of resistor R84, the other end of resistor R84 is connected to the eighth terminal of chip IC1, the thirty-fourth terminal of chip IC1 is connected to resistor R86, the thirty-third terminal of chip IC1 is connected to resistor R87, the thirty-second terminal of chip IC1 is connected to resistor R88, the thirty-first terminal of chip IC1 is connected to one end of resistor R89, the other end of resistor R89 ​​is connected to resistor R85, the thirty-eighth terminal of chip IC1 is connected to resistor R91, and the thirty-seventh terminal of chip IC1 is connected to resistor R92. The side of the chip IC1 is also provided with the capacitor C100, the capacitor C99, the resistor R90, the resistor R93 and the resistor R94 in sequence, and the resistor R90 and the resistor R93 are connected in series.

8. A charging pile control board according to claim 1, characterized in that, The analog-to-digital converter acquisition circuit (5) further includes: diodes D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24 and D25. In this configuration, diodes D13, D14, D15, and D16 are connected in parallel; diodes D17, D18, D19, and D20 are connected in parallel; diodes D21, D22, D23, and D24 are connected in parallel; and diode D25 is disposed on one side of diode D24.

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