Circuit for preventing reverse electric leakage of external connector
By placing a level conversion chip and diode between the GPIO and UART interfaces of the electronic device and the external connector, the problem of reverse leakage of the external connector is solved, ensuring the normal operation of the chip and avoiding abnormal situations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHANGZHI ZHUOYI HENGTONG INFORMATION SECURITY CO LTD
- Filing Date
- 2025-04-28
- Publication Date
- 2026-05-15
AI Technical Summary
The GPIO and UART interfaces of existing electronic devices are susceptible to reverse leakage from external devices via external connectors when not powered on, which can lead to chip malfunctions or failure to power on.
A level conversion chip and a diode are placed between the interface of the first chip and the external connector to form isolation. Signal transmission is carried out when the chip is powered on normally, and leakage current is isolated when the chip is not powered on to avoid affecting the chip.
It effectively prevents reverse current leakage from external devices when electronic devices are turned off, preventing chip malfunctions such as failure to power on or abnormal function, and ensuring the normal operation of electronic devices.
Smart Images
Figure CN224249358U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic technology, and in particular to a circuit for preventing reverse leakage of external connectors. Background Technology
[0002] Electronic devices are increasingly used in people's work and life, and their functions are constantly expanding. Electronic devices can usually be connected to external devices through external interfaces to expand their functions. However, for some external interfaces, if isolation measures are not taken, current from the external device can leak back into the electronic device through the external interface when the electronic device is turned off, causing the electronic device to malfunction.
[0003] Specifically, many chips on the circuit boards of electronic devices (such as computer motherboards) have GPIO (General-Purpose Input / Output) interfaces, UART (Universal Asynchronous Receiver / Transmitter) interfaces, etc. If these interfaces are to be used as external interfaces, they need to be electrically connected to external connectors to connect to external devices. Taking a microcontroller unit (MCU) as an example... Figure 1 As shown, the GPIO / UART interfaces of the existing microcontroller unit on the circuit board are directly connected to external connectors, and external devices are electrically connected to the circuit board through these external connectors. Because the external connectors are directly connected to the GPIO / UART interfaces of the microcontroller unit, in the event of leakage, the current from the external device will flow through the external connectors according to… Figure 1 If the direction of the middle arrow C leaks onto the circuit board, it may cause some functions on the circuit board to fail or even prevent the circuit board from working properly.
[0004] The reasons for the above situation will be explained in detail below. Normally, when the device is powered off (not powered on), the voltages of the microcontroller unit (MCU) will maintain their states according to the chip's design requirements, with some power supply voltages needing to remain at 0V. When leakage occurs, current from the external device flows back into the MCU through the external connector. The power supply voltage, which should be 0V according to the design requirements, will no longer remain 0V but will exhibit a certain voltage, i.e., leakage voltage. The leakage voltage that the MCU can withstand varies depending on the chip's internal design. When the leakage voltage exceeds the chip's tolerance range and reaches a value that causes the chip to malfunction, it may lead to failure to meet the chip's timing requirements during power-on, resulting in failure to power on or malfunctions in some functions.
[0005] Other chips with similar GPIO or UART interfaces will also have the same problem.
[0006] Therefore, how to prevent chips connected to external devices via external connectors through GPIO and / or UART interfaces from being affected by reverse leakage current from external devices through external connectors when the device is powered off is an urgent technical problem to be solved. Summary of the Invention
[0007] The purpose of this invention is to provide a circuit that prevents reverse leakage from external connectors, thus avoiding the impact of reverse leakage from external devices when the chips connected to external devices via external connectors through GPIO interfaces and / or UART interfaces are not powered on.
[0008] To achieve the above objectives, this utility model provides a circuit for preventing reverse leakage of an external connector, comprising a first chip, a level conversion chip, a diode, and an external connector for connecting to an external device. The first chip has an interface, which is one of a GPIO interface and a UART interface. The level conversion chip includes a first port and a second port. The first port includes a first power supply voltage pin and a plurality of first data input / output pins. The second port includes a second power supply voltage pin and a plurality of second data input / output pins. The interface is connected to the plurality of first data input / output pins, and the first power supply voltage pin is connected to the anode of the diode. The plurality of second data input / output pins are connected to the external connector, and the second power supply voltage pin is connected to the cathode of the diode.
[0009] Preferably, the first chip is a microcontroller unit.
[0010] Preferably, the first chip is one of a central processing unit, a bridge chip, a serial port chip, and a field-programmable gate array chip.
[0011] Preferably, the first power supply voltage pin is connected to a first power supply, and the second power supply voltage pin is connected to a second power supply, wherein the output voltages of the first power supply and the second power supply are the same.
[0012] Preferably, the first power supply voltage pin is connected to a first power supply, and the first power supply is also grounded through a first capacitor; the second power supply voltage pin is connected to a second power supply, and the second power supply is also grounded through a parallel circuit of a second capacitor and a first resistor.
[0013] Preferably, the level conversion chip further includes an output enable pin, which is connected to the second power supply via a second resistor.
[0014] Preferably, the diode is a Schottky diode.
[0015] Preferably, the diode is of type LBAT54AWT1G.
[0016] Preferably, the level conversion chip is model SGM4564YTQM12G / TR.
[0017] The beneficial effects of this utility model are as follows: The circuit for preventing reverse leakage of the external connector of this utility model forms an isolation between the interface of the first chip (such as GPIO interface, UART interface) and the external connector for connecting external devices by setting a level conversion chip and a diode between the interface of the first chip (such as GPIO interface, UART interface) and the external connector for connecting external devices. During normal power-on operation, the level conversion chip transmits signals between the first chip and the external connector. When the first chip is not powered on, the level conversion chip and diode isolate the leakage current flowing into the external device through the external connector, preventing the leakage current from flowing to the first chip and affecting the first chip, causing it to malfunction, such as timing abnormalities or functional abnormalities. Furthermore, when the circuit for preventing reverse leakage of the external connector is applied to electronic devices, it can prevent the current on the external device from leaking into the electronic device in reverse through the external connector when the electronic device is powered off, thus preventing the electronic device from malfunctioning, such as not turning on or having partial functional abnormalities. Attached Figure Description
[0018] To further understand the features and technical content of this utility model, please refer to the following detailed description and accompanying drawings. However, the drawings are provided for reference and illustration only and are not intended to limit the scope of this utility model. In the drawings,
[0019] Figure 1 This is a schematic diagram showing the connection between the GPIO / UART interface of an existing microcontroller unit and an external connector.
[0020] Figure 2 This is a schematic diagram of the circuit for preventing reverse leakage of the external connector according to an embodiment of the present invention.
[0021] Figure 3 This is a circuit wiring diagram of the level conversion chip and diode in the circuit for preventing reverse leakage of the external connector according to an embodiment of the present invention. Detailed Implementation
[0022] To further illustrate the technical means and effects of this utility model, the following detailed description is provided in conjunction with the preferred embodiments of this utility model and their accompanying drawings.
[0023] This invention provides a circuit to prevent reverse leakage from external connectors. It is used to prevent chips that require external devices to be connected via external connectors for GPIO and / or UART interfaces from being affected by reverse leakage from external devices when the device is not powered on. When applied to electronic devices, it can prevent current from external devices from leaking into the electronic device via external connectors when the electronic device is powered off, thus preventing abnormalities such as failure to power on or partial malfunctions of the electronic device.
[0024] like Figure 2 As shown, the circuit 10 for preventing reverse leakage of the external connector according to this invention includes a first chip 11, a level conversion chip 12, a diode 13, and an external connector 14 for connecting to an external device 20. The interface 110 of the first chip 11 is connected to the external connector 14 via the level conversion chip 12, and then the external connector 14 is connected to the external device 20.
[0025] Specifically, the first chip 11 has an interface 110, which is one of a GPIO interface and a UART interface. The level conversion chip 12 includes a first port B and a second port A. The first port B includes a first power supply voltage pin VCCB and a plurality of first data input / output pins B1-Bn. The second port A includes a second power supply voltage pin VCCA and a plurality of second data input / output pins A1-An. The interface 110 is connected to the plurality of first data input / output pins B1-Bn. The first power supply voltage pin VCCB is connected to the anode of the diode 13. The plurality of second data input / output pins A1-An are connected to the external connector 14, and the second power supply voltage pin VCCA is connected to the cathode of the diode 13.
[0026] With this configuration, when the circuit board containing circuit 10 is not powered on, i.e., when the first chip 11 is not powered on, the current from the external device 20 will leak through the external connector 14 to the second port A of the level conversion chip 12. However, since the diode 13 is unidirectional, the current cannot flow from the second power supply voltage pin VCCA of the level conversion chip 12 to the first power supply voltage pin VCCB, meaning the leakage voltage will not be applied to the first power supply voltage pin VCCB. At this time, the level conversion chip 12 is not powered and has not yet started working, and the leakage current cannot flow from its second port A to its first port B. Communication between its multiple first data input / output pins B1-Bn and multiple second data input / output pins A1-An is impossible. Therefore, the level conversion chip 12 and the diode 13 can isolate the leakage current, preventing it from flowing to the first chip 11, thereby preventing the first chip 11 from being affected by reverse leakage from the external device 20 through the external connector 14. Normal communication can only occur between the plurality of first data input / output pins B1-Bn and the plurality of second data input / output pins A1-An when the first chip 11 is working properly.
[0027] It should be noted that the interface 110 of the first chip 11 is one of the GPIO interface and the UART interface. When the first chip 11 has multiple interfaces 110, the multiple interfaces 110 can be multiple GPIO interfaces, multiple UART interfaces, or both GPIO interfaces and UART interfaces. Each interface 110 can be configured as described above, that is, the level conversion chip 12 and the diode 13 can be set between each interface 110 and its corresponding external connector 14 to isolate leakage current.
[0028] In a preferred embodiment, the first chip 11 may be a microcontroller unit (MCU). In other embodiments, the first chip 11 may also be a central processing unit (CPU), a bridge chip, a serial port chip, a field-programmable gate array (FPGA) chip, etc.
[0029] Furthermore, the first power supply voltage pin VCCB and the second power supply voltage pin VCCA are connected to different power supplies. Specifically, the first power supply voltage pin VCCB can be connected to a first power supply, and the second power supply voltage pin VCCA can be connected to a second power supply. In a preferred embodiment, the first power supply and the second power supply have the same output voltage, for example, both are 3.3V.
[0030] Figure 3 This is a circuit wiring diagram of a specific embodiment of the level conversion chip 12 and diode 13 in the circuit 10 for preventing reverse leakage of the external connector according to this utility model. Figure 3 In the embodiment shown, the level conversion chip 12 includes a first port B and a second port A. The first port B includes a first power supply voltage pin VCCB and a plurality of first data input / output pins B1-B4. The second port A includes a second power supply voltage pin VCCA and a plurality of second data input / output pins A1-A4.
[0031] Among them, the plurality of first data input / output pins B1-B4 are used to connect to the first chip 11 ( Figure 3 Not shown in the figure, in this embodiment, the first chip 11 can be an FPGA chip) with a UART interface, transmitting UART_BK1RX_FPGA4TX, UART_BK1TX_FPGA4RX, UART_BK2RX_FPGA7TX, and UART_BK2TX_FPGA7RX signals; the plurality of second data input / output pins A1-A4 are used to connect to an external connector 14 ( Figure 3 (Not shown in the image), transmitting UART_BK1RX_FPGA4TX_C, UART_BK1TX_FPGA4RX_C, UART_BK2RX_FPGA7TX_C, and UART_BK2TX_FPGA7RX_C signals.
[0032] The first power supply voltage pin VCCB is connected to the anode of the diode 13 and the first power supply VCC_3V3_K, and the first power supply VCC_3V3_K is also grounded through the first capacitor C1; the second power supply voltage pin VCCA is connected to the cathode of the diode 13 and the second power supply VCC_3V3_I, and the second power supply VCC_3V3_I is also grounded through the parallel circuit of the second capacitor C2 and the first resistor R1.
[0033] In one embodiment, when the circuit 10 for preventing reverse leakage of the external connector is disposed on the motherboard, the first power supply VCC_3V3_K and the second power supply VCC_3V3_I come from different 3.3V power supply interfaces on the motherboard.
[0034] In addition, the output enable pin OE of the level conversion chip 12 is connected to the second power supply VCC_3V3_I via the second resistor R2, and the EP pin and ground pin GND of the level conversion chip 12 are grounded.
[0035] Figure 3The working principle of the level conversion chip 12 shown is as follows: when powered on, the level conversion chip 12 transmits signals between the first chip 11 and the external connector 14; when not powered on, the level conversion chip 12 no longer transmits signals. Even if the current from the external device 20 leaks to the second port A of the level conversion chip 12 through the external connector 14, since the diode 13 is unidirectional, the current cannot flow from the second power supply voltage pin VCCA of the level conversion chip 12 to the first power supply voltage pin VCCB, and the level conversion chip 12 will not transmit signals, thereby isolating leakage current.
[0036] Preferably, the diode 13 can be implemented using a Schottky diode, such as a Schottky diode of model LBAT54AWT1G, but it is not limited to this. The diode 13 can also be implemented in other forms, as long as it can achieve unidirectional conduction to isolate leakage current.
[0037] In one embodiment, the level conversion chip 12 is model SGM4564YTQM12G / TR, but is not limited thereto.
[0038] Therefore, the circuit for preventing reverse leakage from the external connector of this utility model forms isolation between the first chip and the external connector by setting a level conversion chip and a diode between the interface of the first chip (such as a GPIO interface or a UART interface) and the external connector for connecting external devices. During normal power-on operation, the level conversion chip transmits signals between the first chip and the external connector. When the first chip is not powered on, the level conversion chip and the diode isolate the leakage current flowing into the external device through the external connector, preventing the leakage current from flowing to the first chip and affecting it, causing abnormalities such as timing abnormalities or functional abnormalities. Furthermore, when the circuit for preventing reverse leakage from the external connector is applied to electronic devices, it can prevent the current from the external device from leaking back into the electronic device through the external connector when the electronic device is powered off, thus preventing abnormalities such as the electronic device not turning on or partial functional abnormalities.
[0039] Preferably, the circuit for preventing reverse leakage of external connectors of this invention can be applied to circuit boards with external GPIO and UART interfaces.
[0040] Preferably, the circuit for preventing reverse leakage of external connectors in this invention can be set on the motherboard, which can ensure that the chips on the motherboard that need to be connected to external devices through external connectors via GPIO interfaces and UART interfaces are not affected by reverse leakage of external devices through external connectors. This avoids abnormal situations such as the motherboard not booting or some functions malfunctioning due to failure to meet chip timing requirements when powered on, which may be caused by such reverse leakage.
[0041] As described above, those skilled in the art can make various other corresponding changes and modifications based on the technical solution and concept of this utility model, and all such changes and modifications should fall within the protection scope of the claims of this utility model.
Claims
1. A circuit for preventing reverse leakage current from an external connector, characterized in that, The device includes a first chip, a level shifting chip, a diode, and an external connector for connecting to an external device. The first chip has an interface, which is either a GPIO interface or a UART interface. The level shifting chip includes a first port and a second port. The first port includes a first power supply voltage pin and a plurality of first data input / output pins. The second port includes a second power supply voltage pin and a plurality of second data input / output pins. The interface is connected to the plurality of first data input / output pins. The first power supply voltage pin is connected to the anode of the diode. The plurality of second data input / output pins are connected to the external connector. The second power supply voltage pin is connected to the cathode of the diode.
2. The circuit for preventing reverse leakage of the external connector according to claim 1, characterized in that, The first chip is a microcontroller unit.
3. The circuit for preventing reverse leakage of the external connector according to claim 1, characterized in that, The first chip is one of the central processing unit, bridge chip, serial port chip, and field programmable gate array chip.
4. The circuit for preventing reverse leakage of the external connector according to claim 1, characterized in that, The first power supply voltage pin is connected to a first power supply, and the second power supply voltage pin is connected to a second power supply. The output voltages of the first power supply and the second power supply are the same.
5. The circuit for preventing reverse leakage of the external connector according to claim 1, characterized in that, The first power supply voltage pin is connected to a first power supply, which is also grounded through a first capacitor; the second power supply voltage pin is connected to a second power supply, which is also grounded through a parallel circuit of a second capacitor and a first resistor.
6. The circuit for preventing reverse leakage of the external connector according to claim 5, characterized in that, The level conversion chip also includes an output enable pin, which is connected to the second power supply via a second resistor.
7. The circuit for preventing reverse leakage of the external connector according to claim 1, characterized in that, The diode is a Schottky diode.
8. The circuit for preventing reverse leakage of the external connector according to claim 7, characterized in that, The diode is model LBAT54AWT1G.
9. The circuit for preventing reverse leakage of the external connector according to claim 1, characterized in that, The level conversion chip is model SGM4564YTQM12G / TR.