Chip packaging structure and circuit board
By setting a double-layer metal heat sink that passes through the bare die body in the chip packaging structure, the problem of low heat dissipation efficiency of the bottom chip is solved, and efficient heat dissipation and structural stability are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2025-04-24
- Publication Date
- 2026-05-15
AI Technical Summary
In a stacked chip configuration, the bottom-layer chip has lower heat dissipation efficiency, which can cause it to warp when overheated, affecting performance.
In the chip packaging structure, a heat sink is provided on the side of the die body away from the first die, and it passes through the die body and connects to the first die. The heat sink with a double-layer metal structure is used to improve the bonding force and thermal conductivity.
Effective heat dissipation prevents warping caused by heat buildup, improving the heat dissipation performance of the underlying chip and the stability of the overall packaging structure.
Smart Images
Figure CN224250153U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, specifically to a chip packaging structure and a circuit board. Background Technology
[0002] In related technologies, in order to increase the number of chips integrated and achieve high-density chip integration, multiple chips are stacked.
[0003] However, in stacked chips, the heat dissipation efficiency of the bottom chip is relatively low. When the bottom chip overheats, the internal film layer of the bottom chip will warp, affecting the performance of the bottom chip.
[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Utility Model Content
[0005] The purpose of this application is to provide a chip packaging structure that can improve the heat dissipation performance of the underlying chip.
[0006] To solve the above problems, the technical solution of this application is as follows:
[0007] In a first aspect, this application proposes a chip packaging mechanism, comprising:
[0008] Interconnect layer;
[0009] The first die is bonded to one side of the interconnect layer; and
[0010] The second die includes a die body and a heat sink. The die body is bonded to the side of the first die away from the interconnect layer. A portion of the heat sink is located on the side of the die body away from the first die, and another portion of the heat sink passes through the die body and is connected to the first die.
[0011] In one embodiment of this application, the die body is provided with a first thermal conductive hole, which penetrates the die body along the thickness direction of the chip packaging structure;
[0012] The heat sink includes:
[0013] A first metal layer covers the side of the die body away from the first die and the inner wall of the first heat-conducting hole. A via is provided in the portion of the first metal layer within the first heat-conducting hole, and the via exposes a portion of the first die.
[0014] A second metal layer covers the side of the first metal layer away from the die body and the via, wherein the portion of the second metal layer located within the via is connected to the first die;
[0015] Wherein, the bonding force between the first metal layer and the non-metallic film layer is the first bonding force, the bonding force between the second metal layer and the non-metallic film layer is the second bonding force, the first bonding force is greater than the second bonding force, and the thermal conductivity of the second metal layer is greater than the thermal conductivity of the first metal layer.
[0016] In one embodiment of this application, the first die includes a main body and a first pin, wherein the first pin is disposed on the side of the main body close to the die body;
[0017] The heat sink includes:
[0018] The second pin is located on the side of the die body near the main body and is connected to the first pin;
[0019] A heat-conducting portion is disposed within the bare die body and connected to the second pin; and
[0020] A heat dissipation section is located on the side of the die body away from the first die and is connected to the heat conduction section.
[0021] In one embodiment of this application, the main body includes:
[0022] A first substrate is located between the interconnect layer and the second die;
[0023] A thin-film transistor is disposed on the side of the first substrate near the second bare die;
[0024] A heat-conducting element is disposed on the side of the thin-film transistor away from the first substrate and is insulated from the thin-film transistor;
[0025] A passivation layer covers the side of the thermal conductive component away from the first substrate. The first pin is provided on the side of the passivation layer away from the first substrate. The passivation layer is provided with a second thermally conductive hole, which exposes a portion of the thermal conductive component. The first pin is connected to the thermal conductive component through the second thermally conductive hole.
[0026] In one embodiment of this application, the first substrate is a glass substrate.
[0027] In one embodiment of this application, the interconnect layer includes:
[0028] Second substrate;
[0029] A device layer is disposed on the side of the second substrate near the first die; and
[0030] A first connection layer is disposed on the side of the device layer away from the second substrate, and the first connection layer is electrically connected to the device layer;
[0031] The first die is connected to the first interconnect layer.
[0032] In one embodiment of this application, the device layer includes:
[0033] An inductor, wherein a first portion of the inductor is disposed on the side of the second substrate close to the first die, a second portion of the inductor passes through the second substrate, and a third portion of the inductor is disposed on the side of the second substrate away from the first die;
[0034] A first insulating layer is disposed on the side of the second substrate near the first bare die and covers a first portion of the inductor;
[0035] The first connection layer is disposed on the side of the first insulating layer away from the second substrate, and the first connection layer is electrically connected to the inductor.
[0036] In one embodiment of this application, the third portion of the inductor is covered with a protective layer on the side away from the second substrate.
[0037] In one embodiment of this application, the device layer further includes wiring, which is disposed on the side of the second substrate close to the first bare die;
[0038] The interconnect layer further includes a second connection layer, which is disposed on the side of the second substrate away from the first die, and is electrically connected to the trace;
[0039] The thickness of the second connection layer is greater than the thickness of the third part of the inductor.
[0040] In one embodiment of this application, the device layer further includes a resistor disposed on the side of the second substrate near the first die and spaced apart from the inductor, and the first insulating layer covers the resistor;
[0041] The first connection layer includes a third pin and a fourth pin spaced apart, wherein the third pin is connected to the inductor and the fourth pin is connected to the resistor;
[0042] The first die has a fifth pin and a sixth pin spaced apart on the side near the interconnect layer. The fifth pin is connected to the third pin, and the sixth pin is connected to the fourth pin. The first die is electrically connected to the fifth pin and the fourth pin, respectively.
[0043] In one embodiment of this application, the device layer further includes a capacitor disposed on the side of the second substrate near the first die and spaced apart from the inductor, and the first insulating layer covers the capacitor;
[0044] The first connection layer also includes a seventh pin, which is connected to the capacitor;
[0045] The chip packaging structure further includes a third die, which is disposed on the side of the first insulating layer away from the second substrate. The third die is spaced apart from the first die, and an eighth pin is provided on the side of the third die near the interconnect layer. The seventh pin is connected to the eighth pin.
[0046] In one embodiment of this application, the second substrate is a glass substrate.
[0047] Secondly, this application proposes a circuit board including a chip packaging structure, the chip packaging structure including an interconnect layer, a first die and a second die, the first die being bonded to one side of the interconnect layer; the second die including a die body and a heat sink, the die body being bonded to the side of the first die away from the interconnect layer, a portion of the heat sink being disposed on the side of the die body away from the first die, and another portion of the heat sink passing through the die body and connected to the first die.
[0048] In this application, a first die and a second die are stacked sequentially on one side of the interconnect layer. The second die includes a die body and a heat sink. This application provides a heat sink on the side of the die body away from the first die, and the heat sink passes through the die body and connects to the first die. The heat sink in this application can dissipate the heat generated by the first die in a timely manner, preventing overheating and warping of the underlying chip due to the inability to dissipate heat effectively, thus improving the heat dissipation performance of the underlying chip. Attached Figure Description
[0049] Figure 1 This is a schematic diagram of one embodiment of the chip packaging structure of this application;
[0050] Figure 2 yes Figure 1 A schematic diagram of an embodiment of the first and second dies in the chip packaging structure described above;
[0051] Figure 3 yes Figure 2 A schematic diagram of an embodiment of the first bare die shown;
[0052] Figure 4 yes Figure 1 A schematic diagram of one embodiment of the interconnect layer is shown. Detailed Implementation
[0053] The terms used in this specification and claims have the meanings that are commonly understood by one of ordinary skill in the art to which this application pertains. The terms used in this specification and claims are for the purpose of facilitating the description and understanding of this application only, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.
[0054] This application discloses a circuit board, which includes a circuit board body and a chip packaging structure. The chip packaging structure can be fixed to the circuit board body by soldering or by surface mount technology. No limitation is made on the connection method between the circuit board body and the chip packaging structure.
[0055] Please see Figure 1 This application also proposes a chip packaging structure 100. The chip packaging structure 100 includes an interconnect layer 10, a first die 20, and a second die 30. The first die 20 is bonded to one side of the interconnect layer 10. The second die 30 includes a die body 31 and a heat sink 32. The die body 31 is bonded to the side of the first die 20 away from the interconnect layer 10. A portion of the heat sink 32 is disposed on the side of the die body 31 away from the first die 20. Another portion of the heat sink 32 passes through the die body 31 and is connected to the first die 20.
[0056] In this application, a first die 20 and a second die 30 are stacked sequentially on one side of the interconnect layer 10. The second die 30 includes a die body 31 and a heat sink 32. This application provides a heat sink 32 on the side of the die body 31 away from the first die 20, and the heat sink 32 passes through the die body 31 and connects to the first die 20. The heat sink 32 in this application can dissipate the heat generated by the first die 20 in a timely manner, preventing the underlying chip from overheating and warping due to the inability to dissipate heat from the first die 20, thus improving the heat dissipation performance of the underlying chip.
[0057] It is important to understand that a bare die, also known as a bare chip, is a small piece of integrated circuit made of semiconductor material that has not been packaged. In other words, it is a chip that has been cut and tested but has not been packaged.
[0058] Optionally, the heat sink 32 may be made of a metallic material. Materials for the heat sink 32 may include metals such as copper, molybdenum, titanium, aluminum, silver, zinc, and tungsten.
[0059] Optionally, the heat sink 32 may be made of a non-metallic material. Materials for the heat sink 32 include silicon carbide, graphite, etc.
[0060] Optionally, the heat sink 32 can also be made of materials such as aluminum nitride.
[0061] Please see Figure 2Optionally, the die body 31 is provided with a first thermally conductive hole. The first thermally conductive hole penetrates the die body 31 along the thickness direction Z of the chip package structure 100.
[0062] The heat sink 32 includes a first metal layer 321 and a second metal layer 322. The first metal layer 321 covers the side of the die body 31 away from the first die 20 and the inner wall of the first heat-conducting hole. The portion of the first metal layer 321 located within the first heat-conducting hole has a through-hole. The through-hole exposes a portion of the first die 20.
[0063] The second metal layer 322 covers the side of the first metal layer 321 away from the die body 31 and the via. The portion of the second metal layer 322 located within the via connects to the first die 20. The bonding force between the first metal layer 321 and the non-metallic film layer is a first bonding force. The bonding force between the second metal layer 322 and the non-metallic film layer is a second bonding force. The first bonding force is greater than the second bonding force. The thermal conductivity of the second metal layer 322 is greater than the thermal conductivity of the first metal layer 321.
[0064] In this embodiment, to improve the heat dissipation effect of the chip package structure 100, the heat sink 32 is made of a metal material with a high thermal conductivity. Taking copper as an example, copper has good thermal conductivity, but its adhesion to non-metallic films is weak. When the copper heat sink 32 is placed on the die body 31, the film layer on the side of the die body 31 closest to the copper heat sink 32 is a non-metallic insulating film layer. The copper heat sink 32 and the die body 31 are prone to peeling, leading to a decrease in the heat dissipation effect of the chip package structure 100. To improve the adhesion between the heat sink 32 and the die body 31, this embodiment sets the heat sink 32 as a double-layer metal structure. The first metal layer 321 has a strong adhesion to the non-metallic film layer, and the second metal layer 322 has a high thermal conductivity. Because the first metal layer 321 has a strong adhesion to the non-metallic layer, it is less likely to peel off. The material of the first metal layer 321 can be molybdenum, titanium, or their alloys. Because the second metal layer 322 has a high thermal conductivity, it can quickly conduct and dissipate heat, thus improving the heat dissipation performance of the chip package structure 100. The material of the second metal layer 322 can be one of copper, aluminum, silver, or their alloys.
[0065] Please see Figure 2 Optionally, the first die 20 includes a main body 21 and a first pin 22, with the first pin 22 located on the side of the main body 21 close to the die body 31.
[0066] The heat sink 32 includes a second pin 323, a heat-conducting part 324, and a heat-dissipating part 325. The second pin 323 is located on the side of the die body 31 near the main body 21 and is connected to the first pin 22. The heat-conducting part 324 is located inside the die body 31 and is connected to the second pin 323. The heat-dissipating part 325 is located on the side of the die body 31 away from the first die 20 and is connected to the heat-conducting part 324.
[0067] In this embodiment, the heat sink 32 is connected to the first pin 22 of the first die 20 via the second pin 323, thereby dissipating the heat generated by the first die 20 along the heat dissipation path formed by the first pin 22, the second pin 323, the heat-conducting part 324 and the heat dissipation part 325, which improves the heat dissipation efficiency of the first die 20 in the chip package structure 100, thereby improving the heat dissipation performance of the underlying chip.
[0068] Optionally, in this application, the first die 20 can be a glass-based die, and the second die 30 can be a silicon-based die. It is understood that the substrate material of the second die 30 is silicon, and the substrate material of the first die 20 is glass.
[0069] Please see Figure 3 Optionally, the main body 21 includes a first substrate 211, a thin film transistor 212, a heat-conducting element 213, and a passivation layer 214.
[0070] A first substrate 211 is located between the interconnect layer 10 and the second die 30. A thin-film transistor 212 is disposed on the side of the first substrate 211 closest to the second die 30. A heat-conducting element 213 is disposed on the side of the thin-film transistor 212 away from the first substrate 211 and is insulated from the thin-film transistor 212. A passivation layer 214 covers the side of the heat-conducting element 213 away from the first substrate 211. A first pin 22 is provided on the side of the passivation layer 214 away from the first substrate 211. A second heat-conducting via is provided in the passivation layer 214. The second heat-conducting via exposes a portion of the heat-conducting element 213. The first pin 22 is connected to the heat-conducting element 213 through the second heat-conducting via.
[0071] In this embodiment, by providing a heat-conducting element 213 in the passivation layer 214, the heat-conducting element 213 can quickly transfer the internal heat of the first die 20 to the outside of the first die 20 and discharge it outside the chip packaging structure 100 along the heat sink 32. This can reduce the heat accumulation inside the first die 20 and reduce the peeling phenomenon of the internal film layer of the first die 20, thereby further improving the heat dissipation performance of the chip packaging structure 100.
[0072] Optionally, the first substrate 211 is a glass substrate.
[0073] In this embodiment, the first die 20 can be fabricated using panel manufacturing processes. Panel manufacturing processes refer to the processes used in the fabrication of display panels, array substrates, etc. This allows for the stacking of multiple layers of glass-based chips and silicon-based chips.
[0074] Please see Figure 4 Optionally, the interconnect layer 10 includes a second substrate 11, a device layer 12, and a first interconnect layer 13. The device layer 12 is disposed on the side of the second substrate 11 closest to the first die 20. The first interconnect layer 13 is disposed on the side of the device layer 12 furthest from the second substrate 11. The first interconnect layer 13 is electrically connected to the device layer 12. The first die 20 is connected to the first interconnect layer 13.
[0075] In this embodiment, the first die 20 and the second die 30 can be integrated onto the interconnect layer 10, and then the interconnect layer 10, in which the first die 20 and the second die 30 are integrated, can be integrated onto the circuit board body. The first die 20 is bonded to and connected to the interconnect layer 10. The second die 30 is bonded to the first die 20, thereby connecting to the interconnect layer 10. The stacking arrangement of the first die 20 and the second die 30 improves the utilization rate of the circuit board unit space, allowing more transistors to be placed on a unit area of the circuit board, thus improving the performance of the circuit board.
[0076] Optionally, device layer 12 includes inductor 121 and first insulating layer 122.
[0077] A first portion 121a of inductor 121 is disposed on the side of the second substrate 11 near the first die 20, a second portion 121b of inductor 121 passes through the second substrate 11, and a third portion 121c of inductor 121 is disposed on the side of the second substrate 11 away from the first die 20. A first insulating layer 122 is disposed on the side of the second substrate 11 near the first die 20 and covers the first portion 121a of inductor 121. A first connecting layer 13 is disposed on the side of the first insulating layer 122 away from the second substrate 11. The first connecting layer 13 is electrically connected to inductor 121.
[0078] In this embodiment, the device layer 12 includes an inductor 121, which can be integrated into the interconnect layer 10, saving the space required to set the inductor 121 on the circuit board body. This can reduce the size of the circuit board or increase the number of chips on the circuit board, thereby improving the performance of the circuit board.
[0079] Optionally, the third portion 121c of the inductor 121 is covered with a protective layer 14 on the side away from the second substrate 11.
[0080] In this embodiment, since the third portion 121c of the inductor 121 is exposed to the outside of the second substrate 11, a protective layer 14 can be provided on the side of the third portion 121c of the inductor 121 away from the second substrate 11 to reduce the erosion of the third portion 121c by external water and oxygen. The protective layer 14 not only isolates the third portion 121c of the inductor 121 from external water and oxygen, but also isolates the inductor 121 from the circuit board, reducing the influence of other devices on the circuit board on the inductor 121. The material of the protective layer 14 can be ink, such as screen printing ink. The material of the protective layer 14 can also be inorganic materials such as silicon oxide and silicon nitride; no limitation is made on the material of the protective layer 14 here.
[0081] Optionally, device layer 12 may also include traces 125. The traces 125 are disposed on the side of the second substrate 11 near the first die 20.
[0082] The interconnect layer 10 also includes a second connection layer 15. The second connection layer 15 is disposed on the side of the second substrate 11 away from the first die 20. The second connection layer 15 is electrically connected to the trace 125. The thickness L of the second connection layer 15 is greater than the thickness H of the third portion 121c of the inductor 121.
[0083] In this embodiment, the second connection layer 15 is used to electrically connect the interconnect layer 10 and the internal circuitry of the circuit board body. The interconnect layer 10 is bonded to the circuit board via the second connection layer 15. Since a protective layer 14 is required on the side of the third portion 121c of the inductor 121 away from the second substrate 11, the thickness L of the second connection layer 15 needs to be greater than the thickness H of the third portion 121c of the inductor 121. This is to prevent the protective layer 14 from interfering with the bonding of the interconnect layer 10 to the circuit board, thus preventing bonding failure. Interference means that when the sum of the thickness H of the third portion 121c of the inductor 121 and the thickness of the protective layer 14 is greater than the thickness L of the second connection layer 15, the third portion 121c of the inductor 121 and the protective layer 14 are located between the second substrate 11 and the circuit board body when the second connection layer 15 is bonded to the pins on the circuit board body, causing the second connection layer 15 to be unable to contact the pins on the circuit board body, resulting in bonding failure.
[0084] Optionally, the sum of the thickness H of the third portion 121c of the inductor 121 and the thickness of the protective layer 14 is less than or equal to the thickness L of the second interconnect layer 15. In this case, it can be ensured that the third portion 121c of the inductor 121 and the protective layer 14 will not interfere with the bonding of the interconnect layer 10, thereby improving the stability of the circuit board structure.
[0085] Optionally, the second substrate 11 is a silicon-based substrate.
[0086] Optionally, the second substrate 11 is a glass substrate.
[0087] In this embodiment, when the second substrate 11 is a glass substrate, the interconnect layer 10 can be fabricated using panel manufacturing processes. Panel manufacturing processes refer to processes for display panels, array substrates, etc. When the material of the second substrate 11 is glass, the second portion 121b of the inductor 121 passes through the glass substrate, which can improve the Q value of the inductor 121, resulting in lower dielectric loss and greater energy efficiency in high-frequency applications, thereby improving the performance of the inductor 121.
[0088] Optionally, device layer 12 further includes a resistor 123. The resistor 123 is disposed on the side of the second substrate 11 near the first die 20 and spaced apart from the inductor 121. The first insulating layer 122 covers the resistor 123.
[0089] The first connection layer 13 includes a third pin 131 and a fourth pin 132 spaced apart. The third pin 131 is connected to the inductor 121. The fourth pin 132 is connected to the resistor 123.
[0090] The first die 20 has a fifth pin 23 and a sixth pin 24 spaced apart on the side closest to the interconnect layer 10. The fifth pin 23 is connected to the third pin 131. The sixth pin 24 is connected to the fourth pin 132. The first die 20 is electrically connected to the fifth pin 23 and the fourth pin 132, respectively.
[0091] In this embodiment, the device layer 12 includes a resistor 123, which can be integrated into the interconnect layer 10, saving the space required to set the resistor 123 on the circuit board body. This achieves the effect of reducing the size of the circuit board or increasing the number of chips on the circuit board, thereby improving the performance of the circuit board.
[0092] Optionally, device layer 12 also includes a capacitor 124. The capacitor 124 is disposed on the side of the second substrate 11 near the first die 20 and spaced apart from the inductor 121. A first insulating layer 122 covers the capacitor 124.
[0093] The first connection layer 13 also includes a seventh pin 133. The seventh pin 133 is connected to the capacitor 124.
[0094] The chip package structure 100 also includes a third die 40. The third die 40 is disposed on the side of the first insulating layer 122 away from the second substrate 11. The third die 40 is spaced apart from the first die 20. An eighth pin 41 is provided on the side of the third die 40 near the interconnect layer 10. A seventh pin 133 is connected to the eighth pin 41.
[0095] In this embodiment, the device layer 12 includes a capacitor 124, which can be integrated into the interconnect layer 10, saving the space required to set the capacitor 124 on the circuit board body. This achieves the effect of reducing the size of the circuit board or increasing the number of chips on the circuit board, thereby improving the performance of the circuit board.
[0096] In this embodiment, the interconnect layer 10 can be bonded to either the stacked first die 20 and the second die 30, or a separately disposed third die 40. No limitation is made on the devices bonded to the interconnect layer 10. The third die 40 can be a glass-based chip or a silicon-based chip; no limitation is made on either.
[0097] This application employs a glass stacking process to integrate at least one of the capacitor 124, inductor 121, and resistor 123 within the interconnect layer 10, reducing the space required for integrating the capacitor 124, inductor 121, or resistor 123 on the circuit board. This achieves the effect of reducing the size of the circuit board and improving its space utilization.
[0098] The specific embodiments of this application have been described in detail above. The embodiments disclosed above are merely preferred embodiments of this application. Those skilled in the art can make many modifications and improvements without departing from the concept of this application. All such modifications and improvements fall within the scope of protection defined by the claims of this application.
Claims
1. A chip packaging structure, characterized in that, include: Interconnect layer; The first die is bonded to one side of the interconnect layer; as well as The second die includes a die body and a heat sink. The die body is bonded to the side of the first die away from the interconnect layer. A portion of the heat sink is located on the side of the die body away from the first die, and another portion of the heat sink passes through the die body and is connected to the first die.
2. The chip packaging structure as described in claim 1, characterized in that, The die body is provided with a first heat-conducting hole, which penetrates the die body along the thickness direction of the chip packaging structure. The heat sink includes: A first metal layer covers the side of the die body away from the first die and the inner wall of the first heat-conducting hole. A via is provided in the portion of the first metal layer within the first heat-conducting hole, and the via exposes a portion of the first die. A second metal layer covers the side of the first metal layer away from the die body and the via, wherein the portion of the second metal layer located within the via is connected to the first die; Wherein, the bonding force between the first metal layer and the non-metallic film layer is the first bonding force, the bonding force between the second metal layer and the non-metallic film layer is the second bonding force, the first bonding force is greater than the second bonding force, and the thermal conductivity of the second metal layer is greater than the thermal conductivity of the first metal layer.
3. The chip packaging structure as described in claim 1, characterized in that, The first die includes a main body and a first pin, wherein the first pin is disposed on the side of the main body close to the die body; The heat sink includes: The second pin is located on the side of the die body near the main body and is connected to the first pin; A heat-conducting portion is disposed within the bare die body and connected to the second pin; and A heat dissipation section is located on the side of the die body away from the first die and is connected to the heat conduction section.
4. The chip packaging structure as described in claim 3, characterized in that, The main body includes: A first substrate is located between the interconnect layer and the second die; A thin-film transistor is disposed on the side of the first substrate near the second bare die; A heat-conducting element is disposed on the side of the thin-film transistor away from the first substrate and is insulated from the thin-film transistor; A passivation layer covers the side of the thermal conductive component away from the first substrate. The first pin is provided on the side of the passivation layer away from the first substrate. The passivation layer is provided with a second thermally conductive hole, which exposes a portion of the thermal conductive component. The first pin is connected to the thermal conductive component through the second thermally conductive hole.
5. The chip packaging structure as described in claim 4, characterized in that, The first substrate is a glass substrate.
6. The chip packaging structure as described in any one of claims 1-5, characterized in that, The interconnection layer includes: Second substrate; A device layer is disposed on the side of the second substrate near the first die; and A first connection layer is disposed on the side of the device layer away from the second substrate, and the first connection layer is electrically connected to the device layer; The first die is connected to the first interconnect layer.
7. The chip packaging structure as described in claim 6, characterized in that, The device layer includes: An inductor, wherein a first portion of the inductor is disposed on the side of the second substrate close to the first die, a second portion of the inductor passes through the second substrate, and a third portion of the inductor is disposed on the side of the second substrate away from the first die; A first insulating layer is disposed on the side of the second substrate near the first bare die and covers a first portion of the inductor; The first connection layer is disposed on the side of the first insulating layer away from the second substrate, and the first connection layer is electrically connected to the inductor.
8. The chip packaging structure as described in claim 7, characterized in that, The third portion of the inductor is covered with a protective layer on the side away from the second substrate.
9. The chip packaging structure as described in claim 7, characterized in that, The device layer also includes wiring, which is disposed on the side of the second substrate close to the first die; The interconnect layer further includes a second connection layer, which is disposed on the side of the second substrate away from the first die, and is electrically connected to the trace; The thickness of the second connection layer is greater than the thickness of the third part of the inductor.
10. The chip packaging structure as described in claim 7, characterized in that, The device layer further includes a resistor disposed on the side of the second substrate near the first die and spaced apart from the inductor, and the first insulating layer covers the resistor; The first connection layer includes a third pin and a fourth pin spaced apart, wherein the third pin is connected to the inductor and the fourth pin is connected to the resistor; The first die has a fifth pin and a sixth pin spaced apart on the side near the interconnect layer. The fifth pin is connected to the third pin, and the sixth pin is connected to the fourth pin. The first die is electrically connected to the fifth pin and the fourth pin, respectively.
11. The chip packaging structure as described in claim 7, characterized in that, The device layer also includes a capacitor, which is disposed on the side of the second substrate near the first die and spaced apart from the inductor, and the first insulating layer covers the capacitor; The first connection layer also includes a seventh pin, which is connected to the capacitor; The chip packaging structure further includes a third die, which is disposed on the side of the first insulating layer away from the second substrate. The third die is spaced apart from the first die, and an eighth pin is provided on the side of the third die near the interconnect layer. The seventh pin is connected to the eighth pin.
12. The chip packaging structure as described in claim 6, characterized in that, The second substrate is a glass substrate.
13. A circuit board, characterized in that, Includes the chip packaging structure as described in any one of claims 1-12.