Low noise amplifier circuit, low noise amplifier and radio frequency system

Abstract

The utility model discloses a low-noise amplifier circuit, a low-noise amplifier and a radio frequency system, and the low-noise amplifier circuit comprises a plurality of gain subunits which are connected in parallel; the output end of the control circuit is connected with the controlled ends of the plurality of gain subunits, and the control circuit is used for outputting enable signals to the plurality of gain subunits and controlling the plurality of gain subunits to work; and the input impedance compensation circuit is connected with the plurality of gain subunits in parallel, and the input impedance compensation circuit is used for compensating the input impedance of the plurality of gain subunits. According to the utility model, the problem that when the equivalent transconductance is changed to adjust the gain, the input impedance is influenced and the requirement of input impedance matching cannot be met at any time is solved.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit design, and in particular to a low-noise amplifier circuit, a low-noise amplifier, and a radio frequency system. Background Technology

[0002] The low-noise amplifier (LNA) is a key module in an RF receiving system. When a weak signal is received, the gain is increased to improve system sensitivity and suppress noise in subsequent stages; when a strong signal is received, the gain needs to be reduced to prevent saturation in subsequent stages.

[0003] Common gain control methods involve altering the transistor size to change the gain. Taking a source-degenerate negative feedback LNA as an example, both the gain and input impedance of the structure are related to the transistor size. When the transistor size changes, the transconductance of the circuit changes accordingly, and the parasitic capacitance cgs, i.e., the gate-source capacitance, also changes. Therefore, when adjusting the gain by changing the equivalent transconductance, the input impedance is also affected, making it impossible to always meet the input impedance matching requirements. This necessitates redesigning the matching network, which not only increases the complexity of the circuit design but may also adversely affect other circuit performance aspects. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this utility model is to provide a low-noise amplifier circuit, a low-noise amplifier and an RF system to solve the problem that when the equivalent transconductance is changed to adjust the gain, the input impedance will also be affected, and the input impedance matching requirements cannot be met at all times.

[0005] The technical solution of this utility model is as follows:

[0006] A low-noise amplifier circuit includes:

[0007] Multiple gain sub-units, wherein the multiple gain sub-units are connected in parallel;

[0008] A control circuit, the output of which is connected to the controlled terminals of the multiple gain sub-units, the control circuit being used to output enable signals to the multiple gain sub-units to control the operation of the multiple gain sub-units;

[0009] An input impedance compensation circuit is provided, which is connected in parallel with multiple gain sub-units. The input impedance compensation circuit is used to compensate the input impedance of the multiple gain sub-units.

[0010] Optionally, the low-noise amplifier circuit further includes a power input terminal and a power output terminal, with the input terminals of the plurality of gain sub-units connected to the power input terminal and the output terminals of the plurality of gain sub-units connected to the power output terminal.

[0011] Optionally, the input impedance compensation circuit includes a DC blocking element, a first compensation element, and a second compensation element. One end of the DC blocking element and one end of the first compensation element are connected to the power input terminal, the other end of the DC blocking element and one end of the second compensation element are connected, the other end of the first compensation element is grounded, and the other end of the second compensation element is connected to the power output terminal.

[0012] Optionally, the first compensation element is a first capacitor, the second compensation element is a first resistor, the DC blocking element is a second capacitor, the first end of the first capacitor and the first end of the second capacitor are connected to the power input terminal, the second end of the first capacitor is grounded, the second end of the second capacitor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the power output terminal.

[0013] Optionally, the gain subunit includes:

[0014] Multiple transistors, the gates of which are all connected to the output of the control circuit.

[0015] Optionally, the output terminal of the control circuit includes an enable output terminal and a power output terminal. The plurality of transistors include a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The gate of the second NMOS transistor and the gate of the first PMOS transistor are connected to the power output terminal. The source of the first PMOS transistor is used to connect to the power supply. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The drain of the first NMOS transistor is connected to the drain of the second PMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is grounded. The gates of the first NMOS transistor and the second PMOS transistor are connected to the enable output terminal.

[0016] Optionally, the number of the gain sub-units is 2. N There are , where N is a positive integer.

[0017] This invention also proposes a low-noise amplifier, including the low-noise amplifier circuit described above.

[0018] This invention also proposes a radio frequency system, including the low-noise amplifier described above.

[0019] This invention employs a low-noise amplifier circuit comprised of multiple gain sub-units, a control circuit, and an input impedance compensation circuit. The multiple gain sub-units are connected in parallel. The output of the control circuit is connected to the controlled terminals of the multiple gain sub-units, and the control circuit outputs enable signals to the multiple gain sub-units to control their operation. The input impedance compensation circuit is also connected in parallel with the multiple gain sub-units, compensating for their input impedance. Thus, this solution divides the gain unit into multiple gain sub-units and compensates for their input impedance through the input impedance compensation circuit, thereby meeting the input impedance matching requirements. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 This is a functional module schematic diagram of an embodiment of the low-noise amplifier circuit of this utility model.

[0022] Figure 2 This is a schematic diagram of the circuit structure of an embodiment of the low-noise amplifier circuit of this utility model.

[0023] Figure 3 This is a schematic diagram of the circuit structure of another embodiment of the low-noise amplifier circuit of this utility model.

[0024] Explanation of reference numerals in the attached figures: 10, gain sub-unit; 20, control circuit; 30, input impedance compensation circuit; R1, first resistor; C1, first capacitor; C2, second capacitor; Mn1, first NMOS transistor; Mn2, second NMOS transistor; Mp1, first PMOS transistor; Mp2, second PMOS transistor. Detailed Implementation

[0025] To make the objectives, technical solutions, and effects of this utility model clearer and more explicit, the present utility model will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0026] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of this utility model involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0027] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0028] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0029] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0030] The low-noise amplifier (LNA) is a key module in an RF receiving system. When a weak signal is received, the gain is increased to improve system sensitivity and suppress noise in subsequent stages; when a strong signal is received, the gain needs to be reduced to prevent saturation in subsequent stages.

[0031] Common gain control methods involve altering the transistor size to change the gain. Taking a source-degenerate negative feedback LNA as an example, both the gain and input impedance of the structure are related to the transistor size. When the transistor size changes, the transconductance of the circuit changes accordingly, and the parasitic capacitance cgs, i.e., the gate-source capacitance, also changes. Therefore, when adjusting the gain by changing the equivalent transconductance, the input impedance is also affected, making it impossible to always meet the input impedance matching requirements. This necessitates redesigning the matching network, which not only increases the complexity of the circuit design but may also adversely affect other circuit performance aspects.

[0032] To address the above problems, this utility model proposes a low-noise amplifier circuit.

[0033] Reference Figure 1 In one embodiment, the low-noise amplifier circuit includes:

[0034] Multiple gain sub-units 10 are connected in parallel;

[0035] The control circuit 20 has its output terminal connected to the controlled terminals of the multiple gain sub-units 10. The control circuit 20 is used to output enable signals to the multiple gain sub-units 10 to control the multiple gain sub-units 10 to work.

[0036] An input impedance compensation circuit 30 is provided, which is connected in parallel with a plurality of the gain sub-units 10. The input impedance compensation circuit 30 is used to compensate the input impedance of the plurality of the gain sub-units 10.

[0037] In this embodiment, multiple gain sub-units 10 can be derived from a single gain unit, which can be composed of multiple transistors. A single gain unit is decomposed into multiple identical parallel gain sub-units 10, for example, into eight sub-units. The transistor size of each gain sub-unit 10 is 1 / 8 of the transistor size in maximum gain mode. Therefore, under the same voltage bias, the transconductance provided by each sub-unit is 1 / 8 of the total transconductance. Furthermore, by adjusting the number or operating state of the parallel gain sub-units 10, flexible gain control can be achieved, allowing for finer gain adjustment to adapt to different signal strengths and application requirements. Multiple parallel gain sub-units 10 can effectively reduce the overall system noise, as the noise of each gain sub-unit 10 cancels each other out, thereby improving the signal-to-noise ratio and enabling the amplifier to maintain good performance even in low-signal environments. The parallel structure can also improve the amplifier's linearity and reduce distortion. The parallel connection of multiple gain sub-units 10 can share the input signal, thereby reducing the workload of each gain sub-unit 10 and improving overall linear performance. The specific number of gain sub-units 10 can be selected according to actual conditions and user needs.

[0038] The control circuit 20 can be a digital signal processor (DSP), microcontroller, or field-programmable gate array (FPGA) to control the bias voltages of the transistors in the multiple gain sub-units 10. Specifically, the control circuit 20 can generate different control signals based on a preset program or externally input digital signals. These control signals are converted into analog voltage signals by a digital-to-analog converter, thereby adjusting the bias voltages of the transistors. It is understood that digital signals are less susceptible to noise and interference, and the bias voltages controlled by digital circuits are more stable than those controlled by analog control circuits 20. Digital circuits can monitor and adjust the bias voltages in real time through a feedback mechanism to ensure the stability of the transistor operating point. The input impedance compensation circuit 30 can be composed of electronic components such as capacitors and resistors to compensate the input impedance of the gain sub-units 10, avoiding input impedance mismatch during gain switching, ensuring the stability of input impedance matching across the entire gain range, and improving the stability, gain, and bandwidth of the low-noise amplifier.

[0039] This utility model's technical solution constructs a low-noise amplifier circuit using multiple gain sub-units 10, a control circuit 20, and an input impedance compensation circuit 30. The multiple gain sub-units 10 are connected in parallel. The output terminal of the control circuit 20 is connected to the controlled terminal of the multiple gain sub-units 10, and the control circuit 20 outputs an enable signal to the multiple gain sub-units 10 to control their operation. The input impedance compensation circuit 30 is connected in parallel with the multiple gain sub-units 10 and compensates for the input impedance of the multiple gain sub-units 10. Thus, this solution divides the gain unit into multiple gain sub-units 10 and compensates for the input impedance of the gain sub-units 10 through the input impedance compensation circuit 30, thereby meeting the input impedance matching requirements.

[0040] Reference Figure 2 In one embodiment, the low-noise amplifier circuit further includes a power input terminal and a power output terminal, with the input terminals of the plurality of gain sub-units 10 connected to the power input terminal and the output terminals of the plurality of gain sub-units 10 connected to the power output terminal.

[0041] In this embodiment, multiple gain sub-units 10 are disposed between the power input terminal and the power output terminal. The power output terminal and power input terminal of the low-noise amplifier circuit can be used to connect to an external power supply to ensure the normal operation of the low-noise amplifier. (Refer to...) Figure 2 The power output terminals are Vin and Vout.

[0042] In one embodiment, the input impedance compensation circuit 30 includes a DC blocking element, a first compensation element, and a second compensation element. One end of the DC blocking element and one end of the first compensation element are connected to the power input terminal, the other end of the DC blocking element and one end of the second compensation element are connected, the other end of the first compensation element is grounded, and the other end of the second compensation element is connected to the power output terminal.

[0043] In this embodiment, the input impedance compensation circuit 30 can be composed of a DC blocking element, a first compensation element, and a second compensation element. The DC blocking element prevents DC signals from passing through while allowing AC signals to pass, thus avoiding the influence of subsequent circuits (such as feedback circuits) on the DC bias and maintaining the transistor at its optimal operating point. The first and second compensation elements are used to achieve a good match between the imaginary and real parts. It is understood that when a transistor is operating, its input and output impedances are typically complex numbers, containing a real part (resistive component) and an imaginary part (reactant component). The real part mainly affects power consumption and transmission efficiency, while the imaginary part is related to energy storage and release, leading to signal phase changes. At different operating frequencies, the impedance characteristics of the transistor will change significantly, which may lead to problems such as signal reflection, gain reduction, and noise figure deterioration. In this embodiment, by reasonably selecting the parameters of the first and second compensation elements and connecting them to the circuit in an appropriate manner, the total impedance of the circuit can be changed. The first and second compensation elements can be a compensation capacitor and a compensation resistor. The compensation capacitor can provide capacitive reactance to compensate for the inductive reactance of the transistor; the compensation resistor can adjust the real part of the impedance. In this way, the input and output impedances of the amplifier are well matched with the impedances of the signal source and the load at a specific operating frequency, that is, the real parts are equal and the imaginary parts are opposites of each other.

[0044] Furthermore, referring to Figure 2 In one exemplary technology, the first compensation element is a first capacitor C1, the second compensation element is a first resistor R1, and the DC blocking element is a second capacitor C2. The first terminals of the first capacitor C1 and the second capacitor C2 are connected to the power input terminal. The second terminal of the first capacitor C1 is grounded, and the second terminal of the second capacitor C2 is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to the power output terminal. In this embodiment, the first compensation element is specifically the first capacitor C1, and the second compensation element is specifically the first resistor R1. In this embodiment, parallel compensation can be used. The parallel capacitor can provide a low-impedance path, allowing high-frequency signals to pass smoothly; the parallel resistor can reduce the equivalent value of the input impedance. By reasonably selecting the values ​​of the capacitor and resistor, the real and imaginary parts of the input impedance can be matched with the signal source impedance. The specific circuit structure can be referred to... Figure 2Alternatively, the input impedance of the transistor can be compensated by setting the first capacitor C1 and the first resistor R1 in series.

[0045] In one embodiment, the gain subunit 10 includes:

[0046] Multiple transistors, the gates of which are all connected to the output of the control circuit 20.

[0047] In this embodiment, the gain subunit 10 can be composed of multiple transistors, specifically including NMOS transistors and PMOS transistors. The gates of the multiple transistors are connected to the output terminal of the control circuit 20. The transistors can be turned on or off by the signal output by the control circuit 20, thereby adjusting the gain of the low noise amplifier.

[0048] Reference Figure 2 and Figure 3 In one embodiment, the output terminal of the control circuit 20 includes an enable output terminal and a power output terminal. The plurality of transistors include a first NMOS transistor Mn1, a second NMOS transistor Mn2, a first PMOS transistor Mp1, and a second PMOS transistor Mp2. The gate of the second NMOS transistor Mn2 and the gate of the first PMOS transistor Mp1 are connected to the power output terminal. The source of the first PMOS transistor Mp1 is connected to the power supply. The drain of the first PMOS transistor Mp1 is connected to the source of the second PMOS transistor Mp2. The drain of the first NMOS transistor Mn1 is connected to the drain of the second PMOS transistor Mp2. The source of the first NMOS transistor Mn1 is connected to the drain of the second NMOS transistor Mn2. The source of the second NMOS transistor Mn2 is grounded. The gates of the first NMOS transistor Mn1 and the second PMOS transistor Mp2 are connected to the enable output terminal.

[0049] In this embodiment, Vn0, Vp0, Vn1, and Vp1 can be the power output terminals of the control circuit 20, used to control the first NMOS transistor Mn1, the second NMOS transistor Mn2, the first PMOS transistor Mp1, and the second PMOS transistor Mp2 to be in a normally on state; while the enable output terminal of the control circuit 20 can also be connected to the gate of the first NMOS transistor Mn1 and the gate of the second PMOS transistor Mp2, and the control circuit 20 can output an enable signal to control the first NMOS transistor Mn1 and the second PMOS transistor Mp2 to be off. Furthermore, other MOS transistors and inverters can also be set in the gain subunit 10, as detailed in the following reference. Figure 3When the enable signal en_0=1, en_0_1=0, en_0_0=1, and the first NMOS transistor Mn1 and the second PMOS transistor Mp2 are turned on. When the enable signal en_0=0, en_0_1=01, en_0_0=0, and the first NMOS transistor Mn1 and the second PMOS transistor Mp2 are turned off. The voltage VDD can be set to 1V by default. Additionally, an inverter is placed between the output of the control circuit 20 and the gates of multiple transistors to output different signals to the gates of the first NMOS transistor Mn1 and the second PMOS transistor Mp2. See [link to details]. Figure 3 .

[0050] In one embodiment, the number of gain sub-units 10 is 2. N There are , where N is a positive integer.

[0051] In this embodiment, the number of gain sub-units 10 is set to 2. N Because the gain becomes half the original value for every halving of the number of conduction sub-units, setting the number of gain sub-units 10 in this way can better control the gain level of the low-noise amplifier.

[0052] To better illustrate the technical concept of this solution, combined with Figures 1 to 3 The content of the above embodiments will be described as follows:

[0053] Taking a source-degenerate negative feedback LNA as an example, its circuit gain and input impedance formulas are as follows:

[0054] ;

[0055] ;

[0056] Among them, A v Z is the circuit gain. in Q is the input impedance. in The Q-factor represents the quality factor of the input series resonant network, reflecting the degree of energy loss in the resonant circuit or system. A higher Q-factor indicates better circuit selectivity and energy efficiency. m C represents the transconductance of the first NMOS transistor Mn1 and the first PMOS transistor Mp1. gs Here, s represents the gate-source capacitance of the first NMOS transistor Mn1 and the first PMOS transistor Mp1, and L represents the Laplace variable. s and L g for Figure 2 The inductance value of the intermediate inductor. From this formula, it can be seen that the gain and input impedance of the source-degenerate negative feedback structure are both related to the transistor size.

[0057] This scheme decomposes the LNA circuit into multiple identical parallel gain sub-units 10. Taking eight as an example, the transistor size of each gain sub-unit 10 is 1 / 8 of the transistor size in the maximum gain mode. Therefore, under the same voltage bias, the transconductance provided by each gain sub-unit 10 is 1 / 8 of the total transconductance. The bias voltage of the transistors in each gain sub-unit 10 is controlled by digital circuitry to control the on and off of the corresponding gain sub-unit 10 module. The equivalent transconductance is controlled by controlling the number of parallel gain sub-units 10 that are turned on. For example, when all eight gain sub-units 10 are turned on, the equivalent transconductance provides a maximum gain of 24dB. When only four sub-circuits are turned on, the equivalent transconductance is halved, and the corresponding gain is reduced by 6dB.

[0058] The specific on / off control method of each gain sub-unit 10 is as follows: when the enable signal en=1, the switch controlling the bias voltage is turned on, and the common gate transistor is biased in the normal working state; when the enable signal en=0, the switch controlling the bias is turned off, the gates of the NMOS and PMOS common gate transistors are biased at 0V and 1V respectively, the common gate transistor is turned off, and the sub-circuit is turned off.

[0059] The eight gain subunits 10 can be controlled by four enable signals, see reference. Figure 2 For example, en_0 controls unitite <0> en_1 controls unit <1> en_2 controls unite <2> ,unite <3> en_3 control sub-circuit unite <4> to unite <7> Among them, unite <0> to unite <7> These represent 8 gain sub-units 10 respectively. Detailed control logic can be found in the table below:

[0060]

[0061] Furthermore, this scheme uses a compensation circuit consisting of a first resistor R1, a first capacitor C1, and a second capacitor C2 to compensate for the input impedance. The second capacitor C2 acts as a DC blocking capacitor, effectively breaking the circuit in DC. Therefore, during DC analysis, the feedback is disconnected, and it does not affect the DC bias of the original circuit. According to the input impedance formula, when the gain changes, the number of parallel sub-units decreases proportionally to the number of conducting sub-units, decreasing by a factor that cannot be quantified, thus changing the input impedance. Simulations show that both the real and imaginary parts decrease. Adding a real part can be achieved by connecting a resistor in series, and adding an imaginary part can be achieved by connecting a capacitor in parallel (the actual resistance also affects the imaginary part, and the capacitor also affects the real part). Simulations demonstrate that the first capacitor C1 and the first resistor R1 work together to satisfy input matching. Thus, the low-noise amplifier circuit in this scheme can meet the input impedance matching requirements when adjusting the gain by changing the equivalent transconductance.

[0062] This invention also proposes a low-noise amplifier.

[0063] In one embodiment, the low-noise amplifier includes the low-noise amplifier circuit described above. It is understood that since the low-noise amplifier of this invention uses the aforementioned low-noise amplifier circuit, the embodiments of the low-noise amplifier of this invention include all the technical solutions of all embodiments of the aforementioned low-noise amplifier circuit, and the achieved technical effects are completely identical, and will not be repeated here.

[0064] This utility model also proposes a radio frequency system.

[0065] In one embodiment, the radio frequency system includes the low-noise amplifier as described above. It is understood that, since the radio frequency system of this invention uses the aforementioned low-noise amplifier, the embodiments of the radio frequency system of this invention include all the technical solutions of all the embodiments of the aforementioned low-noise amplifier, and the achieved technical effects are exactly the same, and will not be repeated here.

[0066] It should be understood that the application of this utility model is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A low noise amplifier circuit, characterized by include: Multiple gain sub-units, wherein the multiple gain sub-units are connected in parallel; A control circuit, the output of which is connected to the controlled terminals of the multiple gain sub-units, the control circuit being used to output enable signals to the multiple gain sub-units to control the operation of the multiple gain sub-units; An input impedance compensation circuit is provided, which is connected in parallel with multiple gain sub-units. The input impedance compensation circuit is used to compensate the input impedance of the multiple gain sub-units.

2. The low noise amplifier circuit of claim 1, wherein, The low-noise amplifier circuit further includes a power input terminal and a power output terminal. The input terminals of the plurality of gain sub-units are connected to the power input terminal, and the output terminals of the plurality of gain sub-units are connected to the power output terminal.

3. The low noise amplifier circuit of claim 2, wherein, The input impedance compensation circuit includes a DC blocking element, a first compensation element, and a second compensation element. One end of the DC blocking element and one end of the first compensation element are connected to the power input terminal. The other end of the DC blocking element and one end of the second compensation element are connected. The other end of the first compensation element is grounded, and the other end of the second compensation element is connected to the power output terminal.

4. The low noise amplifier circuit of claim 3, wherein, The first compensation element is a first capacitor, the second compensation element is a first resistor, the DC blocking element is a second capacitor, the first end of the first capacitor and the first end of the second capacitor are connected to the power input terminal, the second end of the first capacitor is grounded, the second end of the second capacitor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the power output terminal.

5. The low noise amplifier circuit of claim 1, wherein, The gain subunit includes: Multiple transistors, the gates of which are all connected to the output of the control circuit.

6. The low noise amplifier circuit of claim 5, wherein, The output terminal of the control circuit includes an enable output terminal and a power output terminal. The plurality of transistors include a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The gate of the second NMOS transistor and the gate of the first PMOS transistor are connected to the power output terminal. The source of the first PMOS transistor is used to connect to the power supply. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The drain of the first NMOS transistor is connected to the drain of the second PMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is grounded. The gates of the first NMOS transistor and the second PMOS transistor are connected to the enable output terminal.

7. The low noise amplifier circuit of claim 1, wherein, The number of gain subunits is 2 N where N is a positive integer.

8. A low noise amplifier, characterized by Includes the low-noise amplifier circuit as described in any one of claims 1-7.

9. A radio frequency system, characterized by Including the low-noise amplifier as described in claim 8.

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