PCB (printed circuit board) structure of multichannel DDR (double data rate) particles

Abstract

The utility model discloses a PCB board structure of multichannel DDR particles, comprising a PCB board body, the front side and the back side of the PCB board body are both provided with DDR particles, and the DDR particles arranged on the front side of the PCB board body and the DDR particles arranged on the back side of the PCB board body are overlapped on a projection area of the PCB board body. According to the scheme of the utility model, when the space of the PCB is limited, especially when multi-channel DDR particles need to be placed, the space of the PCB can be effectively utilized by placing the DDR particles on the front side and the back side in an overlapping manner. When the number of layers and the total thickness of the PCB are limited, the multi-channel DDR particles can still be successfully wired through the design. Compared with the method for solving the problem of insufficient wiring space by increasing the number of layers of the PCB or using a high-order HDI technology, the method has the advantages that the processing cost of the PCB can be remarkably reduced, the problems of manufacturing difficulty and yield reduction possibly caused by increasing the number of layers or adopting a complex HDI technology are avoided, and the processing yield is improved.

Description

Technical Field

[0001] This utility model generally relates to the field of PCB design and manufacturing technology. More specifically, this utility model relates to a PCB board structure for multi-channel DDR chips. Background Technology

[0002] With the rapid development of information technology, electronic devices are increasingly demanding high-capacity, high-speed read / write memory. Multi-channel DDR memory chips are widely used in various high-performance electronic systems due to their high bandwidth and high density characteristics. However, achieving high-density layout and routing of multi-channel DDR chips on a PCB, especially under space constraints, poses a severe challenge to PCB design.

[0003] Currently, traditional PCB design methods used in the industry to address these challenges mainly include: First, increasing the number of physical layers on the PCB to provide more routing space to meet the complex signal connection requirements of multi-channel DDR chips. Second, adopting high-density interconnect (HDI) design, using technologies such as micro-blind vias and buried vias to achieve higher routing density within a limited number of board layers. However, increasing the number of physical layers on the PCB directly leads to an increase in PCB thickness, affecting the product's thinness and portability. At the same time, the increase in the number of layers also significantly increases the PCB manufacturing cost and may lead to a decrease in production yield due to increased process complexity. This method is particularly unsuitable for products with specific board thickness standards if the layer stack design to meet high-speed signal quality requirements cannot provide sufficient routing channels. High-density interconnect (HDI) design places extremely high demands on the process capabilities of PCB manufacturers, typically requiring the use of specific high-end board manufacturers for processing, which not only significantly increases PCB manufacturing costs but also extends the production cycle. In addition, in order to achieve fine lines, high-end HDI processes often require the use of thin PP (prepreg) sheets, which may result in excessively narrow impedance control lines, thereby increasing the loss of other high-speed signals during transmission and affecting signal integrity.

[0004] In view of this, there is an urgent need to provide a PCB board structure for multi-channel DDR chips in order to control PCB board thickness, reduce production costs, shorten manufacturing cycle, and ensure excellent signal quality. Utility Model Content

[0005] In order to at least solve one or more of the technical problems mentioned above, this utility model proposes a PCB board structure for multi-channel DDR chips in several aspects.

[0006] This utility model provides a PCB board structure for multi-channel DDR chips, including a PCB board body. DDR chips are disposed on both the front and back sides of the PCB board body. The DDR chips disposed on the front side of the PCB board body and the DDR chips disposed on the back side of the PCB board body overlap in the projection area of ​​the PCB board body.

[0007] In some embodiments, the DDR chip is an eight-channel DDR chip, wherein the eight-channel DDR chip includes an upper four-channel chip disposed on the front side of the PCB board body and a lower four-channel chip disposed on the back side of the PCB board body.

[0008] In some embodiments, the upper four-channel particles and the lower four-channel particles correspond one-to-one at their respective positions on the PCB board body.

[0009] In some embodiments, the PCB board body adopts a stacked structure, which includes an upper stacked structure and a lower stacked structure.

[0010] In some embodiments, electrical connections between signals of DDR chips located on the front side of the PCB body are achieved through wiring layers and vias within the upper stacked structure.

[0011] In some embodiments, electrical connections between signals of DDR chips disposed on the back side of the PCB board body are achieved through wiring layers and vias within the lower stack-up structure.

[0012] In some embodiments, the upper stacked structure includes a PCB top layer and a first power layer. DDR chips disposed on the front side of the PCB body are connected through vias between the PCB top layer and the first power layer, and are routed in the wiring layer between the PCB top layer and the first power layer.

[0013] In some embodiments, the lower stack-up structure includes a PCB bottom layer and a second power layer. DDR chips disposed on the back side of the PCB body are connected through vias between the PCB bottom layer and the second power layer, and are routed in the wiring layer between the PCB bottom layer and the second power layer.

[0014] With the PCB structure for multi-channel DDR chips described above, this embodiment of the invention effectively utilizes PCB space when space is limited, especially when multiple channels of DDR chips need to be placed. This is achieved by overlapping DDR chips on both sides. Even when the number of PCB layers and total thickness are limited, this design can still successfully route multi-channel DDR chips. Compared to solving the problem of insufficient routing space by increasing the number of PCB layers or using high-order HDI (High-Density Interconnect) technology, this solution significantly reduces PCB manufacturing costs and avoids the manufacturing difficulties and yield reductions that may result from increasing the number of layers or using complex HDI processes, thereby improving manufacturing yield.

[0015] Furthermore, in some embodiments, by employing a stacked structure for the PCB board body, including an upper stacked structure and a lower stacked structure, the manufacturing process can be simplified, thereby shortening the product production cycle.

[0016] Furthermore, in some embodiments, electrical connections between signals of DDR chips located on the front side of the PCB are achieved through wiring layers and vias within the upper stack-up structure, while electrical connections between signals of DDR chips located on the back side of the PCB are achieved through wiring layers and vias within the lower stack-up structure. This achieves efficient routing of eight-channel DDR chips stacked on opposite sides under limited conditions. Even with stack-up and space constraints, signal quality requirements are met, avoiding the problem of thin impedance lines due to PP (prepreg) thickness limitations in high-order HDI, which increases transmission losses of other high-speed signals. Attached Figure Description

[0017] The above and other objects, features, and advantages of the present invention will become readily understood by reading the following detailed description of exemplary embodiments with reference to the accompanying drawings. In the drawings, several embodiments of the present invention are shown by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0018] Figure 1 An exemplary structural block diagram of an eight-channel DDR chip PCB board structure according to some embodiments of the present invention is shown;

[0019] Figure 2 An exemplary structural block diagram of the PCB board body according to some embodiments of the present invention is shown. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0021] It should be understood that the terms "comprising" and "including" used in the specification and claims of this utility model indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0022] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0023] This application provides a PCB structure for multi-channel DDR chips, comprising a PCB body with DDR chips disposed on both the front and back sides. The DDR chips disposed on the front side of the PCB body overlap with those disposed on the back side of the PCB body in the projection area of ​​the PCB body. That is, when viewed vertically from directly above the PCB body (i.e., the "projection area"), the DDR chips on the front and back sides of the PCB body overlap in the top view.

[0024] By grouping multi-channel DDR chips in physical layout, specifically, dividing multi-channel DDR chips into DDR chips located on the front side of the PCB board and DDR chips located on the back side of the PCB board, and making the DDR chips located on the front side of the PCB board and the DDR chips located on the back side of the PCB board overlap in the projection area of ​​the PCB board, the vertical space of the PCB board is utilized to the maximum extent, and the area occupied on the XY plane of the PCB board is reduced.

[0025] In the embodiments of this application, the PCB board body adopts a laminated structure. Specifically, the laminated structure includes an upper laminated structure and a lower laminated structure. During PCB board processing, each layer forming the upper laminated structure and each layer forming the lower laminated structure are manufactured separately. The manufactured upper laminated structure and lower laminated structure are then bonded together through a lamination process to form the final PCB board body.

[0026] In the embodiments of this application, the upper and lower stacked structures are designed to be symmetrical, that is, the number of layers in the upper stacked structure is the same as the number of layers in the lower stacked structure.

[0027] In the embodiments of this application, the thickness of the PCB board body, the number of layers of the upper and lower stacked structures are set according to actual needs, and this application does not impose any restrictions.

[0028] By separately manufacturing the layers forming the upper and lower stack-up structures, and then bonding them together using a lamination process, more flexible inner layer routing and optimized stack-up design are possible. This allows for accommodating more wiring layers or achieving more complex connections without increasing the overall board thickness. Furthermore, by designing the upper and lower stack-up structures with symmetry, signal reflections and impedance mismatches can be reduced, thereby improving signal integrity.

[0029] Through the above process, the routing challenges of multi-channel DDR chips in high-density layouts can be effectively solved under a fixed PCB thickness constraint. By employing a Z-axis overlapping layout of DDR chips and a PCB lamination process, the requirements for routing space and signal quality in multi-channel DDR designs can be met without significantly sacrificing product thinness, increasing costs substantially, or extending manufacturing cycles, while also contributing to improved production yield.

[0030] In the embodiments of this application, electrical connections between signals of DDR chips disposed on the front side of the PCB board body are achieved through wiring layers and vias in the upper stacked structure, and electrical connections between signals of DDR chips disposed on the back side of the PCB board body are achieved through wiring layers and vias in the lower stacked structure.

[0031] By routing the signals of the DDR chips located on the front side of the PCB in the upper layer stack-up structure and the signals of the DDR chips located on the back side of the PCB in the lower layer stack-up structure, physical isolation between the two sets of signals can be achieved. This separate routing method minimizes crosstalk and interference between the DDR signals on the front and back sides of the PCB. Furthermore, it allows for focused optimization of the signal path for each set of DDR chips, simplifying the routing process. In addition, routing the DDR signals on both sides in a dedicated layer allows for better control of signal impedance, thereby improving signal integrity.

[0032] Specifically, the upper layered structure includes a top PCB board and a first power layer. The DDR chips located on the front side of the PCB board are connected through vias between the top PCB board and the first power layer, and are routed in the wiring layer between the top PCB board and the first power layer.

[0033] Specifically, the lower layer structure includes a bottom layer of the PCB board and a second power layer. The DDR chips located on the back of the PCB board body are connected through vias between the bottom layer of the PCB board and the second power layer, and are routed in the wiring layer between the bottom layer of the PCB board and the second power layer.

[0034] Signals from DDR chips located on the front side of the PCB are conducted and routed through vias between the top layer and the first power layer. Signals from DDR chips located on the back side of the PCB are conducted and routed through vias between the bottom layer and the second power layer. This proximity of the power layer to the signal layer shortens the signal path and allows for better impedance control. Simultaneously, proximity to the power layer improves the power supply to the DDR chips by providing a low-impedance return path for the signals. Furthermore, since the power layer also acts as a ground plane, proximity to the signal layer minimizes ground bounce.

[0035] Figure 1 An exemplary structural block diagram of an eight-channel DDR chip PCB board structure according to some embodiments of the present invention is shown.

[0036] like Figure 1As shown, the PCB structure 100 of the eight-channel DDR chip includes a PCB body, with DDR chips disposed on both the front side 110 and the back side 120 of the PCB body. Specifically, the eight-channel DDR chip includes an upper four-channel chip disposed on the front side 110 of the PCB body and a lower four-channel chip disposed on the back side 120 of the PCB body. The upper four-channel chip includes a first upper DDR chip 111, a second upper DDR chip 112, a third upper DDR chip 113, and a fourth upper DDR chip 114. The lower four-channel chip includes a first lower DDR chip 121, a second lower DDR chip 122, a third lower DDR chip 123, and a fourth lower DDR chip 124.

[0037] Specifically, the upper-layer four-channel DDR chips correspond one-to-one with the lower-layer four-channel DDR chips at their respective positions on the PCB board. More specifically, the first upper-layer DDR chip 111 corresponds to the first lower-layer DDR chip 121, the second upper-layer DDR chip 112 corresponds to the second lower-layer DDR chip 122, the third upper-layer DDR chip 113 corresponds to the third lower-layer DDR chip 123, and the fourth upper-layer DDR chip 114 corresponds to the fourth lower-layer DDR chip 124. This arrangement facilitates a more symmetrical routing method, thereby improving signal integrity. It also makes it easier to match signal lengths and minimize impedance discontinuities.

[0038] For details regarding the specific composition of the aforementioned PCB board body, please refer to [link / reference needed]. Figure 2 .

[0039] like Figure 2 As shown, the PCB board body 200 includes an upper stacked structure 210 and a lower stacked structure 220. Specifically, the upper stacked structure 210 includes the PCB board top layer, Gnd02 layer, Inner03 layer, Gnd04 layer, Inner05 layer, Gnd06 layer, Inner07 layer, Gnd08 layer, Inner09 layer, Gnd10 layer, and a first power layer (Vcc11). The lower stacked structure 220 includes a second power layer (Vcc12), Gnd13 layer, Inner14 layer, Gnd15 layer, Inner16 layer, Gnd17 layer, Inner18 layer, Gnd19 layer, Inner20 layer, Gnd21 layer, and the PCB board bottom layer.

[0040] The presence of multiple ground layers (Gnd02, Gnd04, Gnd06, Gnd08, ​​and Gnd10) near the signal layers (Inner03, Inner05, Inner07, and Inner09) in the upper stack-up structure 210, and multiple ground layers (Gnd13, Gnd15, Gnd17, Gnd19, and Gnd21) near the signal layers (Inner14, Inner16, Inner18, and Inner20) in the lower stack-up structure 220, allows for strict impedance control, which is crucial for high-speed DDR signals. Furthermore, the ground layers provide shielding between the signal layers, thereby reducing crosstalk and improving signal integrity.

[0041] Specifically, the first upper-layer DDR chip 111, the second upper-layer DDR chip 112, the third upper-layer DDR chip 113, and the fourth upper-layer DDR chip 114 are connected through vias between the top layer of the PCB board and the first power layer (Vcc11), and are routed on the wiring layers Gnd02, Inner03, Gnd04, Inner05, Gnd06, Inner07, Gnd08, ​​Inner09, and Gnd10 between the top layer of the PCB board and the first power layer (Vcc11).

[0042] Specifically, the first lower-layer DDR chip 121, the second lower-layer DDR chip 122, the third lower-layer DDR chip 123, and the fourth lower-layer DDR chip 124 are connected through vias between the bottom layer and the second power layer (Vcc12) of the PCB board, and are routed on the wiring layers Gnd13, Inner14, Gnd15, Inner16, Gnd17, Inner18, Gnd19, Inner20, and Gnd21 between the bottom layer and the second power layer (Vcc12) of the PCB board.

[0043] Top-side DDR signals are routed via vias from the top layer to the inner signal layer in the upper stack-up structure, all the way to the first power layer. Bottom-side DDR signals are similarly routed in the lower stack-up structure, from the bottom layer to the second power layer. This routing scheme, combined with the stack-up structure, allows for relatively short and controlled signal paths. Terminating the signal layer near the power layer reduces reflections and improves signal integrity. Furthermore, it reduces interference between power and signals.

[0044] With the PCB structure for multi-channel DDR chips described above, this embodiment of the invention effectively utilizes PCB space when space is limited, especially when multiple channels of DDR chips need to be placed. This is achieved by overlapping DDR chips on both sides. Even when the number of PCB layers and total thickness are limited, this design can still successfully route multi-channel DDR chips. Compared to solving the problem of insufficient routing space by increasing the number of PCB layers or using high-order HDI (High-Density Interconnect) technology, this solution significantly reduces PCB manufacturing costs and avoids the manufacturing difficulties and yield reductions that may result from increasing the number of layers or using complex HDI processes, thereby improving manufacturing yield.

[0045] Furthermore, in some embodiments, by employing a stacked structure for the PCB board body, including an upper stacked structure and a lower stacked structure, the manufacturing process can be simplified, thereby shortening the product production cycle.

[0046] Furthermore, in some embodiments, electrical connections between signals of DDR chips located on the front side of the PCB are achieved through wiring layers and vias within the upper stack-up structure, while electrical connections between signals of DDR chips located on the back side of the PCB are achieved through wiring layers and vias within the lower stack-up structure. This achieves efficient routing of eight-channel DDR chips stacked on opposite sides under limited conditions. Even with stack-up and space constraints, signal quality requirements are met, avoiding the problem of thin impedance lines due to PP (prepreg) thickness limitations in high-order HDI, which increases transmission losses of other high-speed signals.

[0047] While various embodiments of the present invention have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of the present invention. It should be understood that various alternatives to the embodiments of the present invention described herein may be employed in the practice of the present invention. The appended claims are intended to define the scope of protection of the present invention and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A PCB board structure for multi-channel DDR chips, comprising a PCB board body, wherein DDR chips are disposed on both the front and back sides of the PCB board body, and the DDR chips disposed on the front side of the PCB board body and the DDR chips disposed on the back side of the PCB board body overlap on the projection area of ​​the PCB board body.

2. The PCB structure for multi-lane DDR devices of claim 1, wherein, The DDR chip is an eight-channel DDR chip, wherein the eight-channel DDR chip includes an upper four-channel chip disposed on the front side of the PCB board body and a lower four-channel chip disposed on the back side of the PCB board body.

3. The PCB structure for multi-lane DDR devices of claim 2, wherein, The upper four-channel particles and the lower four-channel particles correspond one-to-one in their respective positions on the PCB board body.

4. The PCB structure of multi-lane DDR particles according to any one of claims 1-3, characterized in that, The PCB board body adopts a stacked structure, which includes an upper stacked structure and a lower stacked structure.

5. The PCB structure for multi-lane DDR devices of claim 4, wherein, Electrical connections between signals of DDR chips located on the front side of the PCB board body are achieved through wiring layers and vias within the upper stacked structure.

6. The PCB structure for multi-lane DDR devices of claim 5, wherein, Electrical connections between signals of DDR chips located on the back of the PCB board body are achieved through wiring layers and vias within the lower stacked structure.

7. The PCB structure for multi-lane DDR devices of claim 6, wherein, The upper layered structure includes a PCB top layer and a first power layer. DDR chips disposed on the front side of the PCB body are connected through vias between the PCB top layer and the first power layer, and are routed in the wiring layer between the PCB top layer and the first power layer.

8. The PCB board structure of multi-channel DDR particles according to claim 7, characterized by, The lower layer structure includes a PCB bottom layer and a second power layer. DDR chips disposed on the back of the PCB body are connected through vias between the PCB bottom layer and the second power layer, and are routed in the wiring layer between the PCB bottom layer and the second power layer.

Images