Cis-ferroelectric field effect transistor
By employing a quantum well structure with hafnium silicon oxide and doped transition material layers in a ferroelectric field-effect transistor, and combining dielectric and ferroelectric layers, the problems of material miniaturization and durability are solved, thereby improving the stability and reliability of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI SHENMING AOSI SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2025-07-31
- Publication Date
- 2026-05-19
AI Technical Summary
Existing ferroelectric field-effect transistor materials are insufficient in terms of miniaturization and durability, and cannot meet the miniaturization requirements of technology nodes below 130 nanometers, and have poor storage reliability and stability.
A more stable paraferroelectric field-effect transistor structure is constructed by using a quantum well layered structure formed by a hafnium silicon oxide layer and a doped transition material layer, combined with a dielectric intermediate layer, a ferroelectric layer and a barrier layer.
It improves the endurance and data retention of non-volatile memory, enhances stability against changes in doping concentration, thickness, temperature and stress, and improves storage performance.
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Figure CN224265381U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of non-volatile memory device technology, and in particular to a paraferroelectric field-effect transistor. Background Technology
[0002] Ferroelectric field-effect transistors (FETs), as an important non-volatile memory device, operate on the principle of controlling the polarization direction of the ferroelectric dielectric layer through gate voltage, thereby altering the threshold voltage state of the semiconductor channel. When the dipoles within the ferroelectric dielectric are aligned upwards, the channel exhibits a low threshold voltage conduction state; conversely, when the dipoles are aligned downwards, the channel transitions to a high threshold voltage off state. This polarization-flipping-based memory mechanism offers advantages in high-speed read / write speeds and low power consumption, but its practical applications have long been limited by material system defects. Traditional perovskite ferroelectric materials, such as lead zirconate titanate or strontium bismuth titanate, not only require thicknesses exceeding 200 nanometers to maintain effective residual polarization intensity, but their high-temperature fabrication processes also cause cross-contamination issues in silicon-based production lines. More importantly, these materials cannot meet the miniaturization requirements of technology nodes below 130 nanometers, and their manufacturing costs are significantly higher than those of dynamic random access memory (DRAM) and flash memory products, hindering their commercialization.
[0003] In recent years, with the continuous research on hafnium-based ferroelectric materials, it has been found that by incorporating elements such as silicon, aluminum, and yttrium, the ferroelectric properties of hafnium oxide can be realized in the 28-nanometer high-dielectric metal gate process.
[0004] However, these types of doped hafnium oxide materials will produce severe fatigue and imprinting effects during repeated read and write operations, and their durability can only reach 10,000 to 100,000 cycles, resulting in poor data storage reliability and stability. Summary of the Invention
[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a paraferroelectric field-effect transistor (PFFET) that improves the reliability and stability of stored data.
[0006] To achieve the above objectives, this application provides a paraferroelectric field-effect transistor, comprising:
[0007] Semiconductor substrate;
[0008] A semiconductor channel containing a source and a drain is located on the semiconductor substrate and is connected to a metal source and a metal drain, respectively.
[0009] A paraferroelectric layer is located on the semiconductor channel containing the source and drain electrodes;
[0010] A metal gate is located on the paraferroelectric layer;
[0011] The paraferroelectric layer is a quantum well layered structure formed by cyclic deposition of a hafnium silicon oxide layer and a doped transition material layer.
[0012] Furthermore, the hafnium silicon oxide layer is The material layer, where x takes values from 0.02 to 0.65; the doped transition material layer is... layer, layer, TiN layer, TiN layer, TaN layer Layer or layer.
[0013] Furthermore, a dielectric intermediate layer is provided between the semiconductor channel containing the source and drain electrodes and the paraferroelectric layer.
[0014] Furthermore, the dielectric intermediate layer is Layer or SiON layer.
[0015] Furthermore, a ferroelectric layer is disposed between the paraferroelectric layer and the metal gate.
[0016] Furthermore, the ferroelectric layer is doped. Ferroelectric layer, doping Ferroelectric layer or doping Ferroelectric layer, where x takes values from 0.02 to 0.65.
[0017] Furthermore, a barrier layer is provided between the paraferroelectric layer and the ferroelectric layer.
[0018] Furthermore, a dielectric intermediate layer, a ferroelectric layer, and a barrier layer are disposed between the semiconductor channel containing the source and drain and the metal gate, wherein the dielectric intermediate layer, the ferroelectric layer, the paraferroelectric layer, the barrier layer, and the metal gate are sequentially disposed in the semiconductor channel containing the source and drain.
[0019] Furthermore, the barrier layer is layer, layer, layer, Layer or ONO layer.
[0020] The para-iron field-effect transistor of this application not only improves the charge storage performance of non-volatile memory in terms of endurance and data retention, but also makes it more stable in terms of resistance to changes in doping concentration, thickness, temperature and stress.
[0021] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. Attached Figure Description
[0022] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings:
[0023] Figure 1 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 1 of this application;
[0024] Figure 2 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 2 of this application;
[0025] Figure 3 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 3 of this application;
[0026] Figure 4 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 4 of this application;
[0027] Figure 5 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 5 of this application;
[0028] Figure 6 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 7 of this application;
[0029] Figure 7 This is a schematic diagram of the structure of the paraferroelectric field-effect transistor of Embodiment 7 of this application. Detailed Implementation
[0030] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.
[0031] It should be understood that the steps described in the method embodiments of this application may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.
[0032] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.
[0033] It should be noted that the terms "one" and "multiple" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "Multiple" should be understood as two or more.
[0034] Example 1
[0035] One embodiment of this application provides a paraferroelectric field-effect transistor. Figure 1 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 1 of this application, as shown below. Figure 1 As shown, the paraferroelectric field-effect transistor of this application includes:
[0036] Semiconductor substrate 10, and semiconductor channel 20 containing source and drain electrodes, paraferroelectric layer 30 and metal gate 40 sequentially formed on semiconductor substrate 10.
[0037] In this embodiment, the paraferroelectric layer 30 is a quantum well layered structure formed by a hafnium silicon oxide layer and a doped transition material layer.
[0038] In this embodiment, hafnium silicon oxide is , where x ranges from 0.02 to 0.65.
[0039] In this embodiment, the doped transition material can also be , , TiN, TaN and .
[0040] In this embodiment, the metal gate 40 is a TiN, TaN, WN, W, Ir, Pt, or Pd metal electrode.
[0041] In this embodiment, the paraferroelectric field-effect transistor is an NMOS ferroelectric field-effect transistor, and the semiconductor substrate 10 is a P-type semiconductor substrate. When storing "0", +Vpp is applied to the gate of the paraferroelectric field-effect transistor, and electrons from the memory are injected into the paraferroelectric layer, causing the threshold voltage of the paraferroelectric field-effect transistor to be lowered. Forward offset; when storing "1", -Vpp is applied to the gate of the paraferroelectric field-effect transistor, and holes from the memory are injected into the paraferroelectric layer, causing the threshold voltage of the paraferroelectric field-effect transistor to rise. Negative offset.
[0042] Example 2
[0043] One embodiment of this application provides a paraferroelectric field-effect transistor. Figure 2 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 2 of this application, as shown below. Figure 2 As shown, the paraferroelectric field-effect transistor of this application differs from the paraferroelectric field-effect transistor of Embodiment 1 in that:
[0044] In this embodiment, the paraferroelectric field-effect transistor is a PMOS ferroelectric field-effect transistor, and the semiconductor substrate 10 is an N-type semiconductor substrate. When storing "0", -Vpp is applied to the gate of the paraferroelectric field-effect transistor, and holes from the memory are injected into the paraferroelectric layer, causing the threshold voltage of the paraferroelectric field-effect transistor to be lowered. Negative offset; when storing a "1", +Vpp is applied to the gate of the paraferroelectric field-effect transistor, and electrons from the memory are injected into the paraferroelectric layer, causing the threshold voltage of the paraferroelectric field-effect transistor to rise. Positive offset.
[0045] Example 3
[0046] One embodiment of this application provides a paraferroelectric field-effect transistor. Figure 3 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 3 of this application, as shown below. Figure 3 As shown, the paraferroelectric field-effect transistor of this application differs from the paraferroelectric field-effect transistor of Embodiment 1 in that:
[0047] A dielectric intermediate layer 50 is also formed between the semiconductor channel 20 containing the source and drain electrodes and the paraferroelectric layer 30 to prevent mutual diffusion between the paraferroelectric layer 30 and the semiconductor channel 20.
[0048] In this embodiment, the dielectric intermediate layer 50 is Layer or SiON layer.
[0049] Example 4
[0050] One embodiment of this application provides a paraferroelectric field-effect transistor. Figure 4 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 4 of this application, as shown below. Figure 4 As shown, the paraferroelectric field-effect transistor of this application embodiment differs from the paraferroelectric field-effect transistor of embodiment 2 in that:
[0051] A dielectric intermediate layer 50 is also formed between the semiconductor channel 20 containing the source and drain electrodes and the paraferroelectric layer 30 to prevent mutual diffusion between the paraferroelectric layer 30 and the semiconductor channel 20.
[0052] In this embodiment, the dielectric intermediate layer 50 is Layer or SiON layer.
[0053] Example 5
[0054] One embodiment of this application provides a paraferroelectric field-effect transistor. Figure 5 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 5 of this application, as shown below. Figure 5 As shown, the paraferroelectric field-effect transistor of this application includes:
[0055] The semiconductor substrate 10 includes a semiconductor channel 20 containing a source and a drain, a dielectric intermediate layer 50, a ferroelectric layer 70, a paraferroelectric layer 30, and a metal gate 40 formed sequentially on the semiconductor substrate 10.
[0056] In this embodiment, the paraferroelectric layer 30 is an independent paraelectric layer, and the ferroelectric layer 70 is an independent ferroelectric layer.
[0057] In this embodiment, the ferroelectric layer 70 is doped. Ferroelectric layer, doped Layer or doping The layer, where x takes values from 0.02 to 0.65.
[0058] In this embodiment, the paraferroelectric field-effect transistor is an NMOS ferroelectric field-effect transistor, and the semiconductor substrate 10 is a P-type semiconductor substrate. When storing "0", +Vpp is applied to the gate of the paraferroelectric field-effect transistor, and electrons from the memory are injected into the paraferroelectric layer, causing the threshold voltage of the paraferroelectric field-effect transistor to be lowered. Forward offset; when storing "1", -Vpp is applied to the gate of the paraferroelectric field-effect transistor, and holes from the memory are injected into the paraferroelectric layer, causing the threshold voltage of the paraferroelectric field-effect transistor to rise. Negative offset.
[0059] In this embodiment, the metal gate 40 is a TiN, TaN, WN, W, Ir, Pt, or Pd metal electrode.
[0060] This dielectric intermediate layer 50 is... Layer or SiON layer.
[0061] In this embodiment, a dielectric intermediate layer 50 is provided to prevent mutual diffusion between the paraferroelectric layer 30 and the semiconductor channel 20.
[0062] Example 6
[0063] One embodiment of this application provides a paraferroelectric field-effect transistor. Figure 6 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 6 of this application, as shown below. Figure 6 As shown, the paraferroelectric field-effect transistor of this application embodiment differs from the paraferroelectric field-effect transistor of embodiment 5 in that:
[0064] A barrier layer 80 is provided between the paraferroelectric layer 30 and the ferroelectric layer 70 to enhance the data retention capability of the paraferroelectric field-effect transistor.
[0065] In this embodiment, the barrier layer 80 is layer, layer, layer Either the layer or the ONO layer.
[0066] Example 7
[0067] One embodiment of this application provides a paraferroelectric field-effect transistor. Figure 7 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 7 of this application, as shown below. Figure 7 As shown, the paraferroelectric field-effect crystal of this application embodiment includes:
[0068] The semiconductor substrate 10 includes a semiconductor channel 20 containing a source and a drain, a dielectric intermediate layer 50, a paraferroelectric layer 30, a ferroelectric layer 70, a barrier layer 80, and a metal gate 40, which are sequentially formed on the semiconductor substrate 10.
[0069] In this embodiment, the paraferroelectric layer 30 is an independent paraelectric layer, and the ferroelectric layer 70 is an independent ferroelectric layer.
[0070] In this embodiment, the ferroelectric layer 70 is doped. Ferroelectric layer, doped Layer or doping layer.
[0071] In this embodiment, the metal gate 40 is a TiN, TaN, WN, W, Ir, Pt, or Pd metal electrode.
[0072] Dielectric intermediate layer 50 is Layer or SiON layer.
[0073] In this embodiment, a dielectric intermediate layer 50 is provided to prevent mutual diffusion between the paraferroelectric layer 30 and the semiconductor channel 20.
[0074] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A paraferroelectric field-effect transistor, characterized in that, include: Semiconductor substrate; A semiconductor channel containing a source and a drain is located on the semiconductor substrate and is connected to a metal source and a metal drain, respectively. A paraferroelectric layer is located on the semiconductor channel containing the source and drain electrodes; A metal gate is located on the paraferroelectric layer; The paraferroelectric layer is a quantum well layered structure formed by cyclic deposition of a hafnium silicon oxide layer and a doped transition material layer.
2. The paraferroelectric field-effect transistor according to claim 1, characterized in that, A dielectric intermediate layer is also provided between the semiconductor channel containing the source and drain electrodes and the paraferroelectric layer.
3. The paraferroelectric field-effect transistor according to claim 2, characterized in that, The dielectric intermediate layer is Layer or SiON layer.
4. The paraferroelectric field-effect transistor according to claim 2, characterized in that, A ferroelectric layer is disposed between the paraferroelectric layer and the metal gate.
5. The paraferroelectric field-effect transistor according to claim 4, characterized in that, A barrier layer is provided between the paraferroelectric layer and the ferroelectric layer.
6. The paraferroelectric field-effect transistor according to claim 1, characterized in that, Between the semiconductor channel containing the source and drain and the metal gate, a dielectric intermediate layer, a ferroelectric layer, and a barrier layer are also disposed, wherein the dielectric intermediate layer, the ferroelectric layer, the paraferroelectric layer, the barrier layer, and the metal gate are sequentially disposed in the semiconductor channel containing the source and drain.
7. The paraferroelectric field-effect transistor according to claim 5 or 6, characterized in that, The barrier layer is layer, layer, layer, Layer or ONO layer.