Semiconductor device structure

Abstract

A semiconductor device structure includes a semiconductor circuit on a substrate, the semiconductor circuit including a power amplifier and a low noise amplifier; the metal interconnection structure is embedded in a first dielectric material layer above the power amplifier and the low noise amplifier; a first phase change material (PCM) switch and a second PCM switch over the first dielectric material layer, where the first PCM switch includes a first electrode and a second electrode, and the second PCM switch includes a third electrode and a fourth electrode, where the second electrode is electrically connected to the third electrode to form a common electrical node; and a radio frequency antenna electrically connected to the common electrical node.

Description

Technical Field

[0001] This utility model relates to a method and a device structure for forming a device structure, and particularly to a method and a semiconductor device structure for forming a semiconductor device structure. Background Technology

[0002] Phase change material (PCM) switches are useful devices for mitigating interference caused by electromagnetic radiation and can be used in a variety of applications, such as radio frequency (RF) applications. PCM switches can provide electrical connection or electrical isolation in the RF signal path depending on the resistivity state of the phase change material portion. Utility Model Content

[0003] According to some embodiments of this disclosure, a semiconductor device structure is provided, comprising: a semiconductor circuit on a substrate; a first dielectric material layer on the semiconductor circuit; a first metal plate, a second metal plate, a third metal plate, a first heater element, and a second heater element on the top surface of the first dielectric material layer, wherein the first heater element is located between the first metal plate and the second metal plate, and the second heater element is located between the second metal plate and the third metal plate; a first phase change material switch and a second phase change material switch located above the first dielectric material layer, wherein the second metal plate is a common electrode of the first phase change material switch and the second phase change material switch.

[0004] According to some embodiments of this disclosure, a semiconductor device structure is provided, comprising: a semiconductor device including a power amplifier and a low-noise amplifier and superimposed on a substrate; an interconnect structure superimposed on the power amplifier and the low-noise amplifier; a first phase change material switch and a second phase change material switch located above the interconnect structure, wherein the first phase change material switch includes a first electrode and a second electrode, and the second phase change material switch includes a third electrode and a fourth electrode, wherein the second electrode is electrically connected to the third electrode to provide a common electrical node; and a radio frequency antenna electrically connected to the common electrical node. Attached Figure Description

[0005] The nature of this disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the features may be arbitrarily increased or decreased.

[0006] Figure 1A This is a vertical cross-sectional view of an embodiment of the structure after the formation of a semiconductor circuit, a first metal interconnect structure, and a first dielectric material layer, according to an embodiment of the present disclosure.

[0007] Figure 1B for Figure 1AThis is a top-to-bottom view of the embodiment structure. The vertical plane A–A' is... Figure 1A The cutting plane of the vertical cross-section.

[0008] Figure 2 This is a vertical cross-sectional view of an embodiment structure after at least one layer of metallic material has been deposited, according to one embodiment of the present disclosure.

[0009] Figure 3A This is a vertical cross-sectional view of an embodiment of the present disclosure after the at least one metal material layer has been patterned into a first metal plate, a second metal plate, a third metal plate, a first heater element, and a second heater element.

[0010] Figure 3B for Figure 3A This is a top-to-bottom view of the embodiment structure. The vertical plane A–A' is... Figure 3A The cutting plane of the vertical cross-section.

[0011] Figure 4A This is a vertical cross-sectional view of an embodiment structure after a dielectric material layer has been formed, according to one embodiment of the present disclosure.

[0012] Figure 4B for Figure 4A This is a top-to-bottom view of the embodiment structure. The vertical plane A–A' is... Figure 4A The cutting plane of the vertical cross-section.

[0013] Figure 5A This is a vertical cross-sectional view of the embodiment structure after the heat-conducting plate has been formed, according to one embodiment of the present disclosure.

[0014] Figure 5B for Figure 5A This is a top-to-bottom view of the embodiment structure. The vertical plane A–A' is... Figure 5A The cutting plane of the vertical cross-section.

[0015] Figure 5C for Figure 5A and 5B A vertical cross-sectional view of a first alternative configuration of the embodiment structure following the processing steps.

[0016] Figure 6A This is a vertical cross-sectional view of an embodiment of the present disclosure after the formation of a phase change material layer, a first outer dielectric layer and a second outer dielectric layer.

[0017] Figure 6B for Figure 6A A vertical cross-sectional view of the first alternative configuration of the embodiment structure after the processing steps.

[0018] Figure 7A This is a vertical cross-sectional view of an embodiment of the present disclosure, showing the structure after the second outer dielectric layer, the first outer dielectric layer, and the phase change material layer are patterned into a second outer dielectric plate, a first outer dielectric plate, and a phase change material portion.

[0019] Figure 7B for Figure 7A This is a top-to-bottom view of the embodiment structure. The vertical plane A–A' is... Figure 7A The cutting plane of the vertical cross-section.

[0020] Figure 7C for Figure 7A and 7B A vertical cross-sectional view of the first alternative configuration of the embodiment structure after the processing steps.

[0021] Figure 7D In order to be in Figure 7A and 7B A vertical cross-sectional view of a second alternative configuration of the embodiment structure following the processing steps.

[0022] Figure 7E for Figure 7D The second configuration of the embodiment structure is shown in a top-to-bottom view. The vertical plane D–D' is... Figure 7D The cutting plane of the vertical cross-section.

[0023] Figure 8A This is a vertical cross-sectional view of an embodiment of the present disclosure after the formation of a second dielectric material layer, a metal via structure, a metal pad structure, and a radio frequency antenna.

[0024] Figure 8B for Figure 8A This is a top-to-bottom view of the embodiment structure. The vertical plane A–A' is... Figure 8A The cutting plane of the vertical cross-section.

[0025] Figure 8C for Figure 8A and 8B The embodiment structure along Figure 8B A vertical cross-sectional view of the vertical plane C–C'.

[0026] Figure 8D A vertical cross-sectional view of the first alternative configuration of the embodiment structure after the processing steps of 8A–8C.

[0027] Figure 8E A vertical cross-sectional view of the first alternative configuration of the embodiment structure after the processing steps of 8A–8C.

[0028] Figure 9This is a top-down view of an alternative configuration of the embodiment structure after forming various metal gasket structures, according to one embodiment of the present disclosure.

[0029] Figure 10 A perspective view of a PCM switch that is part of the content of this disclosure.

[0030] Figure 11A This is a timing diagram of a heater pulse signal and an RF transmission output signal during a transition to a first switching state of a phase change material (PCM) switching circuit, according to one embodiment of the present disclosure.

[0031] Figure 11B A schematic diagram of a signal path representing the PCM switching circuit in the first switching state.

[0032] Figure 12A A timing diagram of a heater pulse signal and an RF transmission input signal during a transition to a second switching state of the PCM switching circuit, according to one embodiment of the present disclosure.

[0033] Figure 12B A schematic diagram of a signal path representing the PCM switching circuit in the second switching state.

[0034] Figure 13A A diagram illustrating the noise level at the input node of a low-noise amplifier connected to the PCM switching circuit and the noise level at the input node of a low-noise amplifier connected to a CMOS switching circuit is shown.

[0035] Figure 13B A diagram is provided to compare the device coverage and switching power of a PCM switching circuit disclosed herein with that of a conventional CMOS switching circuit.

[0036] Figure 14 A first flowchart illustrating the general processing steps for manufacturing an apparatus structure according to an embodiment of the present disclosure is provided.

[0037] Figure 15 A second flowchart illustrating the general processing steps for manufacturing an apparatus structure according to an embodiment of the present disclosure is shown. Detailed Implementation

[0038] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are merely examples and not limitations. The drawings are not to scale. Elements having the same reference numerals refer to the same elements, and unless explicitly indicated otherwise, it is assumed that the elements have the same material composition and the same thickness range. All features of an original embodiment are assumed to exist in any derived embodiments unless otherwise explicitly disclosed herein. Therefore, features illustrated with reference to relevant embodiments in the drawings and / or description support features in one embodiment. Unless explicitly indicated otherwise, embodiments in which multiple instances of any illustrated element are repeated are expressly contemplated. Embodiments in which non-essential elements are omitted are expressly contemplated, even if such embodiments are not explicitly disclosed but are known in the art.

[0039] Additionally, for ease of explanation, spatial relative terms such as "under," "below," "below," "above," "on top," and similar terms may be used herein to describe the relationship of one element or feature relative to another element(s) as illustrated in the accompanying drawings. Besides the orientations shown in the drawings, these spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly. Unless expressly indicated otherwise, elements having the same element symbol are assumed to have the same material composition and a thickness within the same thickness range.

[0040] The various embodiments disclosed herein relate to semiconductor device structures and methods for forming such semiconductor device structures. Specifically, the various embodiments disclosed herein relate to a single-pole dual-throw (SPDT) phase-change material (PCM) switching circuit for switching radio frequency (RF) signals. The various embodiments disclosed herein overcome the drawbacks of associated SPDT switches by providing a simplified, low-power, and compact design that eliminates the need for shunt cells while enhancing isolation and reducing parasitic capacitance. The SPDT PCM switch uses only a series connection of two PCM switches without using any shunt switches. This configuration not only simplifies the switching circuit but also reduces the overall area and power consumption of the switching circuit. Using PCM switches provides excellent signal isolation, effectively blocking signal leakage without requiring additional control circuitry or devices.

[0041] During a manufacturing process, a semiconductor circuit including a power amplifier (PA) and a low-noise amplifier (LNA) can be formed on a substrate. A first metal interconnect structure formed within a first dielectric material layer can be formed above the PA and LNA. Two PCM switches are formed above the first dielectric material layer. A common electrical node can be established by electrically shorting (i.e., electrically connecting) an electrode of a first PCM switch and an electrode of a second PCM switch. This common electrical node is connected to a radio frequency (RF) antenna, thereby facilitating efficient signal transmission and reception. The metal electrodes of the two PCM switches can be formed by depositing and patterning at least one metal material layer into a heater element and a metal plate serving as electrodes. A phase change material layer can be deposited and patterned to form a phase change material portion of the two PCM switches.

[0042] The various embodiments disclosed herein may include a semiconductor circuit having a metal interconnect structure formed within a dielectric layer and a PCM switch configured to enhance performance and reduce footprint. An RF antenna may be electrically connected to a common electrical node of the PCM switch, thereby enabling high signal isolation and low-power operation. Various forms and embodiments of the methods and structures disclosed herein are described with reference to the accompanying drawings.

[0043] Reference Figure 1A and 1B This illustration depicts an embodiment of a structure according to the present disclosure. The embodiment structure includes a substrate 8, which may be a semiconductor substrate, such as a silicon substrate. The substrate 8 may include a semiconductor material layer 9 at at least an upper portion of the substrate. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or it may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single-crystal semiconductor material, such as single-crystal silicon. In another embodiment, the substrate 8 may include a single-crystal silicon substrate comprising a single-crystal silicon material.

[0044] A shallow trench isolation structure 720, comprising a dielectric material such as silicon oxide, may be formed in an upper portion of the semiconductor material layer 9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed in the regions laterally enclosed by a portion of the shallow trench isolation structure 720. A semiconductor circuit 700 may be formed above the top surface of the semiconductor material layer 9. The semiconductor circuit 700 may include a complementary metal-oxide-semiconductor (CMOS) circuit including p-type field-effect transistors and n-type field-effect transistors. For example, each field-effect transistor may include a source region 732, a drain region 738, a semiconductor channel 735 (which includes a surface portion of the substrate 8 extending between the source region 732 and the drain region 738), and a gate structure 750. The semiconductor channel 735 may include a single-crystal semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source region 732, and a drain-side metal-semiconductor alloy region 748 may be formed on each drain region 738. Devices formed on the top surface of the semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (such as resistors, diodes, capacitor structures, etc.), and are collectively referred to as semiconductor circuit 700.

[0045] One or more of the field-effect transistors in the semiconductor circuit 700 may include a semiconductor channel 735 containing a portion of the semiconductor material layer 9 in the substrate 8. In embodiments where the semiconductor material layer 9 comprises a single-crystal semiconductor material such as single-crystal silicon, the semiconductor channel 735 of each field-effect transistor in the semiconductor circuit 700 may include a single-crystal semiconductor channel such as a single-crystal silicon channel. In one embodiment, a subset of the field-effect transistors in the semiconductor circuit 700 may include a node later electrically connected to an energy harvesting device and / or a corresponding node electrically connected to a battery structure later formed.

[0046] In one embodiment, substrate 8 may include a monocrystalline silicon substrate, and the field-effect transistor may include a corresponding portion of the monocrystalline silicon substrate as a half-conductive channel. As used herein, a "semiconductor" device refers to a device having a conductivity of 1.0 x 10⁻⁶. -6 S / cm up to 1.0 x 10 5 A component having conductivity in the range of S / cm. As used herein, a "semiconductor material" refers to a component that is free of electrical dopants and has a conductivity in the range of 1.0 x 10⁻⁶ S / cm. -6 S / cm up to 1.0 x 10 5 A material with conductivity in the range of S / cm, and which, after appropriate doping with electrical dopant, can produce conductivity in the range of 1.0 S / cm to 1.0 x 10⁻⁶.5 A doped material with conductivity in the range of S / cm.

[0047] According to the format of this disclosure, semiconductor circuit 700 includes a power amplifier 701 that generates a radio frequency (RF) signal with sufficient signal strength for transmission to an RF antenna. As used herein, a "power amplifier" refers to an amplifier that increases the power of a signal. Typically, a power amplifier is used in a transmission path to drive an antenna with a high-power signal. For example, the power transmitted from the output node of power amplifier 701 can be in the range of 1 watt to 100 watts, but the output node of power amplifier 701 can transmit smaller and larger powers. As used herein, a "radio frequency (RF) signal" refers to an electromagnetic wave having a frequency in the range of about 3 kHz to 300 GHz for wireless communication. In one embodiment, the drain region 738 of power amplifier 701 may include the output node of power amplifier 701. Additionally, the semiconductor circuit includes a low-noise amplifier (LNA) 702 configured to receive an RF signal from the RF antenna. As used herein, a "low-noise amplifier" refers to an amplifier that amplifies a weak signal with minimal additional noise. Typically, an LNA is used in the receive path to amplify the received signal before processing in subsequent stages. For example, the amplitude of the RF signal transmitted to the input node of the low-noise amplifier can range from 1 microvolt to 100 millivolts, although smaller and larger amplitudes can also be used. In one embodiment, the gate electrode of the LNA can be adapted as an input node. Furthermore, the phase-change material switches disclosed herein can also be used in other applications involving RF switching, such as MIMO (Multiple-Input Multiple-Output) radar systems and phase-shift RF circuits, where enhanced signal isolation and low power consumption are critical.

[0048] Various first dielectric layers (601, 610, 620, 630, 640, 24) for embedding various first metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648, 21, 32, 38) may be subsequently formed over the substrate 8 and the semiconductor circuit 700. In an exemplary example, the first dielectric layer may include, for example, a contact-level dielectric layer 601 surrounding a contact structure providing electrical connections to the source region 732, the drain region 738, and the gate electrode 754; a first interconnect-level dielectric layer 610; a second interconnect-level dielectric layer 620; a third interconnect-level dielectric layer 630; a fourth interconnect-level dielectric layer 640; and a via-level dielectric layer 24. The first metal interconnect structure may include a device contact via structure 612 extending through the contact-level dielectric material layer 601 and contacting a corresponding component of the semiconductor circuit 700; a first metal line structure 618 formed in the first interconnect-level dielectric material layer 610; a first metal via structure 622 extending through a lower portion of the second interconnect-level dielectric material layer 620; a second metal line structure 628 formed in an upper portion of the second interconnect-level dielectric material layer 620; and a second metal via structure 63. 2. It extends through a lower portion of the third interconnect dielectric layer 630; a third metal circuit structure 638 is formed in an upper portion of the third interconnect dielectric layer 630; a third metal via structure 642 extends through a lower portion of the fourth interconnect dielectric layer 640; a fourth metal circuit structure 648 is formed in an upper portion of the fourth interconnect dielectric layer 640; and connecting via structures (21, 32, 38) extend through the via-level dielectric layer 24. Although this disclosure is illustrated using an embodiment in which a four-level metal circuit structure is formed in the first dielectric layer, embodiments in which a smaller or larger number of metal circuit structures are formed in the first dielectric layer are explicitly contemplated herein.

[0049] Each of the first dielectric material layers (601, 610, 620, 630, 640, 24) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, or a combination thereof with varying porosity. Each of the first metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648, 21, 32, 38) may include at least one conductive material, which may be a combination of a metal liner (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal filler materials within the scope of this disclosure may also be used. In one embodiment, the first metal via structure 622 and the second metal circuit structure 628 can be formed into an integrated circuit and via structure through a dual damascene process. Generally, any consecutive set of metal circuit structures (628, 638, 648) and at least one lower metal via structure (622, 632, 642) can be formed into an integrated circuit and via structure.

[0050] Generally, a semiconductor device (such as a field-effect transistor) may be formed on a substrate 8, and a first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648, 21, 32, 38) and a first dielectric material layer (601, 610, 620, 630, 640, 24) may be formed in the first dielectric material layer (601, 610, 620, 630, 640, 24) and may be electrically connected to the semiconductor device.

[0051] The connecting via structures (21, 32, 38) may be located at the position where the metal plate of the phase change material (PCM) radio frequency (RF) switching circuit will subsequently be formed above. The connecting via structures (21, 32, 38) may include a signal node connecting via structure 21, which is a subset of the metal plate for contacting the signal nodes used as signal nodes in the PCM RF switching circuit; a first heater connecting via structure 32, which is for contacting a corresponding first wide end of the metal plate having an intermediate strip portion and serving as a heater element; and a second heater connecting via structure 38, which is for contacting a corresponding second wide end of the metal plate. The signal node connecting via structure 21 may include a first signal node connecting via structure 21A, which is for contacting a signal node of a first (PCM) switch serving as a signal path for a high-power RF signal from the output node of the power amplifier 701; and a second signal node connecting via structure 21B, which is for contacting a signal node of a second (PCM) switch serving as a signal path for a low-power RF signal from an RF antenna to the input node of the low-noise amplifier 702.

[0052] Reference Figure 2 At least one metal material layer 40L may be deposited above the via-level dielectric material layer 24. Generally, at least one metal material layer 40L may be deposited above the top surface of the first dielectric material layer (601, 610, 620, 630, 640, 24). In one embodiment, at least one metal material layer 40L comprises at least one metal material that can withstand a sufficiently high temperature to induce melting of the phase change material.

[0053] In one embodiment, at least one metal material layer 40L may comprise at least one metal material selected from the following: tungsten, tantalum, molybdenum, niobium, rhenium, tungsten nitride, tantalum nitride, titanium nitride and molybdenum nitride, copper, aluminum, silver, platinum and aluminum nitride. In one embodiment, at least one metal material layer 40L may comprise a metal barrier material layer 40B and a main metal layer 40M. The metal barrier material layer 40B may be substantially composed of a metal nitride material selected from tungsten nitride, tantalum nitride, titanium nitride and molybdenum nitride. The main metal layer 40M may comprise a metal selected from tungsten, tantalum, molybdenum, niobium, rhenium, copper, aluminum, silver, platinum and aluminum nitride. In a non-limiting exemplary embodiment, at least one metal material layer 40L may comprise a metal barrier material layer 40B and a main metal layer 40M, the metal barrier material layer comprising titanium nitride having a melting point of 2,930 degrees Celsius, and the main metal layer comprising tungsten having a melting point of 3,422 degrees Celsius.

[0054] Generally, at least one metallic material layer 40L can be deposited by physical vapor deposition (PVD) and / or chemical vapor deposition (CVD). The thickness of the at least one metallic material layer 40L can be in the range of 30 nm to 300 nm, such as from 60 nm to 150 nm, although smaller and larger thicknesses can also be used.

[0055] Reference Figure 3A and 3B An etch mask layer (such as a patterned photoresist layer) may be applied over at least one metal material layer 40L and may be photolithographically patterned to form a patterned etch mask layer (not illustrated). An etch process (such as a reactive ion etching process) may transfer the pattern in the patterned etch mask layer via at least one metal material layer 40L. The pattern in the etch mask layer may be selectively patterned such that the patterned remainder of at least one metal material layer 40L includes a first heater element 501 for a first PCM RF switch, a second heater element 502 for a second PCM RF switch, a first electrode and a second electrode for the first PCM RF switch, and a second electrode for the second PCM RF switch. In one embodiment, the second electrode of the first (PCM) switch and the third electrode of the second (PCM) switch may include the same structure.

[0056] An anisotropic etching process can be performed to transfer a pattern in an etching mask layer via at least one metal material layer 40L. The at least one metal material layer 40L can be patterned into a first metal plate 42, a second metal plate 45, a third metal plate 48, a first heater element 501, and a second heater element 502. The first heater element 501 is formed between the first metal plate 42 and the second metal plate 45, and the second heater element 502 is formed between the second metal plate 45 and the third metal plate 48. Each of the first metal plate 42, the second metal plate 45, the third metal plate 48, the first heater element 501, and the second heater element 502 includes a corresponding patterned portion of at least one metal material layer 40L, and may include corresponding patterned portions (42B, 45B, 48B, 42M, 45M, 48M) of an optional metal barrier material layer 40B and a main metal layer 40M. The etching mask layer can be removed later, for example, by ashing.

[0057] Generally, the patterned portion of at least one metal material layer 40L includes a first heater element 501, a second heater element 502, a first electrode (which may include a first metal plate 42), a second electrode (which may include a second metal plate 45), a third electrode (including the second metal plate 45), and a fourth electrode (which may include a third metal plate 48). The first heater element 501, the second heater element 502, the first metal plate 42, the second metal plate 45, and the third metal plate 48 may include at least one metal material from the same group and may have the same thickness.

[0058] According to one aspect of this disclosure, the first metal plate 42 may be electrically connected to an output node (such as a drain region 738) of the power amplifier 701, and the third metal plate 48 may be electrically connected to an input node (such as a gate electrode 754) of the low-noise amplifier 702.

[0059] Each heater element 50 includes a strip portion 55 having a narrow, uniform width; a first end portion 52 adjacent to a first end of the strip portion 55; and a second end portion 58 adjacent to a second end of the strip portion 55 and laterally spaced from the first end portion 52. For example, the heater element 50 may include a first heater element 501 located between a first metal plate 42 and a second metal plate 45, and a second heater element 502 located between a second metal plate 45 and a third metal plate 48. The first heater element 501 may include a first heater strip portion 551 having a narrow, uniform width; a first heater first end portion 521 adjacent to a first end of the first heater strip portion 551; and a first heater second end portion 581 adjacent to a second end of the first heater strip portion 551. The second heater element 502 may include a second heater strip portion 552 having a narrow, uniform width; a second heater first end portion 522 adjacent to a first end of the second heater strip portion 552; and a second heater second end portion 582 adjacent to a second end of the second heater strip portion 552. In one embodiment, each strip portion 55 may have a narrow, uniform width along a first horizontal direction hd1 and may extend laterally along a second horizontal direction hd2 orthogonal to the first horizontal direction hd1; and each second end portion 58 of a heater element 50 may be laterally spaced from the first end portion 52 of the corresponding heater element 50 along the second horizontal direction hd2.

[0060] One of the first end 521 and the second end 581 of the first heater can be connected to an output node of a first programming transistor located within the semiconductor circuit 700 and configured to generate current pulses for programming a first PCM switch to be formed later, and the other of the first end 521 and the second end 581 of the first heater can be electrically grounded. One of the first end 522 and the second end 582 of the second heater can be connected to an output node of a second programming transistor located within the semiconductor circuit 700 and configured to generate current pulses for programming a second PCM switch to be formed later, and the other of the first end 522 and the second end 582 of the second heater can be electrically grounded.

[0061] The uniform width of each strip portion 55 along the first horizontal direction can be a critical dimension, that is, the smallest size that can be printed using a single photolithography exposure by a photolithography tool used to pattern etch a mask layer (such as a patterned photoresist layer). For example, the uniform width of the strip portion 55 can be in the range of 10 nm to 60 nm, such as from 20 nm to 40 nm, although smaller and larger sizes can also be used. The ratio of the length of the strip portion 55 to the width of the strip portion 55 can be in the range of 3 to 60, such as from 6 to 30, although smaller and larger ratios can also be used.

[0062] Each of the first end 52 and the second end 58 may include a corresponding pad region, which may have a corresponding rectangular or rounded rectangular shape. Each pad region may be adjacent to the strip portion 55 via a corresponding intermediate region having a width smaller than the pad region along the first horizontal direction hd1. Each intermediate region may have a corresponding rectangular or trapezoidal shape. The first end 52 is adjacent to a first end of the strip portion 55, and the second end 58 is adjacent to a second end of the strip portion 55.

[0063] In one embodiment, the first heater strip portion 551 of the first heater element 501 extends laterally along a second horizontal direction hd2 between the first metal plate 42 and the second metal plate 45; and the second heater strip portion 552 of the second heater element 502 extends laterally along the second horizontal direction hd2 between the second metal plate 45 and the third metal plate 48. Each of the first metal plate 42, the second metal plate 45, and the third metal plate 48 may have a corresponding rectangular shape. The width of each of the first metal plate 42, the second metal plate 45, and the third metal plate 48 along the second horizontal direction hd2 may be from 50% to 96% of the length of the strip portion 55 of each heater element 50, such as from 70% to 90%. The length of each of the first metal plate 42, the second metal plate 45, and the third metal plate 48 along the first horizontal direction hd1 can be within a range of 50% to 300% of the width of the corresponding one of the first metal plate 42, the second metal plate 45, and the third metal plate 48 along the second horizontal direction hd2, although smaller and larger lengths may also be used.

[0064] In one embodiment, the top surfaces of the heater element 50, the first metal plate 42, the second metal plate 45, and the third metal plate 48 may be formed in a first horizontal plane. The bottom surfaces of the heater element 50, the first metal plate 42, the second metal plate 45, and the third metal plate 48 may be formed in a second horizontal plane including the top surface of the through-hole dielectric material layer 24.

[0065] The width of the strip portion 55 of each heater element 50 along the first horizontal direction hd1 can be generally uniform. In one embodiment, the width of the strip portion 55 of each heater element 50 along the first horizontal direction hd1 can be in the range of 10 nm to 100 nm, such as from 20 nm to 60 nm, although smaller and larger widths can also be used. The lateral separation distance between adjacent pairs of metal plates of the first metal plate 42, the second metal plate 45, and the third metal plate 48 can be in the range of 2 to 10 times the width of the strip portion 55, such as from 3 to 5 times the width of the strip portion 55. Each strip portion 55 is laterally separated from the adjacent metal plates (42, 45, 48) by a corresponding gap.

[0066] Reference Figure 4A and 4BA dielectric material may be deposited over various patterned portions of at least one metal material layer 40L, including a heater element 50, a first metal plate 42, a second metal plate 45, and a third metal plate 48. The dielectric material comprises a planarizable dielectric material or a self-planarizing dielectric material. For example, the dielectric material may comprise an undoped silicate glass having a dielectric constant of 3.9, a doped silicate glass having a dielectric constant in the range of 3.5 to 3.9, an organosilicon glass having a dielectric constant in the range of 2.2 to 3.0, or a nanoglass having a dielectric constant of about 1.3. Excess portions of the dielectric material may be removed above a horizontal plane comprising the top surfaces of the heater element 50, the first metal plate 42, the second metal plate 45, and the third metal plate 48. The remaining portions of the dielectric material comprise a dielectric material layer, referred herein as an electrode-level dielectric layer 26.

[0067] Reference Figure 5A and 5B A thermally conductive layer may be formed above the electrode-level dielectric layer 26 and may be patterned into a thermally conductive plate 28. Preferably, the thermally conductive layer comprises a dielectric material that provides a reasonably high thermal conductivity to facilitate heat dissipation from the heater element 50. For example, the thermally conductive layer may have a thermal conductivity in the range of 1 W / m·K to 2,300 W / m·K. For example, the thermally conductive layer may comprise aluminum nitride, tantalum nitride, silicon nitride, boron nitride, silicon carbide, silicon oxide, silicon carbide, and diamond. Aluminum nitride has a thermal conductivity in the range of 140 W / m·K to 180 W / m·K. Tantalum nitride has a thermal conductivity in the range of 20 W / m·K to 30 W / m·K. Silicon nitride has a thermal conductivity in the range of 10 W / m·K to 30 W / m·K. Hexagonal boron nitride has a thermal conductivity of approximately 600 W / m·K. Silicon carbide has a thermal conductivity ranging from 120 W / m·K to 270 W / m·K. Silicon oxide has a thermal conductivity of about 1.4 W / m·K. Diamond exhibits particularly high thermal conductivity ranging from 900 W / m·K to 2300 W / m·K. The thermally conductive layer can be deposited by chemical vapor deposition and can have a thickness ranging from 6 nm to 60 nm, such as from 12 nm to 30 nm, but smaller and larger thicknesses can also be used.

[0068] A photoresist layer (not shown) may be applied over the thermally conductive layer and may be photolithographically patterned to form a pattern covering the strip portion 55 of the heater element 50. A primary portion (i.e., more than 50%) of each of the first metal plate 42, the second metal plate 45, and the third metal plate 48 is not covered by the patterned photoresist layer. An etching process may be performed to etch the unmasked portions of the thermally conductive layer. The etching process selectively etches the material of the thermally conductive layer relative to the materials of the heater element 50, the first metal plate 42, the second metal plate 45, and the third metal plate 48. The etching process may include an anisotropic etching process (such as a reactive ion etching process) or an isotropic etching process (such as a wet etching process). The patterned portion of the thermally conductive layer includes a thermally conductive plate 28. The photoresist layer may be removed later, for example, by ashing. The thermally conductive plate 28 may include a first thermally conductive plate 281 covering the first heater strip portion 551 and a second thermally conductive plate 282 covering the second heater strip portion 552.

[0069] Reference Figure 5C A first alternative configuration of the embodiment structure can be derived from Figure 5A and 5B In this embodiment, the top surface of the electrode-level dielectric layer 26 is vertically recessed before the heat-conducting plate 28 is formed. In this case, an additional processing step can be performed before forming the heat-conducting plate 28 to selectively recess the dielectric material of the electrode-level dielectric layer 26 vertically relative to the metal materials of the first metal plate 42, the second metal plate 45, and the third metal plate 48. In this embodiment, when the electrode-level dielectric layer 26 is selectively recessed relative to the metal materials of the first metal plate 42, the second metal plate 45, and the third metal plate 48, the upper surface sections of the sidewalls of the first metal plate 42, the second metal plate 45, and the third metal plate 48 can be solidly exposed. The recess depth can be in a range from 1% to 90% of the thickness of the electrode-level dielectric layer 26, such as from 10% to 50%. In this embodiment, the heat-conducting plate 28 can contact the upper surface section of the sidewall of the strip portion 55 of the heater element 50.

[0070] Reference Figure 6A and 6B A phase change material (PCM) layer 70L and at least one outer dielectric layer (72L, 74L) may be deposited above the heat-conducting plate 28 and the first electrode (including the first metal plate 42) and the first heater element 501. Figure 4A and 4B (shown), second electrode (including second metal plate 45), third electrode (including second metal plate 45), second heater element 502 (as shown ... third heater Figure 4A and 4BThe phase change material layer 70L can be deposited directly on the solidly exposed top surface portions of the first metal plate 42, the second metal plate 45, the third metal plate 48, and the heater element 50, as shown in the diagram. Figure 6A Corresponding to derived from Figure 5A and 5B The configuration of the illustrated embodiment structure. Figure 6B Corresponding to Figure 5C The illustrated first alternative configuration has the top surface of the electrode dielectric layer 26 recessed perpendicularly to the top surfaces of the first metal plate 42, the second metal plate 45 and the third metal plate 48.

[0071] The phase change material layer 70L comprises and / or is substantially composed of a phase change material. As used herein, "phase change material" refers to a material having at least two distinct phases providing different resistivities. A phase change material (PCM) can be used to store information as a resistivity state of a material, which may be in different resistivity states corresponding to different phases of the material. Different phases may include an amorphous state with high resistivity and a crystalline state with low resistivity (i.e., lower resistivity than the amorphous state). The transition between the amorphous and crystalline states can be induced by controlling the cooling rate after applying an electrical pulse that makes the phase change material amorphous in a first part of the programming process. A second part of the programming process includes controlling the cooling rate of the phase change material. In embodiments where rapid quenching occurs, the phase change material may be cooled to an amorphous, high-resistivity state. In embodiments where slow cooling occurs, the phase change material may be cooled to a crystalline, low-resistivity state.

[0072] Exemplary phase change materials include, but are not limited to, germanium antimony telluride (GST) compounds such as Ge2Sb2Te5 or GeSb2Te4, germanium antimony compounds, indium germanium telluride compounds, aluminum selenide telluride compounds, indium selenide telluride compounds, and aluminum indium selenide telluride compounds. The phase change material can be doped (e.g., nitrogen-doped GST) or undoped to enhance resistive switching characteristics. The phase change material layer 70L can be deposited by physical vapor deposition. The thickness of the phase change material layer 70L can range from 1 nm to 1,000 nm, such as from 30 nm to 300 nm, although smaller and larger thicknesses are also possible.

[0073] At least one outer dielectric layer (72L, 74L) may be deposited over the phase change material layer 70L. In one embodiment, the at least one outer dielectric layer (72L, 74L) may comprise a stack of a first outer dielectric layer 72L and a second outer dielectric layer 74L. In one embodiment, the first outer dielectric layer 72L may comprise a dielectric barrier material, such as silicon nitride or silicon carbonitride, and the second outer dielectric layer 74L may comprise a dielectric material different from the dielectric barrier material. For example, the second outer dielectric layer 74L may comprise silicon oxide. The first outer dielectric layer 72L and the second outer dielectric layer 74L may be deposited by a corresponding chemical vapor deposition. The thickness of the first outer dielectric layer 72L may be in the range from 10 nm to 100 nm, such as from 20 nm to 60 nm, although smaller and larger thicknesses may also be used. The thickness of the second outer dielectric layer 74L can range from 10nm to 100nm, such as from 20nm to 60nm, although smaller and larger thicknesses can also be used.

[0074] Reference Figure 7A –7E, a patterned etched mask portion 77 may be formed over at least one outer dielectric layer (72L, 74L). Figure 7A and 7B Examples derived from Figure 6A The illustrated embodiment structure is a set of configurations. Figure 7C Examples derived from Figure 6B The illustrated embodiment structure is a first alternative configuration of a first alternative configuration. Figure 7D and 7E Examples can be derived from Figure 6A The illustrated embodiments are structures or derived from Figure 6B The illustrated embodiment structure has a first alternative configuration and a second alternative configuration. Figure 7A and 7B In the illustrated configuration, the top surface of the electrode dielectric layer 26 lies in the same horizontal plane as the top surfaces of the first metal plate 42, the second metal plate 45, and the third metal plate 48, and the phase change material layer 70L is patterned into a single continuous phase change material portion 70. Figure 7C In the illustrated configuration, the top surface of the electrode dielectric layer 26 is perpendicularly recessed relative to the top surfaces of the first metal plate 42, the second metal plate 45, and the third metal plate 48, and the phase change material layer 70L is patterned into a single continuous phase change material portion 70. Figure 7D and 7E In the illustrated configuration, the top surface of the electrode dielectric layer 26 may be recessed perpendicularly or non-perpendicularly relative to the top surfaces of the first metal plate 42, the second metal plate 45 and the third metal plate 48, and the phase change material layer 70L is patterned into a plurality of phase change material portions 70.

[0075] For example, a photoresist layer may be applied over at least one outer dielectric layer (72L, 74L) and may be photolithographically patterned to provide an elongated photoresist material portion serving as a patterned etch mask portion 77. The patterned etch mask portion 77 spans the strip portions 55 of the two heater elements 50 and the second metal plate 45 along a first horizontal direction hd1. In some embodiments, the patterned etch mask portion 77 may span a first metal plate 42 and a third metal plate 48. In one embodiment, the patterned etch mask portion 77 may have a rectangular horizontal cross-sectional shape having longitudinal edges parallel to the first horizontal direction hd1 and lateral edges parallel to the second horizontal direction hd2.

[0076] The unmasked portions of at least one outer dielectric layer (72L, 74L) and the phase change material layer 70L can be etched by performing an anisotropic etching process using a patterned etch mask portion 77 as an etch mask. Therefore, the anisotropic etching process etches portions of the at least one outer dielectric layer (72L, 74L) and the phase change material layer 70L that are not masked by the patterned etch mask portion 77. The remaining portions of the at least one outer dielectric layer (72L, 74L) comprise at least one outer dielectric plate (72, 74). In one embodiment, the at least one outer dielectric plate (72, 74) may comprise a stack of a first outer dielectric plate 72 and a second outer dielectric plate 74. The first outer dielectric plate 72 may comprise a patterned portion of the first outer dielectric layer 72L, and the second outer dielectric plate 74 may comprise a patterned portion of the second outer dielectric layer 74L.

[0077] The phase change material layer 70L can be patterned into at least one phase change material portion. Generally, the at least one phase change material portion may include, for example: Figure 7A and 7B or Figure 7C The single phase change material portion 70 illustrated herein may include, for example, a portion 70 containing ... Figure 7D and 7E The multiple phase change material portions 70 illustrated herein. At least one phase change material portion includes a first patterned portion, which is located on the first metal plate 42 and the first heater element 501. Figure 4A and 4B (as shown) and extending above a first portion of the second metal plate 45; and a second patterned portion extending above a second portion of the second metal plate 45 and the second heater element 502 (as shown). Figure 4A and 4BThe first patterned portion of the phase change material layer 70L extends over the first electrode (including a first metal plate 42), the first heater element 501, and the second electrode (including a second metal plate 45), and extends over the third electrode (including the second metal plate 45), the second heater element 502, and the fourth electrode (including the third metal plate 48). The first patterned portion of the phase change material layer 70L includes a first phase change region 70S1, which can be programmed into an amorphous phase or a crystalline phase and is overlaid on the second heater strip portion 552. Therefore, the first patterned portion of the phase change material extends over the first electrode (including a first metal plate 42), the first heater element 501, and the second electrode (including a second metal plate 45), and the second patterned portion of the phase change material extends over the third electrode (including the second metal plate 45), the second heater element 502, and the fourth electrode (including the third metal plate 48).

[0078] The first patterned portion and the second patterned portion of the phase change material layer 70L may be non-adjacent or adjacent. Figure 7A and 7B The configurations shown in the example and in Figure 7C In the first alternative configuration illustrated herein, the first patterned portion of the phase change material layer 70L is adjacent to the second patterned portion of the phase change material layer 70L. In this configuration, the first and second patterned portions may be formed as corresponding portions of a single continuous phase change material portion 70 extending above each of the first heater element 501 and the second heater element 502. In one embodiment, a single continuous phase change material portion 70 extends laterally along a first horizontal direction hd1 and has a uniform width along a second horizontal direction hd2, and contacts the top surfaces of the first electrode (including a first metal plate 42), the second electrode (including a second metal plate 45), the third electrode (including a second metal plate 45), and the fourth electrode (including a third metal plate 48). In this embodiment, at least one outer dielectric plate (72, 74) and the phase change material portion 70 are a strip portion 55 spanning the heater element 50 and the second metal plate 45 (which includes a second electrode of a first (PCM) switch 101 and a third electrode of a second (PCM) switch 102). The phase change material portion 70 contacts and extends over at least a portion of the second metal plate 45 and the strip portion 55 of the first metal plate 42 and the third metal plate 48 near the heater element 50.

[0079] exist Figure 7D and 7EIn the second alternative configuration illustrated, the first patterned portion of the phase change material layer 70L is not adjacent to the second patterned portion of the phase change material layer 70L. Therefore, a first phase change material portion 70A may extend over the first electrode (including a first metal plate 42), the first heater element 501, and the second electrode (including a second metal plate 45), and a second phase change material portion 70B may extend over the third electrode (including the second metal plate 45), the second heater element 502, and the fourth electrode (including a third metal plate 48). The lateral distance between the first phase change material portion 70A and the second phase change material portion 70B may range from 0.1 micrometers to 100 micrometers, but smaller and larger lateral distances may also be used.

[0080] The patterned etched mask portion 77 can be removed later, for example, by ashing. A first phase change material (PCM) switch 101 and a second PCM switch 102 may be formed over a first dielectric material layer (601, 610, 620, 630, 640, 24). The first PCM switch 101 includes a first electrode (which may include a first metal plate 42) and a second electrode (which may include a second metal plate 45), and the second PCM switch 102 includes a third electrode (which may include a second metal plate 45) and a fourth electrode (which may include a third metal plate 48). In one embodiment, the second electrode (which may include a second metal plate 45) is electrically connected to the third electrode (which may include a second metal plate 45) to form a common electrical node. In one embodiment, the second metal plate 45 is a common electrode for the first PCM switch 101 and the second PCM switch 102.

[0081] The first PCM switch 101 includes a first heater element 501 located between a first electrode (including a first metal plate 42) and a second electrode (including a second metal plate 45). The second PCM switch 102 includes a second heater element 502 located between a third electrode (including a second metal plate 45) and a fourth electrode (including a third metal plate 48). Each of the first heater element 501 and the second heater element 502 comprises a collection of at least one metallic material identical to the first metal plate 42, the second metal plate 45, and the third metal plate 48.

[0082] In one embodiment, the second electrode (including a second metal plate 45) and the third electrode (including a second metal plate 45) are formed as a single metal plate (such as the second metal plate 45). In one embodiment, a first subset of the first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648, 21A) provides a first conductive path between the first electrode (including a first metal plate 42) and an output node of the power amplifier 701, and a second subset of the first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648, 21B) provides a second conductive path between the fourth electrode (including a third metal plate 48) and an input node of the low-noise amplifier 702.

[0083] According to the configuration of this disclosure, the two PCM RF switching systems provide high signal-to-weight ratio switching for power amplifier 701 and low-noise amplifier 702. Therefore, shunt transistors are not necessary for the operation of the two PCM RF switching systems of this disclosure. In one embodiment, the output node of power amplifier 701 is the only electrical node of semiconductor circuit 700 electrically connected to the first electrode (including a first metal plate 42), and the input node of low-noise amplifier 702 is the only electrical node of semiconductor circuit 700 electrically connected to the fourth electrode (including a third metal plate 48).

[0084] Reference Figures 8A-8E A PCM-level dielectric material layer 80 can be deposited on top of the first PCM switch 101 and the second PCM switch 102. Figure 8A –8C examples can be derived from Figure 7A and 7B The illustrated configuration is an example of a configuration structure. Figure 8D Examples can be derived from Figure 7C The illustrated configuration is a first alternative configuration of the embodiment structure. Figure 8E Examples can be derived from Figure 7D and 7E A second alternative configuration to the illustrated embodiment structure. The PCM-level dielectric layer 80 includes an inter-intermediate dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, porous or non-porous organosilicon glass, etc. The thickness of the PCM-level dielectric layer 80 can be in the range of 200 nm to 1,200 nm, although smaller and larger thicknesses can also be used. The PCM-level dielectric layer 80 is the bottom layer of the second dielectric layer formed above the first PCM switch 101 and the second PCM switch 102.

[0085] According to one aspect of this disclosure, a metal via structure 88 can be directly formed on a top surface of a second metal plate 45 via a PCM-level dielectric material layer 80, constituting a combination of the second electrode of the first PCM switch 101 and the third electrode of the second PCM switch 102.

[0086] Subsequently, an additional second dielectric layer may be formed over the PCM-level dielectric layer 80. This additional second dielectric layer may comprise, for example, a line-level dielectric layer 90. A metal circuit structure 98 may be formed directly on the top surface of a metal via structure 88 within the line-level dielectric layer 90.

[0087] Generally, a second dielectric material layer (80, 90) can be formed above the first PCM switch 101 and the second PCM switch 102, and a metal via structure 88 can pass through the bottom layer of the second dielectric material layer (80, 90) and be formed directly on the top surface of a single metal plate (such as a second metal plate 45) that forms the second electrode of the first PCM switch 101 and the third electrode of the second PCM switch 102.

[0088] A radio frequency (RF) antenna can be electrically connected to a second metal plate 45 via a metal via structure 88 and a metal wiring structure 98, either by forming the RF antenna over a second dielectric material layer (80, 90) or by attaching a structure including the RF antenna (such as an integrated passive device (IPD) die or an additional semiconductor die) to an assembly containing a substrate 8, a first dielectric material layer (601, 610, 620, 630, 640, 24) and a second dielectric material layer (80, 90).

[0089] RF antennas can have any configuration known in the art. Examples of such configurations include microstrip antennas, inverted planar F-type antennas (PIFA), helical antennas, dipole antennas, and slot antennas. Each of these configurations exhibits unique structural features suitable for a variety of applications. Microstrip antennas typically comprise a flat conductive strip (patch) positioned on top of a dielectric substrate, with a ground plane on the opposite side. They are generally represented as a rectangular or circular metallic patch and are often used in wireless communication devices due to their simplicity and ease of integration. The inverted planar F-type antenna (PIFA) is a variant of the microstrip antenna, comprising a short-circuit pin connecting the patch to a ground plane. It is represented as a rectangular patch with a reduced size relative to its width and a short-circuit pin, making the inverted planar F-type antenna advantageous in mobile phones and compact devices. Helical antennas comprise a helical conductor, presenting a circular or rectangular helical pattern, and are used in broadband applications due to their wide frequency response. A dipole antenna comprises two conductive elements (arms) aligned along a straight line, appearing as two straight metal lines extending from a central feed point, and is typically used in basic RF applications. A slot antenna is manufactured by cutting a slot in a conductive plane, appearing as a rectangular or other shaped slot in a metal surface, and is suitable for integration with planar structures. These antenna configurations can be integrated into a semiconductor die using advanced manufacturing techniques to ensure accuracy and performance, thereby enhancing the functionality and efficiency of RF communication systems in a variety of applications.

[0090] Reference Figure 9 The image illustrates a top-down view of an alternative configuration of the embodiment structure. This alternative configuration can be derived from... Figure 8A The embodiment structure of –8E provides electrical contacts to the first end 521, the second end 581, the first end 522, and the second end 582 of the first heater by using additional metal via structures 86 extending vertically through the PCM-level dielectric material layer 80 and additional metal wiring structures 96 formed within the line-level dielectric layer 90.

[0091] Reference Figure 10 The diagram illustrates a portion of an exemplary configuration of a PCM switch. It should be understood that the lateral extent of the phase change material portion 70 can vary according to the various alternative configurations described above.

[0092] Reference Figure 11A This illustrates a timing diagram of a heater pulse signal and an RF transmission output signal during a transition to a first operating state of a phase change material (PCM) switching circuit. To turn on the first PCM switch 101 and turn off the second PCM switch 102, a crystallization-induced programming pulse can be applied across the first heater strip portion 551 of the first PCM switch 101. Figure 4A and 4BAs shown, a first switching heater pulse (S1 heater pulse) can be applied across the second heater strip portion 552 of the second PCM switch 102, and an amorphous induced programming pulse can be applied. Figure 4A and 4B (As shown in the diagram) serves as the second switching heater pulse (S2 heater pulse). The first PCM switch 101 is turned on, and the second PCM switch 102 is turned off. Once the first PCM switch is turned on, an RF signal from the output node of the power amplifier 701 can be supplied to the RF antenna.

[0093] Figure 11B The schematic illustration shows the signal path from the output node of the power amplifier 701 to the RF antenna when the first PCM switch 101 is turned on and the second PCM switch 102 is turned off. The PCM RF switching system of this disclosure can be configured as a single pull double through switch that turns on only one of the switches at any given time.

[0094] Reference Figure 12A This illustrates a timing diagram of a heater pulse signal and an RF transmission input signal during transition to a second operating state of a phase change material (PCM) switching circuit. To disconnect the first PCM switch 101 and connect the second PCM switch 102, an amorphously induced programming pulse can be applied across the first heater strip portion 551 of the first PCM switch 101. Figure 4A and 4B As shown, a first switching heater pulse (S1 heater pulse) can be applied as a crystallization-induced programming pulse across the second heater strip portion 552 of the second PCM switch 102. Figure 4A and 4B (As shown in the diagram) serves as the second switching heater pulse (S2 heater pulse). The first PCM switch 101 is open, and the second PCM switch 102 is closed. Once the second PCM switch is closed, an RF signal from the RF antenna can be supplied to the input node of the low-noise amplifier 702.

[0095] Figure 12B The signal path from the RF antenna to the input node of the low-noise amplifier 702 is illustrated schematically when the first PCM switch 101 is open and the second PCM switch 102 is closed.

[0096] Reference Figure 13AThe diagram illustrates the noise level at the input node of a low-noise amplifier 702 connected to the PCM switching circuit of this disclosure, and the noise level at the input node of a low-noise amplifier connected to a conventional CMOS switching circuit, which uses a conventional CMOS transistor as a signal switch and has a similar device coverage area (i.e., approximately the same device area on the semiconductor substrate). Compared to conventional CMOS switching circuits, the PCM switching circuit of this disclosure provides superior signal isolation.

[0097] Reference Figure 13B The diagram compares the device coverage and switching power of a PCM switching circuit disclosed herein with that of a related CMOS switching circuit using associated CMOS transistors as signal switches and having a similar device coverage. The various embodiments of the PCM switching circuits disclosed herein use less switching power (i.e., less power consumption in the device) and less device coverage.

[0098] Figure 14 A first flowchart illustrating the general processing steps for manufacturing an apparatus structure according to an embodiment of the present disclosure is provided.

[0099] Refer to step 1410 and Figure 1A and Figure 1B A semiconductor circuit 700, including a power amplifier 701 and a low-noise amplifier 702, may be formed on the substrate 8.

[0100] Refer to step 1420 and Figure 1A and Figure 1B The first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648, 21, 32, 38) may be formed in the first dielectric material layer (601, 610, 620, 630, 640, 24) and may be formed above the power amplifier 701 and the low noise amplifier 702.

[0101] Refer to step 1430 and Figure 2 – Figure 7B A first phase change material (PCM) switch 101 and a second PCM switch 102 may be formed above a first dielectric material layer (601, 610, 620, 630, 640, 24). The first PCM switch 101 includes a first electrode (including a first metal plate 42) and a second electrode (including a second metal plate 45), and the second PCM switch 102 includes a third electrode (including the second metal plate 45) and a fourth electrode (including a third metal plate 48). The second electrode (including the second metal plate 45) is electrically connected to the third electrode (including the second metal plate 45) to form a common electrical node.

[0102] Refer to step 1440 and Figure 8A – Figure 9 A radio frequency (RF) antenna can be electrically connected to a common electrical node.

[0103] Figure 15 A second flowchart illustrating the general processing steps for manufacturing an apparatus structure according to an embodiment of the present disclosure is shown.

[0104] Refer to step 1510 and Figure 1A and Figure 1B A semiconductor circuit 700 may be formed on a substrate 8. The semiconductor circuit 700 may include a power amplifier 701 and a low-noise amplifier 702.

[0105] Refer to step 1520 and Figure 2 – Figure 4B A first metal plate 42, a second metal plate 45, a third metal plate 48, a first heater element 501, and a second heater element 502 may be formed on the top surface of a first dielectric material layer (601, 610, 620, 630, 640, 24). The first heater element 501 is formed between the first metal plate 42 and the second metal plate 45, and the second heater element 502 is formed between the second metal plate 45 and the third metal plate 48. The first metal plate 42 may be electrically connected to an output node of a power amplifier 701, and the third metal plate 48 may be electrically connected to an input node of a low-noise amplifier 702.

[0106] Refer to step 1530 and Figure 5A – Figure 9 A first phase change material (PCM) switch 101 and a second PCM switch 102 may be formed above a first dielectric material layer (601, 610, 620, 630, 640, 24). A second metal plate 45 is a common electrode for the first PCM switch 101 and the second PCM switch 102.

[0107] Referring to all the accompanying drawings and various embodiments according to the present disclosure, a device structure includes: a semiconductor circuit 700 including a power amplifier 701 and a low-noise amplifier 702 located on a substrate 8; a first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648, 21, 32, 38) embedded in a first dielectric material layer (601, 610, 620, 630, 640, 24) and covering the power amplifier 701 and the low-noise amplifier 702; a first phase change material (PCM) switch 101 and a second PCM switch 102, etc. Located above the first dielectric material layer (601, 610, 620, 630, 640, 24), the first PCM switch 101 includes a first electrode (including a first metal plate 42) and a second electrode (including a second metal plate 45), and the second PCM switch 102 includes a third electrode (including the second metal plate 45) and a fourth electrode (including a third metal plate 48), wherein the second electrode (including the second metal plate 45) is electrically connected to the third electrode (including the second metal plate 45) to provide a common electrical node; and a radio frequency (RF) antenna is electrically connected to the common electrical node.

[0108] In one embodiment, the first PCM switch 101 includes a first heater element 501 located between the first electrode (including a first metal plate 42) and the second electrode (including a second metal plate 45); the second PCM switch 102 includes a second heater element 502 located between the third electrode (including the second metal plate 45) and the fourth electrode (including a third metal plate 48); and each of the first heater element 501 and the second heater element 502 includes a collection of at least one metallic material that is the same as the first electrode (including a first metal plate 42).

[0109] In one embodiment, the first PCM switch 101 includes a first phase change material portion; the second PCM switch 102 includes a second phase change material portion; and the first phase change material portion and the second phase change material portion are corresponding portions of a single continuous phase change material portion 70 extending above each of the first heater element 501 and the second heater element 502.

[0110] In one embodiment, a single continuous phase change material portion 70 extends laterally along a first horizontal direction hd1 and has a uniform width along a second horizontal direction hd2, and contacts the top surfaces of a first electrode (including a first metal plate 42), a second electrode (including a second metal plate 45), a third electrode (including a second metal plate 45), and a fourth electrode (including a third metal plate 48).

[0111] In one embodiment, the second electrode (including a second metal plate 45) and the third electrode (including a second metal plate 45) are formed as a single metal plate (such as the second metal plate 45).

[0112] In one embodiment, the device structure further includes: a second dielectric material layer (80, 90) above the first PCM switch 101 and the second PCM switch 102; and a metal via structure extending vertically through a bottom layer of the second dielectric material layer (80, 90) and contacting a top surface of the single metal plate (such as the second metal plate 45), wherein the RF antenna is electrically connected to the metal plate via the metal via structure.

[0113] In one embodiment, a first subset of the first metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648, 21, 32, 38) provides a first conductive path between the first electrode (including a first metal plate 42) and an output node of the power amplifier 701; a second subset of the first metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648, 21, 32, 38) provides a second conductive path between the fourth electrode (including a third metal plate 48) and an input node of the low-noise amplifier 702; the output node of the power amplifier 701 is the only electrical node of the semiconductor circuit 700 electrically connected to the first electrode (including a first metal plate 42), and the input node of the low-noise amplifier 702 is the only electrical node of the semiconductor circuit 700 electrically connected to the fourth electrode (including a third metal plate 48).

[0114] The various embodiments disclosed herein offer an improvement over conventional single-pull double-throw (SPDT) switches used in RF signal switching. By leveraging the unique properties of PCM materials, the disclosed SPDT PCM switches provide superior isolation and low power consumption, while simplifying the overall design by eliminating shunt cells. This feature not only reduces parasitic capacitance but also minimizes the device footprint, making it highly suitable for applications requiring compact and efficient RF signal switching. The inherent advantages of PCM materials, such as the ability to precisely control switching between high and low resistance states, further enhance the performance and reliability of the SPDT PCM switches. Thus, the various embodiments disclosed herein present robust solutions for next-generation RF switching applications, resulting in improved isolation, reduced power consumption, and a simplified circuit design, ultimately contributing to advancements in semiconductor technology.

[0115] In a non-limiting exemplary embodiment, a method for forming a device structure is provided, comprising: forming a semiconductor circuit including a power amplifier and a low-noise amplifier on a substrate; forming a metal interconnect structure in a first dielectric material layer above the power amplifier and the low-noise amplifier; forming a first phase change material (PCM) switch and a second PCM switch above the first dielectric material layer, wherein the first PCM switch includes a first electrode and a second electrode, and the second PCM switch includes a third electrode and a fourth electrode, wherein the second electrode is electrically connected to the third electrode to form a common electrical node; and electrically connecting a radio frequency (RF) antenna to the common electrical node.

[0116] In a non-limiting exemplary embodiment, a first subset of the metal interconnect structure provides a first conductive path between the first electrode and an output node of the power amplifier; and a second subset of the metal interconnect structure provides a second conductive path between the fourth electrode and an input node of the low-noise amplifier.

[0117] In a non-limiting exemplary embodiment, the output node of the power amplifier is the only electrical node of the semiconductor circuit electrically connected to the first electrode; and the input node of the low-noise amplifier is the only electrical node of the semiconductor circuit electrically connected to the fourth electrode.

[0118] In a non-limiting exemplary embodiment, the method further includes: depositing at least one metal material layer above a top surface of the first dielectric material layer; and patterning the at least one metal material layer, wherein the patterned portion of the at least one metal material layer includes a first heater element, a second heater element, the first electrode, the second electrode, the third electrode, and the fourth electrode.

[0119] In a non-limiting exemplary embodiment, one of the patterned portions of the at least one metal material layer includes a metal plate; and the second electrode and the third electrode are formed as the metal plate.

[0120] In a non-limiting exemplary embodiment, the method further includes: forming a second dielectric material layer over the first PCM switch and the second PCM switch; and forming a metal via structure at the bottom layer of the second dielectric material layer through a top surface of the metal plate, wherein the RF antenna is electrically connected to the metal plate via the metal via structure.

[0121] In a non-limiting exemplary embodiment, the method further includes: depositing a phase change material layer over the first electrode, the first heater element, the second electrode, the third electrode, the second heater element, and the fourth electrode; and patterning the phase change material layer, wherein a first patterned portion of the phase change material extends over the first electrode, the first heater element, and the second electrode, and a second patterned portion of the phase change material extends over the third electrode, the second heater element, and the fourth electrode.

[0122] In a non-limiting exemplary embodiment, the first patterned portion and the second patterned portion are corresponding portions formed as a single continuous phase change material portion extending over each of the first heater element and the second heater element.

[0123] In a non-limiting exemplary embodiment, a method for forming an apparatus structure is provided, comprising: forming a semiconductor circuit on a substrate; forming a first metal plate, a second metal plate, a third metal plate, a first heater element, and a second heater element on a top surface of a first dielectric material layer, wherein the first heater element is formed between the first metal plate and the second metal plate, and the second heater element is formed between the second metal plate and the third metal plate; and forming a first phase change material (PCM) switch and a second PCM switch above the first dielectric material layer, wherein the second metal plate is a common electrode of the first PCM switch and the second PCM switch.

[0124] In a non-limiting exemplary embodiment, the semiconductor circuit includes a power amplifier and a low-noise amplifier; and the first metal plate is electrically connected to an output node of the power amplifier, and the third metal plate is electrically connected to an input node of the low-noise amplifier.

[0125] In a non-limiting exemplary embodiment, the method further includes: forming a metal interconnect structure within a first dielectric material layer above the power amplifier and the low-noise amplifier, wherein: a first subset of the metal interconnect structure provides a first conductive path between the first metal plate and an output node of the power amplifier; and a second subset of the metal interconnect structure provides a second conductive path between the third metal plate and an input node of the low-noise amplifier.

[0126] In a non-limiting exemplary embodiment, the method further includes: depositing a phase change material layer over the first metal plate, the second metal plate, the third metal plate, the first heater element, and the second heater element; and patterning the phase change material layer, wherein a first patterned portion of the phase change material extends over a first portion of the first metal plate, the first heater element, and the second metal plate, and a second patterned portion of the phase change material extends over a second portion of the second metal plate, the second heater element, and the third metal plate, wherein the first patterned portion and the second patterned portion are corresponding portions of a single continuous phase change material portion extending over each of the first heater element and the second heater element.

[0127] In a non-limiting exemplary embodiment, the method further includes: forming a second dielectric material layer over the first PCM switch and the second PCM switch; forming a metal via structure directly through a bottom layer of the second dielectric material layer on a top surface of one of the first metal plate, the second metal plate, or the third metal plate; and electrically connecting a radio frequency (RF) antenna to the metal via structure by forming the RF antenna over the second dielectric material layer or by attaching a structure including the RF antenna to an assembly containing the substrate, the first dielectric material layer, and the second dielectric material layer.

[0128] In a non-limiting exemplary embodiment, a device structure is provided, comprising: a semiconductor device including a power amplifier and a low-noise amplifier and overlying a substrate; an interconnect structure overlying the power amplifier and the low-noise amplifier; a first phase change material (PCM) switch and a second PCM switch located above the interconnect structure, wherein the first PCM switch includes a first electrode and a second electrode, and the second PCM switch includes a third electrode and a fourth electrode, wherein the second electrode is electrically connected to the third electrode to provide a common electrical node; and a radio frequency (RF) antenna electrically connected to the common electrical node.

[0129] In a non-limiting exemplary embodiment, the first PCM switch includes a first heater element located between the first electrode and the second electrode; the second PCM switch includes a second heater element located between the third electrode and the fourth electrode; and each of the first heater element and the second heater element comprises a collection of at least one metallic material identical to the first electrode.

[0130] In a non-limiting exemplary embodiment, the first PCM switch includes a first phase change material portion; the second PCM switch includes a second phase change material portion; and the first phase change material portion and the second phase change material portion are corresponding portions of a single continuous phase change material portion extending above each of the first heater element and the second heater element.

[0131] In a non-limiting exemplary embodiment, the single continuous phase change material portion extends laterally along a first horizontal direction and has a substantially uniform width along a second horizontal direction, and contacts the top surfaces of the first electrode, the second electrode, the third electrode, and the fourth electrode.

[0132] In a non-limiting exemplary embodiment, the second electrode and the third electrode are formed as a single metal plate.

[0133] In a non-limiting exemplary embodiment, the device structure further includes: a second dielectric material layer above the first PCM switch and the second PCM switch; and a metal via structure extending vertically through a bottom layer of the second dielectric material layer and contacting a top surface of the single metal plate, wherein the RF antenna is electrically connected to the single metal plate via the metal via structure.

[0134] In a non-limiting exemplary embodiment, a first subset of the interconnect structure provides a first conductive path between the first electrode and an output node of the power amplifier; a second subset of the interconnect structure provides a second conductive path between the fourth electrode and an input node of the low-noise amplifier; the output node of the power amplifier is the only electrical node of the semiconductor circuit electrically connected to the first electrode; and the input node of the low-noise amplifier is the only electrical node of the semiconductor circuit electrically connected to the fourth electrode.

[0135] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. The embodiments described using the term "comprising" also inherently disclose that the term "comprising" may be replaced in some embodiments with the term "substantially consisting of" or the term "consisting of," unless otherwise explicitly disclosed herein. Whenever two or more elements are listed in the same paragraph or in different paragraphs as alternatives, a Markush group comprising a list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in this disclosure to describe the execution of a step in the formation or processing of an element, it explicitly covers embodiments in which such an element or such step is not performed, provided that the resulting device or apparatus provides an equivalent result. Therefore, when applied to the execution of a step in the formation or processing of an element, whenever omitting the formation of this element or this step can provide the same or equivalent result, the auxiliary verb "can" is also understood to mean "may" or "may, or may not," where equivalent results include slightly superior results and slightly inferior results. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they may make various changes, substitutions, and alterations to this disclosure without departing from its spirit and scope.

Claims

1. A semiconductor device structure, comprising: Semiconductor circuits located on a substrate; The first dielectric material layer located on top of the semiconductor circuit; A first metal plate, a second metal plate, a third metal plate, a first heater element, and a second heater element are located on the top surface of the first dielectric material layer, wherein the first heater element is located between the first metal plate and the second metal plate, and the second heater element is located between the second metal plate and the third metal plate; and A first phase change material switch and a second phase change material switch are located above the first dielectric material layer, wherein the second metal plate is the common electrode of the first phase change material switch and the second phase change material switch.

2. The semiconductor device structure according to claim 1, characterized in that: The first phase change material switch includes a first phase change material portion extending above the first metal plate, the first heater element, and a first portion of the second metal plate; the second phase change material switch includes a second phase change material portion extending above the second portion of the second metal plate, the second heater element, and the third metal plate; and the first phase change material portion and the second phase change material portion are corresponding portions of a single continuous phase change material portion extending above each of the first heater element and the second heater element.

3. The semiconductor device structure according to claim 2, characterized in that: The semiconductor device structure also includes A second dielectric material layer located above the first phase change material switch and the second phase change material switch; A metal through-hole structure that directly contacts the top surface of one of the first metal plate, the second metal plate, or the third metal plate, the metal through-hole structure passing through the bottom layer of the second dielectric material layer; The radio frequency antenna is electrically connected to the metal through-hole structure.

4. A semiconductor device structure, comprising: A semiconductor device comprising a power amplifier and a low-noise amplifier and covered by a substrate; An interconnection structure covering the power amplifier and the low-noise amplifier; A first phase change material (PCM) switch and a second PCM switch are located above the interconnect structure. The first PCM switch includes a first electrode and a second electrode, and the second PCM switch includes a third electrode and a fourth electrode. The second electrode is electrically connected to the third electrode to provide a common electrical node. The radio frequency antenna is electrically connected to this common electrical node.

5. The semiconductor device structure according to claim 4, characterized in that: The first phase change material switch includes a first heater element located between the first electrode and the second electrode; The second phase change material switch includes a second heater element located between the third electrode and the fourth electrode; and Each of the first heater element and the second heater element comprises a collection of at least one metallic material that is the same as the first electrode.

6. The semiconductor device structure according to claim 5, characterized in that: The first phase change material switch includes a first phase change material portion; the second phase change material switch includes a second phase change material portion; and the first phase change material portion and the second phase change material portion are corresponding portions of a single continuous phase change material portion extending above each of the first heater element and the second heater element.

7. The semiconductor device structure according to claim 6, characterized in that: The single, continuous phase change material portion extends laterally along a first horizontal direction and has a uniform width along a second horizontal direction, and contacts the top surfaces of the first electrode, the second electrode, the third electrode, and the fourth electrode.

8. The semiconductor device structure according to claim 4, characterized in that: The second electrode and the third electrode are formed as a single metal plate.

9. The semiconductor device structure according to claim 8, characterized in that: The semiconductor device structure further includes a second dielectric material layer above the first phase change material switch and the second phase change material switch; and a metal via structure extending vertically through the bottom layer of the second dielectric material layer and contacting the top surface of the single metal plate, wherein the radio frequency antenna is electrically connected to the single metal plate via the metal via structure.

10. The semiconductor device structure according to claim 4, characterized in that: A first subset of the interconnect structure provides a first conductive path between the first electrode and an output node of the power amplifier; A second subset of the interconnect structure provides a second conductive path between the fourth electrode and an input node of the low-noise amplifier; The output node of the power amplifier is the only electrical node of the semiconductor device that is electrically connected to the first electrode; and The input node of the low-noise amplifier is the only electrical node of the semiconductor device that is electrically connected to the fourth electrode.

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