Heat dissipation structure of power device
By setting groove structures on the electrodes of the power chip and protruding structures on the substrate to form a stacked wall structure, the problem of insufficient heat dissipation of power semiconductor chips is solved, achieving more efficient heat dissipation and lower cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 北京怀柔实验室
- Filing Date
- 2025-05-21
- Publication Date
- 2026-05-19
AI Technical Summary
In existing technologies, power semiconductor chips have insufficient heat dissipation capabilities, resulting in high chip costs, low current density, and the heat dissipation area is dependent on the chip size, making it difficult to optimize.
Multiple first groove structures are set on the electrodes of the power chip, and matching first protrusion structures are set on the substrate to form a concave-convex wall structure, which increases the contact area between the electrodes and the substrate and improves the heat transfer efficiency.
It improves the chip's heat dissipation capacity, reduces costs, increases current density, and enhances heat dissipation performance without increasing chip size.
Smart Images
Figure CN224265443U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a heat dissipation structure for a power device. Background Technology
[0002] With the continuous development of power semiconductor technology, the demand for power semiconductor chips in various fields such as electric vehicles, rail transit, and smart grids is increasing. Power semiconductor chips are evolving towards higher blocking voltage and higher current density, thus requiring a focus on heat dissipation technology. Currently, the main solutions to the heat dissipation challenges of power semiconductors are focused on optimizing chip packaging structure and processes, with little emphasis on optimizing the heat dissipation structure from the chip structure perspective.
[0003] In existing technologies, power semiconductor chips of various materials and types often use flat metal structures as electrodes. Through a soldering process, the chip is fixed onto a direct-bonded copper (DBC) board. The chip dissipates heat through the solder layer and the DBC board. Figure 1 As shown in the diagram, in this structure, the chip can only dissipate heat through the metal on its back, and the heat dissipation area is entirely dependent on the chip size. This is not conducive to reducing chip cost or increasing chip current density. Utility Model Content
[0004] This application provides a heat dissipation structure for power devices to solve the problem of low heat dissipation capacity of power devices in related technologies.
[0005] According to one aspect of this application, a heat dissipation structure for a power device is provided, comprising: a power chip having a first surface; a first electrode located on the first surface, the first electrode having a plurality of first groove structures opposite to the surface of the power chip; and a substrate having a plurality of first protrusion structures on one side of the substrate, the plurality of first protrusion structures matching the plurality of first groove structures, the surface of the first electrode opposite to the power chip contacting the surface of the substrate having the first protrusion structures.
[0006] Optionally, the plurality of first groove structures are arranged in an array along a first direction and a second direction, both of which are parallel to the first surface.
[0007] Optionally, the plurality of first groove structures have a plurality of first end faces near one end of the power chip, and the maximum vertical distance from the first end face to the first surface is equal.
[0008] Optionally, the orthographic projection of the first groove structure on the substrate includes any one or more of the following: rectangle, square, circle, ellipse, triangle, and polygon.
[0009] Optionally, the width of the first groove structure in the first direction and / or the second direction is 200nm~100μm.
[0010] Optionally, the first groove structure has a first depth of 0 nm to 200 μm in the direction perpendicular to the first surface.
[0011] Optionally, the first depth is less than or equal to twice the width.
[0012] Optionally, the spacing between any adjacent first groove structures is 200nm~100μm.
[0013] Optionally, the substrate further includes a solder layer located on the side of the substrate near the first electrode, the solder layer matching the first groove structure and contacting the surface of the first electrode away from the power chip.
[0014] Optionally, the heat dissipation structure further includes: a second electrode located on a second surface of the power chip, the second surface being a surface on the power chip opposite to the first surface, the surface of the second electrode facing away from the power chip having a plurality of second groove structures; and a heat dissipation portion located on the side of the second electrode facing away from the power chip, the heat dissipation portion having a plurality of second protrusion structures on the side near the second electrode, the second groove structures matching the second protrusion structures, and the surface of the second electrode facing away from the power chip contacting the surface of the heat dissipation portion near the power chip.
[0015] This application provides a heat dissipation structure for a power device. The first electrode of the heat dissipation structure has multiple first groove structures, and the substrate has a first protrusion structure. The first protrusion structure contacts and matches the first groove structure of the first electrode, so that the first electrode and the substrate form a concave-convex wall structure, which increases the contact area between the first electrode and the substrate. This increases the heat transfer area of the power chip during operation, and the heat conduction speed is faster, thereby improving the heat dissipation capacity of the chip. At the same time, without affecting the heat dissipation of the power device, the size of the power device can be reduced, the cost can be reduced, and the current density of the chip can be increased. Attached Figure Description
[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0017] Figure 1 A schematic diagram of a cross-sectional structure of a heat dissipation structure for a power device in the prior art is shown;
[0018] Figure 2 This is a cross-sectional schematic diagram of the power chip, the first electrode, and the substrate in a heat dissipation structure of a power device according to an embodiment of this application.
[0019] Figure 3 This is a cross-sectional schematic diagram of a heat dissipation structure for a power device according to an embodiment of this application;
[0020] Figure 4 This is a top view of a first electrode according to an embodiment of this application;
[0021] Figure 5 This is a top view of a first groove structure projected onto a substrate according to an embodiment of this application;
[0022] Figure 6 This is a top view of another first groove structure according to an embodiment of this application projected onto a substrate;
[0023] Figure 7 This is a cross-sectional schematic diagram of a heat dissipation structure for another power device according to an embodiment of this application.
[0024] The above figures include the following reference numerals:
[0025] 10. Power chip; 101. First surface; 102. Second surface; 21. First electrode; 211. First groove structure; 2111. First end face; 22. Second electrode; 221. Second groove structure; 30. Substrate; 311. First protrusion structure; 40. Solder layer; 50. Heat dissipation part; 511. Second protrusion structure. Detailed Implementation
[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, products, or devices.
[0029] As described in the background section, existing power semiconductor chips are trending towards higher blocking voltages and larger current densities. Solving the heat dissipation challenges of power semiconductors primarily focuses on optimizing chip packaging structure and processes, with little optimization of the heat dissipation structure from the chip structure perspective. Power semiconductor chips of various materials and types often use flat metal structures as electrodes. Through a soldering process, the chip is fixed to a DBC board, and heat dissipation is achieved through the solder layer and the DBC board. Figure 1 As shown, in this heat dissipation structure, a first electrode 21 and a second electrode 22 are respectively provided on the back and front sides of the power chip 10. A solder layer 40 and a substrate 30 are disposed on the side of the first electrode 21 away from the power chip 10. The surfaces of the first electrode 21, the solder layer 40, and the substrate 30 that come into contact with each other are all planar structures. The heat of the power chip 10 is transferred away through the first electrode 21, the solder layer 40, and the substrate 30 for heat dissipation. The heat dissipation area and heat dissipation capacity of the above structure depend entirely on the size of the power chip 10. Increasing the size of the power chip 10 is necessary to increase the heat dissipation area of the heat dissipation structure, which is not conducive to reducing chip cost and increasing chip current density. To solve the above problems, this application provides a heat dissipation structure for a power device.
[0030] According to one aspect of this application, a heat dissipation structure for a power device is provided, such as... Figures 2 to 3 As shown, the heat dissipation structure includes: a power chip 10 having a first surface 101; a first electrode 21 located on the first surface 101; and a substrate 30. Specifically, as shown... Figure 2 As shown, a plurality of first protrusions 311 are present on one side of the substrate 30, and a plurality of first grooves 211 are present on the surface of the first electrode 21 facing away from the power chip 10; the plurality of first protrusions 311 and the plurality of first grooves 211 are matched, and after the surface of the first electrode 21 facing away from the power chip 10 contacts the surface of the substrate 30 with the first protrusions 311, a shape is formed as shown. Figure 3The heat dissipation structure shown has a first electrode 21 with multiple first groove structures 211 and a first protrusion structure 311 on the substrate 30. The first protrusion structure 311 contacts and matches the first groove structure 211 of the first electrode 21, forming a concave-convex wall structure between the first electrode 21 and the substrate 30. This increases the contact area between the first electrode 21 and the substrate 30, thereby increasing the heat transfer area of the power chip during operation and accelerating the heat conduction speed. This improves the heat dissipation capacity of the chip. At the same time, without affecting the heat dissipation of the power device, the size of the power device can be reduced, the cost can be reduced, and the current density of the chip can be increased.
[0031] In some embodiments, such as Figure 3 As shown, a second electrode 22 is formed on the side of the power chip 10 away from the first electrode 21, which can further increase the heat dissipation capacity of the heat dissipation structure of the power device.
[0032] Specifically, the aforementioned power chip includes, but is not limited to, any one of the following: metal-oxide-semiconductor field-effect transistor (MOSFET) power chip, insulated-gate bipolar transistor (IGBT) power chip, silicon carbide power chip, and gallium nitride power chip. This application does not specifically limit the type of power chip. Furthermore, the material of the first electrode includes, but is not limited to, aluminum, silver, gold, graphene, or a combination of one or more conductive materials. This application does not specifically limit this, and the thickness of the first electrode is 0 nm to 200 μm.
[0033] In addition, the above-mentioned heat dissipation structure preparation steps include: first, forming a first conductive material layer on the first surface of the power chip using a deposition process; then, forming a plurality of first groove structures on the side of the first conductive material layer away from the power chip using an etching process to form a first electrode; then, embedding a substrate having a plurality of first protrusion structures into the first groove structure of the first electrode, wherein the plurality of first protrusion structures match the plurality of first groove structures.
[0034] The deposition processes include, but are not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD). PVD includes, but is not limited to, magnetron sputtering, reactive sputtering, DC sputtering, AC sputtering, vacuum deposition, and arc evaporation. CVD includes, but is not limited to, Plasma Enhanced Chemical Vapor Deposition (PECVD), Metal-Organic Chemical Vapor Deposition (MOCVD), and Laser-Induced Chemical Vapor Deposition (LCVD). Those skilled in the art may select appropriate processes based on actual needs, and no specific limitations are imposed without application.
[0035] Etching processes can include dry etching and wet etching. Dry etching includes physical etching, chemical vapor deposition (CVD), and plasma etching. Wet etching uses liquid chemicals to dissolve or corrode materials. Etching processes also include deep reactive ion etching (DRIE), laser etching, ion beam etching, and electrolyte etching. Those skilled in the art can choose the appropriate process based on actual needs; no specific limitations are imposed without application.
[0036] In addition, the aforementioned substrates may include metal substrates, ceramic substrates, and organic substrates. The materials of the metal substrates include, but are not limited to, alloys of one or more of aluminum, copper, tungsten, and molybdenum, to give the metal substrates excellent heat dissipation performance, machinability, electromagnetic shielding performance, and dimensional stability. The materials of the ceramic substrates include, but are not limited to, one or more of alumina, aluminum nitride, and silicon nitride. These materials have high thermal conductivity and low coefficient of thermal expansion, giving the ceramic substrates high strength, good insulation, and excellent thermal conductivity and heat resistance. Organic substrates have low dielectric constant, low dielectric loss, low moisture absorption, and high heat resistance, but the thermal conductivity and mechanical strength of organic substrates are relatively low, making them suitable for some conditions where performance requirements are not high.
[0037] For example, the substrate may include a Direct Bonded Copper (DBC) substrate, which is a substrate manufactured using the DBC process. It can also be called a DBC ceramic substrate or a copper-clad ceramic substrate. The DBC substrate has high thermal conductivity and electrical insulation, high mechanical strength, low coefficient of expansion and excellent welding performance. It can be used in the heat dissipation structure of various power devices to improve the heat dissipation performance and stability of the devices.
[0038] In some alternative embodiments, a plurality of first groove structures are arranged in an array along a first direction and a second direction, both of which are parallel to the first surface.
[0039] Specifically, such as Figure 4 As shown in the top view of the first electrode 21 in the above embodiment, the first groove structure 211 is arranged in an array along the X and Y directions, wherein the X and Y directions are perpendicular to each other. This allows the heat dissipation structure to have more first groove structures 211 in a limited space, increasing the heat dissipation area and saving space. On the other hand, it makes the arrangement of the heat dissipation structure more regular, which is beneficial to simplifying the manufacturing process.
[0040] In some alternative implementations, the plurality of first groove structures have a plurality of first end faces near one end of the power chip, and the maximum vertical distance from the first end face to the first surface is equal.
[0041] Specifically, such as Figure 2 As shown, the first electrode 21 has multiple first groove structures 211. Each first groove structure 211 has a first end face 2111 at the end near the power chip 10. The vertical distance H from each first end face 2111 to the first surface 101 of the power chip is equal. The first groove structure 211 can be formed by etching. The equal vertical distance H from each first end face 2111 to the first surface 101 can reduce the difficulty of the etching process and reduce the manufacturing cost. At the same time, the first protrusion structure 311 of the substrate 30 matches the first groove structure 211. The equal vertical distance from each first end face 2111 to the first surface 101 can also reduce the difficulty of the substrate 30 manufacturing, thus achieving a better match between the first groove structure 211 of the first electrode 21 and the first protrusion structure 311 of the substrate 30.
[0042] In some alternative embodiments, the orthographic projection of the first groove structure onto the substrate includes any one or more of the following: rectangle, square, circle, ellipse, triangle, and polygon.
[0043] Specifically, such as Figure 5 As shown, the orthographic projection of the first groove structure 211 onto the substrate 30 is a square; as Figure 6As shown, the orthographic projection of the first groove structure 211 onto the substrate 30 is a circle. It should be noted that the orthographic projection of the first groove structure onto the substrate is not limited to the shape described above; it can also be a rectangle, triangle, ellipse, or polygon, etc., which will not be elaborated upon in this application. In addition, when the orthographic projection of the first groove structure onto the substrate is a polygon, it includes not only regular polygons but also irregular polygons, which will not be specifically limited in this application.
[0044] In a heat dissipation structure, the areas of the orthographic projections of each first groove structure onto the substrate may be equal or unequal; that is, the shape and size of the orthographic projections of the first groove structure onto the substrate are not specifically limited in this application. Furthermore, in a heat dissipation structure, each orthographic projection may include the same shape or different shapes. For example, in a heat dissipation structure with m first groove structures, m / 2 of the first groove structures have square orthographic projections, and m / 2 of the first groove structures have circular orthographic projections. The specific shape of the orthographic projections of the first groove structures onto the substrate is also not specifically limited in this application; those skilled in the art can choose according to product requirements.
[0045] In some alternative implementations, such as Figure 2 As shown, the first groove structure 211 has a first depth BD of 0nm~200μm in the direction perpendicular to the first surface.
[0046] Specifically, the function of the first electrode is to effectively dissipate the heat generated by the power chip during operation, preventing damage caused by heat concentration due to excessive operating power. During the power chip packaging process, the first electrode connects the power chip to the substrate. When the chip generates heat during operation, this heat is transferred to the substrate through the first electrode. The substrate, with its excellent heat dissipation capabilities, can transfer the heat away from the chip, thereby maintaining the chip's normal operating temperature and ensuring the stability and reliability of the power chip.
[0047] The first electrode, serving as a heat dissipation electrode, directly impacts the heat dissipation performance of the power chip. If it's too thin, insufficient heat dissipation area and channels will be provided, leading to overheating and performance degradation. Conversely, while a thicker first electrode increases the heat dissipation area, it also increases package size and cost, while reducing heat transfer efficiency. Furthermore, the thickness of the first electrode affects the stability and reliability of the power chip, thus influencing the overall system performance and stability. Therefore, the thickness of the first electrode is set between 0 nm and 200 μm to maintain the stability of the power chip and improve the heat dissipation performance of the heat dissipation structure.
[0048] Furthermore, the main function of the first groove is to increase the heat dissipation performance of the heat dissipation structure. The depth of the first groove structure is between 0nm and 200μm, and the depth of the first groove structure is between 0 and the thickness of the first electrode, so as to increase the heat dissipation area and heat dissipation function of the heat dissipation structure.
[0049] In some alternative implementations, such as Figure 2 As shown, the width BI of the first groove structure 211 in the first direction and / or the second direction is 200nm~100μm.
[0050] Specifically, power chips are generally classified into small power chips (20-30 mm in size), medium power chips (30-50 mm in size), and large power chips (over 100 mm in size). In the heat dissipation structure of a power chip, the more first groove structures there are, the larger the heat dissipation area. The width of the first groove structure in the first and / or second directions is 200 nm to 100 μm. Multiple first groove structures can be set in various types of power chips, ensuring that the number of first groove structures is greater than 150, increasing the heat dissipation area between the first electrode and the substrate, thereby enhancing the heat dissipation function of the power chip.
[0051] In some alternative implementations, such as Figure 2 As shown, the spacing BL between any two adjacent first groove structures 211 is 200nm~100μm.
[0052] Specifically, by effectively setting the spacing between the first groove structures, the number of first groove structures can be further controlled, increasing the heat dissipation capacity of the heat dissipation structure while reducing the stress on the first electrode and improving its welding performance. In this application, the spacing between any adjacent first groove structures is 200nm~100μm. Simultaneously, first protrusion structures corresponding to the spacing are provided on the substrate, further increasing the heat dissipation capacity of the heat dissipation structure, allowing heat to dissipate quickly, while also giving the heat dissipation structure high mechanical strength and welding performance. This enables the heat dissipation structure to withstand greater mechanical stress and temperature changes, and facilitates the assembly and connection of the heat dissipation structure.
[0053] In some alternative implementations, such as Figure 2 As shown, the first depth BD is less than or equal to twice the width BI.
[0054] Specifically, the first electrode is etched to form multiple first groove structures on the side of the first electrode facing away from the power chip. Here, the first depth BD is the depth of the first trench etching, and the width BI is the width of the first trench etching. During the etching process, the first depth BD is set to be ≤2 times the width BI. This is because existing processes can only achieve narrow and deep trench etching. If multiple narrow and deep trenches are formed on the first electrode, stress can cause structural instability and deformation of the first electrode, potentially leading to collapse or damage of the stacking structure under subsequent processing or usage conditions (such as high temperature or external force), affecting the chip's performance and reliability. Furthermore, if the first electrode has a thick protrusion, it will create high thermal resistance between the protrusion and the substrate contact surface, reducing heat dissipation efficiency. The condition of BD ≤ 2BI helps maintain low thermal resistance, ensuring efficient heat transfer from the chip to the heat dissipation substrate while optimizing the contact area to volume ratio. This allows for an increase in the heat dissipation contact area without excessively increasing the electrode volume, thus improving heat dissipation performance while maintaining a reasonable overall chip size and weight.
[0055] In some alternative implementations, such as Figure 3 As shown, the substrate also includes a solder layer 40, which is located on the side of the substrate 30 near the first electrode 21. The solder layer matches the first groove structure 211 and contacts the surface of the first electrode 21 away from the power chip 10.
[0056] Specifically, in the power chip packaging process, the solder layer is a metal layer used to connect the power chip and the substrate. The solder layer, and the first groove structure on the first electrode are welded to the substrate with the protruding structure by solder pads, thereby realizing the electrical connection and mechanical fixation between the power chip and the substrate. The soldering process of the solder layer includes, but is not limited to, traditional lead-tin soldering, nano-silver sintering, etc.
[0057] The first groove structure of the first electrode matches the first protrusion structure of the substrate and is connected by a solder layer. This increases the contact area between the first electrode and the substrate and improves heat dissipation. At the same time, the solder layer provides electrical connection and mechanical fixation between the power chip and the substrate, ensuring that the signal and power of the power chip can be efficiently transmitted to the external circuit. It can also firmly fix the power chip on the substrate, preventing displacement and detachment of the power chip from the substrate during subsequent processing and use. In addition, as a heat conduction channel, the solder layer can effectively transfer the heat generated by the chip to the heat dissipation structure, thereby maintaining the normal operation of the chip. The solder layer can also protect the chip and extend its service life.
[0058] In some alternative implementations, such as Figure 7As shown, the heat dissipation structure further includes: a second electrode 22, which is located on the second surface 102 of the power chip 10. The second surface 102 is the surface of the power chip opposite to the first surface 101. The surface of the second electrode 22 away from the power chip 10 has a plurality of second groove structures 221; and a heat dissipation part 50, which is located on the side of the second electrode 22 away from the power chip 10. The heat dissipation part 50 has a plurality of second protrusion structures 511 on the side near the second electrode 22. The second groove structures 221 match the second protrusion structures 511. The surface of the second electrode 22 away from the power chip 10 is in contact with the surface of the heat dissipation part 50 near the power chip 10. Figure 7 The positional relationships of the other structures shown in the figure are similar to those of the structures shown in the figure. Figure 2 The positional relationships of the structures are the same, so they will not be repeated here.
[0059] Specifically, such as Figure 7 As shown, based on the same principle, a second electrode 22 is deposited on the second surface 102 of the power chip 10, which is opposite to the first surface 101. The side of the second electrode 22 away from the power chip 10 also has a plurality of second groove structures 221 that are the same as the first groove structure of the first electrode 21. A heat dissipation part 50 is formed on the second groove structure 221, and the heat dissipation part 50 has a plurality of second protrusion structures 511 that are the same as the first protrusion structure of the substrate 30. The second groove structure 221 and the plurality of second protrusion structures 511 are in one-to-one contact and match, thereby increasing the heat dissipation channel of the second surface 102 of the power chip 10, further increasing the contact area and heat dissipation function of the power chip heat dissipation structure, and achieving better heat dissipation.
[0060] For example, the heat dissipation part includes copper foil or copper block, both of which have good thermal conductivity and electrical conductivity, and can efficiently dissipate the heat of the power chip.
[0061] In some specific embodiments, multiple second groove structures are arranged in an array along a first direction and a second direction, both of which are parallel to the first surface; the ends of the multiple second groove structures near the power chip have multiple second end faces, and the maximum vertical distance from the second end faces to the second surface is equal; the orthographic projection of the second groove structure on the substrate includes any one or more of rectangles, squares, circles, ellipses, and polygons; the second thickness of the second groove structure in the direction perpendicular to the second surface is 0 nm to 200 μm; the width of the second groove structure in the first direction and / or the second direction is 200 nm to 100 μm; the spacing between any adjacent second groove structures is 200 nm to 100 μm; the second thickness is less than or equal to twice the width of the second groove structure. The heat dissipation part can satisfy one or more of the above conditions, all of which can improve the heat dissipation capacity of the heat dissipation structure. This application does not make specific limitations.
[0062] The heat dissipation structure of the power device of this application will be further described below with reference to embodiments.
[0063] Example 1
[0064] The fabrication of the heat dissipation structure for the power device provided in this embodiment includes the following steps:
[0065] A silicon carbide MOSFET power chip is provided;
[0066] A first electrode and a second electrode are formed on opposite surfaces of a provided power chip using a deposition process, wherein the first electrode and the second electrode are made of aluminum and both have a thickness of 100 μm.
[0067] Multiple square first groove structures are formed on the side of the first electrode away from the power chip using an etching process. The depth of the first groove structure is 2μm, the width of the first groove is 2μm, and the spacing between adjacent first groove structures is 2μm.
[0068] The first electrode is soldered onto the DBC substrate, which also has a first convex structure, using a lead-tin soldering process.
[0069] Example 2
[0070] The fabrication of another heat dissipation structure for a power device provided in this embodiment includes the following steps:
[0071] A silicon IGBT power chip is provided;
[0072] A first electrode and a second electrode are formed on opposite surfaces of a provided power chip using a deposition process, wherein the first electrode and the second electrode are made of aluminum and both have a thickness of 100 μm.
[0073] Multiple square first groove structures are formed on the side of the first electrode away from the power chip using an etching process. The depth of the first groove structure is 2μm, the groove width is 2μm, and the spacing between adjacent first groove structures is 2μm.
[0074] Multiple square second groove structures are formed on the side of the second electrode away from the power chip using a process. The depth of the second groove structure is 2μm, the groove width is 2μm, and the spacing between adjacent second groove structures is 2μm.
[0075] The first electrode is soldered onto the DBC substrate with the first protrusion structure using a lead-tin soldering process, wherein the first groove structure of the first electrode matches the first protrusion structure.
[0076] The second electrode is connected to the copper foil heat dissipation part with the second protrusion structure by a bonding process, wherein the second groove structure of the second electrode matches the second protrusion structure.
[0077] Comparative Example 1
[0078] The fabrication of a heat dissipation structure for a power device provided in this comparative example includes the following steps:
[0079] Provide a MOSFET power chip;
[0080] A first electrode and a second electrode are formed on opposite surfaces of a provided power chip using a deposition process, wherein the first electrode and the second electrode are made of aluminum and both have a thickness of 100 μm.
[0081] The first electrode is soldered onto the DBC substrate using a lead-tin soldering process.
[0082] Compared to Comparative Example 1, Example 1 shows that the heat dissipation area of the first electrode is increased by more than 50%, resulting in better heat dissipation. Compared to Comparative Example 1, Example 2 shows that the heat dissipation area of both the first and second electrodes is increased by more than 50%, further achieving better heat dissipation.
[0083] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or apparatus that includes that element.
[0084] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
Claims
1. A heat dissipation structure for a power device, characterized in that, include: A power chip having a first surface; A first electrode is located on the first surface, and the first electrode has a plurality of first groove structures on the surface of the power chip away from the surface of the power chip. The substrate has a plurality of first protrusions on one side, the plurality of first protrusions matching a plurality of first grooves, and the surface of the first electrode opposite to the power chip is in contact with the surface of the substrate having the first protrusions.
2. The heat dissipation structure of the power device according to claim 1, characterized in that, The plurality of first groove structures are arranged in an array along a first direction and a second direction, both of which are parallel to the first surface.
3. The heat dissipation structure of the power device according to claim 1, characterized in that, Each of the first groove structures has a plurality of first end faces near one end of the power chip, and the maximum vertical distance from the first end face to the first surface is equal.
4. The heat dissipation structure of the power device according to claim 1, characterized in that, The orthographic projection of the first groove structure onto the substrate includes any one or more of the following: rectangle, square, circle, ellipse, and triangle.
5. The heat dissipation structure of the power device according to claim 2, characterized in that, The width of the first groove structure in the first direction and / or the second direction is 200nm~100μm.
6. The heat dissipation structure of the power device according to claim 5, characterized in that, The first groove structure has a first depth of 0 nm to 200 μm in the direction perpendicular to the first surface.
7. The heat dissipation structure of the power device according to claim 6, characterized in that, The first depth is less than or equal to twice the width.
8. The heat dissipation structure of the power device according to claim 1, characterized in that, The spacing between any adjacent first groove structures is 200nm~100μm.
9. The heat dissipation structure of the power device according to claim 1, characterized in that, The substrate further includes: A solder layer is located on the side of the substrate near the first electrode, the solder layer matches the first groove structure and contacts the surface of the first electrode opposite to the power chip.
10. The heat dissipation structure of the power device according to claim 1, characterized in that, The heat dissipation structure also includes: The second electrode is located on the second surface of the power chip. The second surface is the surface of the power chip that is opposite to the first surface. The second electrode has a plurality of second groove structures on the surface of the power chip away from the surface of the power chip. The heat dissipation part is located on the side of the second electrode away from the power chip. The heat dissipation part has a plurality of second protrusion structures on the side near the second electrode. The second groove structure matches the second protrusion structures. The surface of the second electrode away from the power chip is in contact with the surface of the heat dissipation part near the power chip.