Chip direct packaging module system

Abstract

The utility model discloses a chip direct packaging module system, and relates to the technical field of integrated circuits. Comprising an outer packaging module, a substrate main body and an integrated circuit chip, at least one layer of substrate main body is sealed and packaged in the outer packaging module; the integrated circuit chip core is welded on a circuit of the substrate main body; the outer packaging module is filled with non-conductive deformable cooling liquid, and the deformable cooling liquid wraps the peripheral side of the substrate body and the peripheral side of the integrated circuit chip. According to the chip direct packaging module system provided by the utility model, the integrated circuit chip is directly welded on the circuit of the substrate main body, and the circuit on the substrate main body is printed on the substrate main body through a nanometer printing process, so that the line width of a conductive path on the integrated circuit chip can be reduced; the size of the used substrate main body is reduced and the substrate main body adapts to the size of a tablet core; the size of the chip direct packaging module system is far smaller than that of an existing electronic module.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a chip-to-chip direct packaging module system. Background Technology

[0002] The requirements for electronic modules are becoming increasingly stringent, and the size of existing electronic modules is gradually becoming a bottleneck restricting industrial upgrading. The current electronic module technology still follows a multi-level integration model, which involves packaging the chip into a chip structure, assembling the packaged chip with a PCB, and then performing system packaging. The packaged chip will be several times larger in size, and the matching PCB board and circuitry on the PCB board will also require a large space. This technology results in large electronic modules, especially when multiple chips need to be packaged within the electronic module. Such large electronic modules are increasingly unable to meet current industrial needs.

[0003] Therefore, this invention develops a chip-to-chip direct packaging module system to solve the aforementioned technical problems. Summary of the Invention

[0004] The purpose of this invention is to provide a chip-to-chip direct packaging module system to solve the problems existing in the prior art and reduce the size of electronic modules.

[0005] To achieve the above objectives, this utility model provides the following solution:

[0006] This utility model provides a direct chip packaging module system, including an outer packaging module, a substrate body, and an integrated circuit chip; at least one layer of the substrate body is sealed inside the outer packaging module; the integrated circuit chip is soldered onto the circuit of the substrate body; the outer packaging module is filled with a non-conductive variable coolant, and the variable coolant surrounds the outer periphery of the substrate body and the integrated circuit chip.

[0007] Preferably, the circuitry on the substrate body is printed using nanoprinting.

[0008] Preferably, a plurality of integrated circuit chips are soldered onto the circuit of the substrate body.

[0009] Preferably, the substrate body can be made of high-quality thin glass.

[0010] Preferably, the substrate body has multiple layers; each of the integrated circuit chips is electrically connected.

[0011] Preferably, a gap is provided between the substrate body and the outer packaging module.

[0012] Preferably, the outer packaging module is equipped with multiple external interfaces; the external interfaces are electrically connected to the integrated circuit chip.

[0013] The present invention achieves the following technical advantages over the prior art:

[0014] The chip-to-chip packaging module system of this invention significantly reduces the size and enhances the functionality compared to existing electronic modules. In this chip-to-chip packaging module system, the integrated circuit chip is directly soldered onto the circuitry of the substrate body, and the circuitry on the substrate body is printed onto the substrate body using nanoprinting technology. This reduces the linewidth of the conductive paths on the integrated circuit chip, thereby reducing the size of the substrate body while adapting to the size of the chip. Therefore, the chip-to-chip packaging module system of this invention is much smaller than the size of existing electronic modules. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a top view cross-sectional diagram of the single-layer integrated circuit substrate module of this utility model;

[0017] Figure 2 This is a front-view cross-sectional view of the single-layer integrated circuit substrate module of this utility model;

[0018] Figure 3 This is a cross-sectional schematic diagram of the multilayer integrated circuit substrate of this utility model.

[0019] The components include: 1. substrate body; 2. integrated circuit chip; 3. outer packaging module; 4. variable coolant; and 5. external interface. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] The purpose of this invention is to provide a chip-to-chip direct packaging module system to solve the problems existing in the prior art and reduce the size of electronic modules.

[0022] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] This embodiment provides a direct chip packaging module system, including a substrate body 1, an integrated circuit chip 2, and an outer packaging module 3; at least one layer of the substrate body 1 is sealed inside the outer packaging module 3; the integrated circuit chip 2 is soldered onto the circuit of the substrate body 1; the outer packaging module 3 is filled with a non-conductive variable coolant 4, and the variable coolant 4 surrounds the outer periphery of the substrate body 1 and the integrated circuit chip 2.

[0024] Specifically, the circuitry on the substrate body 1 is printed using nanoprinting.

[0025] As a specific implementation of this embodiment, a circuit is printed on the substrate body 1 using a nanoprinter. The unpackaged integrated circuit chip 2 is then placed on the circuit of the substrate body 1 according to the design requirements using an intelligent chip assembly machine. Finally, the pins of the integrated circuit chip 2 are soldered to the circuit on the substrate body 1 using a laser intelligent soldering machine. In this application, the integrated circuit chip 2 is directly soldered onto the circuit of the substrate body 1. Compared with traditional chips, the integrated circuit chip 2 occupies a smaller volume. The conductive path linewidth of the circuit printed on the substrate body 1 using a nanoprinter is narrower, which reduces the volume of the substrate body 1 while accommodating the smaller integrated circuit chip 2. Therefore, the required substrate body 1 is smaller, and the packaged chip direct packaging module system is also smaller.

[0026] Furthermore, in order to enhance the functionality of the optimization module, multiple integrated circuit chips 2 are soldered onto the circuit of the substrate body 1. As a specific implementation of this embodiment, the distance between the unpackaged integrated circuit chips 2 is much smaller than the distance between chips in the prior art, requiring a smaller substrate body 1, thereby further reducing the size of the chip direct packaging module system of this application. At the same time, the chip direct packaging module system is provided with multiple integrated circuit chips 2, which can significantly enhance the functionality of the chip direct packaging module system. Under the same volume, the chip direct packaging module system can install more integrated circuit chips 2, making it more powerful than existing electronic modules of the same volume.

[0027] Furthermore, the substrate body 1 can be made of high-quality thin glass; as a specific implementation of this embodiment, the substrate body 1 uses 0.2 mm glass, which has better insulation properties; by using 0.2 mm glass as the substrate body 1, the thickness of the substrate body 1 is reduced, thereby reducing the overall volume of the electronic module.

[0028] Specifically, the substrate body 1 has multiple layers; each integrated circuit chip 2 is electrically connected; complex or large modules are packaged using a multi-layer substrate body 1 and integrated circuit chips 2 mounted on the substrate body 1 to improve performance; as a specific implementation of this example, the multi-layer substrate body 1 is stacked vertically; when mounting the same number of integrated circuit chips 2, the stacking of the multi-layer substrate body 1 avoids the situation where the length and width of a single-layer substrate body 1 are too long due to the use of a single-layer substrate body 1; the multi-layer setting of the substrate body 1 and the electrical connection between the integrated circuit chips 2 on the substrate body 1 in the case of the multi-layer setting of the substrate body 1 are existing technologies and will not be described in detail here.

[0029] Specifically, a gap is provided between the substrate body 1 and the outer packaging module 3. As a specific implementation of this embodiment, the substrate body 1 located at the bottom layer is fixedly connected to the outer packaging module 3 by multiple pillars, so that a gap is formed between the substrate body 1 and the outer packaging module 3, which facilitates the flow of variable coolant 4 between the substrate body 1 and the outer packaging module 3, thereby improving the heat dissipation efficiency of the substrate body 1 and the integrated circuit chip 2.

[0030] Furthermore, the elastic deformation capacity of the outer packaging module 3 is greater than the volume change of the variable coolant 4 before and after the phase change. The variable coolant 4 changes from a liquid state to a solid state, increasing in volume. Since the elastic deformation of the outer packaging module 3 is greater than the increase in volume of the variable coolant 4, the increased volume of the variable coolant 4 will not damage the outer packaging module 3. As a specific implementation of this embodiment, the variable coolant 4 fills the entire interior of the outer packaging module 3, encapsulating the substrate body 1 and the integrated circuit chip 2. At higher temperatures, the variable coolant 4 is in a liquid state, facilitating convection heat dissipation and improving heat dissipation efficiency. When the ambient temperature is too low... The variable coolant 4 becomes solid, which is beneficial for heat preservation. By filling the entire interior of the outer packaging module 3 with the variable coolant 4, the high-temperature and low-temperature resistance of the substrate body 1 and the integrated circuit chip 2 inside the module is enhanced. In traditional PCB boards, sufficient gaps need to be left between chips to ensure heat dissipation. In this application, the variable coolant 4 directly wraps the integrated circuit chip 2, resulting in better heat dissipation. Therefore, the distance between integrated circuit chips 2 can be set smaller than the distance between chips on traditional PCB boards, thereby further reducing the size of the chip-to-chip packaging module system of this application.

[0031] Specifically, the outer packaging module 3 is equipped with multiple external interfaces 5; the external interfaces 5 are electrically connected to the integrated circuit chip 2; as a specific implementation of this embodiment, the multiple external interfaces 5 include various types of interfaces, and each external interface 5 can connect to different external devices.

[0032] It should be noted that, for those skilled in the art, it is obvious that this utility model is not limited to the details of the above exemplary embodiments, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this utility model. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this utility model is defined by the appended claims rather than the foregoing description. Therefore, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this utility model, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0033] Specific examples are used in this utility model to illustrate its principles and implementation methods. The above description of the embodiments is only for the purpose of helping to understand the method and core idea of ​​this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the idea of ​​this utility model. In summary, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A chip-to-chip direct packaging module system, characterized in that, It includes an outer packaging module, a substrate body, and an integrated circuit chip; at least one layer of the substrate body is sealed inside the outer packaging module; the integrated circuit chip is soldered onto the circuit of the substrate body; the outer packaging module is filled with a non-conductive variable coolant, and the variable coolant surrounds the outer periphery of the substrate body and the integrated circuit chip.

2. The wafer-to-chip direct packaging module system according to claim 1, characterized in that, The circuitry on the substrate is printed using nanoprinting.

3. The wafer-to-chip direct packaging module system according to claim 1, characterized in that, Multiple integrated circuit chips are soldered onto the circuitry of the substrate body.

4. The wafer-to-chip direct packaging module system according to claim 1, characterized in that, The substrate body can be made of high-quality thin glass.

5. The wafer-to-chip direct packaging module system according to claim 1, characterized in that, The substrate body has multiple layers; each integrated circuit chip is electrically connected to the others.

6. The wafer-to-chip direct packaging module system according to claim 1, characterized in that, A gap is provided between the substrate body and the outer packaging module.

7. The wafer-to-chip direct packaging module system according to claim 1, characterized in that, The outer packaging module is equipped with multiple external interfaces; the external interfaces are electrically connected to the integrated circuit chip.

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