Capacitor structure

Abstract

A capacitor structure includes a bottom electrode, a top electrode, and a multilayer stack disposed between the bottom electrode and the top electrode. The multilayer stack has a capacitance value switchable between at least two capacitance states. The multilayer stack includes a ferroelectric layer over the bottom electrode, and an oxide compound layer over the ferroelectric layer.

Description

Technical Field

[0001] This disclosure relates to a capacitor structure for use in neural network circuits. Background Technology

[0002] Artificial neural networks (ANNs) are one of the main tools used in machine learning, inspired by the animal brain. A neural network consists of input and output layers. In a typical ANN implementation, the signals at the connections between artificial neurons are real numbers, and the output of each artificial neuron is calculated using some nonlinear function of the sum of its inputs. The connections between artificial neurons are called "synapses." Artificial neurons and synapses typically have "weights" that adjust as learning progresses. Increasing or decreasing weights indicates an increase or decrease in signal strength at the connection between two neurons. Artificial neurons may have threshold values, causing them to send a signal only when the aggregated signal exceeds the threshold. Typically, artificial neurons are aggregated into layers. Different layers can perform different kinds of transformations on their inputs. A signal may travel from the first layer (input layer) to the last layer (output layer) after traversing several layers. Utility Model Content

[0003] In some embodiments, the capacitor structure includes a bottom electrode, a top electrode, and a multilayer stack disposed between the bottom electrode and the top electrode. The multilayer stack has a capacitance value that can be switched between at least two capacitance states. The multilayer stack includes a ferroelectric layer disposed between the bottom electrode and the top electrode, and an oxide compound layer above the ferroelectric layer.

[0004] In some embodiments, the capacitor structure includes a bottom electrode, a multilayer stack above the bottom electrode, and a top electrode above the multilayer stack. The multilayer stack includes a ferroelectric layer between the bottom electrode and the top electrode, and a high-k dielectric layer above the ferroelectric layer.

[0005] In some embodiments, the capacitor structure includes a bottom electrode located on an intermetallic dielectric layer and overlapping a bottom electrode via structure in the intermetallic dielectric layer; a multilayer stack overlapping the bottom electrode, the multilayer stack including a ferroelectric layer contacting the bottom electrode, a high-k dielectric layer contacting the ferroelectric layer, and an oxide semiconductor layer contacting the high-k dielectric layer; a top electrode overlapping the multilayer stack; and sidewall spacers located on opposite sidewalls of the top electrode and contacting the oxide semiconductor layer. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 It is a block diagram of a neural network according to some embodiments;

[0008] Figure 2 It is a circuit diagram of a neural network according to some embodiments;

[0009] Figure 3 A schematic perspective view illustrating an example of a weight matrix of a neural network according to some embodiments of the present disclosure;

[0010] Figure 4 A cross-sectional view of an example capacitive synaptic unit of a neural network according to some embodiments of the present disclosure is shown.

[0011] Figure 5A and Figure 5B This is a graph illustrating the capacitance-voltage (CV) simulation results of ferroelectric capacitors (FeCAP) with different material compositions according to some embodiments of this disclosure;

[0012] Figure 6 This is a graph illustrating durability tests performed on FeCAPs with different material compositions according to some embodiments of this disclosure;

[0013] Figures 7 to 15 A cross-sectional view illustrating an intermediate stage in the formation of an example integrated circuit (IC) structure having capacitive synaptic units (e.g., FeCAP) according to some embodiments of this disclosure is shown.

[0014] Figure 16 This is a cross-sectional view of an integrated circuit structure according to some embodiments of the present disclosure.

[0015] [Symbol Explanation]

[0016] 50A: First interconnect layer

[0017] 50B: Second Interconnect Layer

[0018] 53A~53B: Conductive vias

[0019] 54A~54B: Conductive wires

[0020] 55A: IMD layer

[0021] 55B: Insulating Film IMD

[0022] 60A~60B: Contains transistor interconnect layers

[0023] 100: Neural Networks

[0024] 110: Input neuron layer

[0025] 120: Hidden Neuron Layer

[0026] 130: Output neuron layer

[0027] 200: Neural Networks

[0028] 210: Preneuron layer

[0029] 220: Postneuronal layer

[0030] 250: Weight Matrix

[0031] 400: FeCAP structure

[0032] 410: Bottom electrode

[0033] 410': Bottom electrode layer

[0034] 420: Ferroelectric layer

[0035] 420': Ferroelectric layer

[0036] 430: High-k dielectric layer

[0037] 430': High-k dielectric layer

[0038] 440: Oxide semiconductor layer

[0039] 440': Oxide semiconductor layer

[0040] 450: Top electrode

[0041] 450': Top electrode layer

[0042] 460: Capacitors can be switched to multi-layer stacking

[0043] 500: Semiconductor Structure

[0044] 501: District

[0045] 502: Semiconductor substrate

[0046] 504: Transistor

[0047] 506: Fins

[0048] 508: Source and Drain Regions

[0049] 510: STI Zone

[0050] 512: HKMG gate structure

[0051] 514: Spacers

[0052] 516: First ILD

[0053] 518: Gate dielectric layer

[0054] 520: Conductive gate layer

[0055] 522: Second ILD layer

[0056] 524: Contact

[0057] 530: IMD layer

[0058] 540: BEVA structure

[0059] 542: Barrier Layer

[0060] 544: Filled metal structure

[0061] 550: Patterned hard mask layer

[0062] 550': Hard mask layer

[0063] 560: Spacing layer

[0064] 560': Spacing layer

[0065] 570: IMD layer

[0066] 582: TEVA structure

[0067] 584: Conductive wire

[0068] 600: Interlayer dielectric layer

[0069] 602: Rear gate structure

[0070] 604: Gate dielectric layer

[0071] 606: Semiconductor layer

[0072] 608: Source / Drain Metal Electrode

[0073] 610: BEOL transistor

[0074] 622: Through hole

[0075] 624: Conductive wire

[0076] 626: Through hole

[0077] 628: Dielectric layer

[0078] C1~C8: Curves

[0079] H1~H N Neuron

[0080] MW1~MW6: Memory Windows

[0081] O1: Through hole opening

[0082] PR: Patterned photoresist layer

[0083] SC: Capacitive Synapse Unit

[0084] S 11 ~S MN Capacitive synapse unit

[0085] X1~X M Neuron Detailed Implementation

[0086] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0087] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature depicted in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 230 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly. As used herein, “approximately,” “about,” “roughly,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The numbers given herein are approximate, thus meaning that the terms “approximately,” “about,” “roughly,” or “substantially” can be inferred unless explicitly stated. However, those skilled in the art will recognize that the values ​​or ranges mentioned throughout the specification are merely examples and may decrease or change as the scale of integrated circuits shrinks.

[0088] The embodiments disclosed herein are applicable to compute-in-memory, processing-in-memory, processing-using-memory, near-memory-compute, near-data processing, near-memory processing, in-storage processing, GPU accelerators, TPU accelerators, in-memory computing, in-memory-processing, compute near memory, and / or processing near memory.

[0089] In the field of compute-in-memory (CIM) technology, algorithms such as deep learning employ vector-matrix multiplication. These algorithms often utilize the concept of "resistive weighting" in analog memory systems using non-volatile memory devices. Traditional designs, such as 1T-1R (one transistor-one resistor) configurations, are being re-evaluated to adopt architectures like ferroelectric capacitor (FeCAP) crossover arrays. FeCAP stands out due to its numerous advantages, including significantly improved power efficiency, fast operation (in the nanosecond range), compact area, high data retention, and low-voltage operation.

[0090] By selecting different metal materials for the top and bottom electrodes of the FeCAP, the capacitance-voltage (CV) curve can be adjusted. This adjustment results in a shift relative to 0V and opens a window of non-zero capacitance at DC 0V. Despite these improvements, the FeCAP's memory window (MW) is limited, typically in the range of 5 to 6, which can affect its retention performance. This is particularly evident in applications that require long-term data storage and retrieval without degradation, such as applications involving lifelong or continuous machine learning (ML).

[0091] To address this issue, embodiments disclosed herein provide an improved material design for ferroelectric capacitors (FeCAPs) that significantly increases the memory window (MW) to, for example, greater than 10. The improved FeCAP material design includes a multilayer stack between the FeCAP top electrode and the FeCAP bottom electrode, wherein the multilayer stack includes one or more of an oxide semiconductor layer (i.e., an oxide compound layer), a high-k dielectric layer, and a ferroelectric layer having a crystal structure with tetragonal and orthorhombic phases. By achieving a MW greater than 10, this design offers the possibility of achieving superior retention performance compared to the typical range of 5 to 6. This improvement in the memory window is a significant advancement because it directly impacts the lifetime and reliability of memory elements in machine learning and other data-intensive applications. This development has significant potential for improving the efficiency and effectiveness of memory devices in the ML field and more broadly. Furthermore, these materials can be formed in a cryogenic deposition process that can be integrated into back-end-of-line (BEOL) processing for embedded memory applications.

[0092] Figure 1 This is a schematic diagram of a neural network 100 according to some embodiments. The neural network 100 includes an input neuron layer 110, one or more hidden neuron layers 120, and an output neuron layer 130. The input neuron layer 110 includes multiple neurons X1 to X2. I The hidden neuron layer 120 includes multiple neurons H1 to H2. J The output neuron layer 130 includes multiple neurons O1 to O2. K These neurons, also known as electronic neurons, can be implemented using digital logic circuits composed of transistors. These circuits perform arithmetic operations, such as multiplication for weighted inputs and addition for summing weighted inputs. In some embodiments, two adjacent neuron layers are referred to as a pre-neuron layer and a post-neuron layer along the forward propagation direction. Each neuron in these layers is connected via synapses to multiple neurons in the next layer. For example, neuron X1 in input neuron layer 110 is connected via individual synaptic units (i.e., Figure 1 The straight lines shown connect to neurons H1 to H2. J In each of these, neuron X2 in the input neuron layer 110 is also connected to neurons H1 to H2 via individual synaptic units. J Each of them, and the remaining neurons X in neuron layer 110. I Each of them is also connected to neurons H1-H through individual synaptic units. JAll of the above. Synaptic units serve as connections linking neurons in the preneuron layer to neurons in the postneuron layer. In some embodiments, a synaptic unit is a FeCAP with programmable capacitance states or values.

[0093] In some embodiments, the input neuron layer 110 and the hidden neuron layer 120 are two adjacent neuron layers, and input data is input from the input neuron layer 110 to the hidden neuron layer 120. The input data is converted into binary numbers or other suitable number types. Subsequently, the binary numbers are input to neurons X1 to X2 in the input neuron layer 110. I In the middle. Each neuron in the input neuron layer 110 and each neuron in the hidden neuron layer 120 are connected by using individual neurons with synaptic weights W. i,j Various synaptic units are used for connection. For example, neuron X1 in input neuron layer 110 and neuron H1 in hidden neuron layer 120 are connected by synaptic weights W. 1,1 They connect via synaptic units. Neurons H1 to H2 in hidden neuron layer 120 J Each component receives each input data point along with its weight W. i,j The product of , and in some embodiments, this product is called the weighted sum.

[0094] In various embodiments, the hidden neuron layer 120 and the output neuron layer 130 are two adjacent neuron layers, with input data flowing from the hidden neuron layer 120 to the output neuron layer 130. Each neuron in the hidden neuron layer 120 and each neuron in the output neuron layer 130 are connected by using respective neurons with weights W. j,k Various synaptic units are used to connect them. For example, neuron H2 in hidden neuron layer 120 and neuron O2 in output neuron layer 130 use a weight W between neuron H2 and neuron O2. 2,2 They connect via synaptic units. Neurons H1 to H2 from hidden neuron layer 120 J The weights of each neuron in the output neuron layer 130 are used as inputs to the output neuron layer 130. Neurons O1 to O2 in the output neuron layer 130... K Each of the components receives each weight and its corresponding weight W. j,k The product of.

[0095] like Figure 1 As shown, neurons O1 to O2 of the output neuron layer 130 are... K The weights of the outputs of each neuron are considered as the output of neural network 100. The weights from neurons O1 to O2 are then considered as the output of neural network 100. K The outputs are respectively related to the target values ​​T1 to T K Compare them. If they originate from neurons O1 to O2... K One of the outputs differs from the target value T1~TK If the corresponding target value is obtained, the weight W between the input neuron layer 110 and the hidden neuron layer 120 will be adjusted. i,j and the weights W between the hidden neuron layer 120 and the output neuron layer 130 j,k This continues until the output matches the corresponding target value. In some embodiments, the target value is set as a predetermined value corresponding to the input data, allowing the weights between two adjacent neurons to be repeatedly trained to optimize the weight values.

[0096] Figure 2 This is a circuit diagram of a neural network 200 according to some embodiments. In some embodiments, such as Figure 2 The circuit diagram of the neural network 200 can be used to implement, for example... Figure 1 An exemplary circuit of the neural network 100 is described. The neural network 200 may include a pre-neuron layer 210 and a post-neuron layer 220, the post-neuron layer following the pre-neuron layer 210 and connected to the pre-neuron layer 210 using a weight matrix 250. The pre-neuron layer 210 may be similar to... Figure 1 The input neuron layer 110 and the post-neuron layer 220 may be similar to... Figure 1 The hidden neuron layer 120 shown is a hidden neuron layer. In some embodiments, the preneuron layer 210 includes a plurality of neurons X1, X2, ..., and X... M The postneuron layer 220 includes multiple neurons H1, H2, ..., and H... N In some embodiments, the number of neurons "M" in the preneuron layer 210 is equal to the number of neurons "N" in the postneuron layer 220. In some embodiments, the number of neurons "M" in the preneuron layer 210 is less than the number of neurons "N" in the postneuron layer 220. In some embodiments, the number of neurons "M" in the preneuron layer 210 is greater than the number of neurons "N" in the postneuron layer 220.

[0097] The weight matrix 250 includes a plurality of capacitive synaptic units (e.g., FeCAP) arranged in an array of rows and columns, a plurality of word lines coupled to first terminals in the capacitive synaptic units, and a plurality of bit lines coupled to second terminals in the capacitive synaptic units. For example, the neural network 200 has preneuron layers 210 with bits coupled to m word lines (i.e., WL1, WL2, ..., WL...). M m neurons (i.e., X1, X2, ..., X...) M In the postneuron layer 220, there are n bit lines respectively coupled to n bits (i.e., BL1, BL2, ..., BL...). N n neurons (i.e., H1, H2, ..., Hn) N), and therefore the weight matrix 250 includes m*n capacitive synaptic units (i.e., S 11 S 12 ... S 1N S 21 S 22 ... S 2N ... S M1 S M2 ... and S MN These are arranged in an array of m rows and n columns. The synaptic units are capacitors, not resistors. Capacitive synaptic units utilize a programmable capacitor state (at DC zero bias) as synaptic weights. The quiescent power of capacitive synaptic units is negligible because the capacitors only consume dynamic power. Furthermore, the open-circuit nature of the capacitors effectively blocks unwanted sneak-path currents. It should be noted that the access transistor in a one-transistor-one-resistor (1T1R) synaptic unit is primarily used to resist sneak-path currents. Because capacitive synaptic units have no or negligible sneak-path currents, they may not have access transistors, allowing each synaptic unit's capacitor to have one terminal directly coupled to the word line and one terminal directly coupled to the bit line.

[0098] An example of the operation of neural network 200 includes two steps. In the first step, the input WL voltages (i.e., IN[1], IN[2], ..., IN[M]) are passed through individual WL multiplexers (in... Figure 2 (represented by "MUX") propagates and affects each corresponding ferroelectric capacitor (C). FECAP An array of capacitive synaptic cells, preprogrammed as distinct capacitors to represent values ​​in a weighting matrix, is charged. The product of an input WL voltage value and a weighted capacitor value is encoded as the charge on each capacitive synaptic cell. Next, in a second step, the input voltage is returned to a common voltage (V). C ), and become neurons in the postneuronal layer 220 (i.e., H1, H2, ..., and H...). N The negative inputs of the operational amplifiers (OPAMPs) in the synaptic layer are essentially the same. Therefore, the voltage drop across each capacitive synaptic unit becomes essentially 0V, thereby forcing charge to transfer along the corresponding bit lines to the neurons in the postneuron layer 220 (i.e., H1, H2, ..., H...). N The reference capacitor C in ) ref Above. Reference capacitor C ref The number of charges on the line is the weighted sum along the bit lines, and the resulting output voltage (V) out) are used as the corresponding neurons in the postneuron layer 220 (i.e., H1, H2, ..., and H... N ) input.

[0099] Figure 3 A schematic perspective view illustrating an example of a weight matrix 250 according to some embodiments of this disclosure is provided. Figure 3 In this configuration, the weight matrix 250 is arranged in a cross-switch array, including word lines extending in a first direction (e.g., WL1, WL2, and WL3), bit lines extending in a second direction perpendicular to the first direction (e.g., BL1, BL2, and BL3), and capacitive synaptic units (e.g., S...). 11 S 12 S 13 S 21 S 22 S 23 S 31 S 32 and S 33 Each capacitive synapse unit has a first terminal (e.g., bottom electrode) coupled to a corresponding one in a word line and a second terminal (e.g., top electrode) coupled to a corresponding one in a bit line.

[0100] In some embodiments, the capacitive synaptic unit (i.e., S) 11 S 12 ... S 1N S 21 S 22 ... S 2N ... S M1 S M2 ... and S MN A ferroelectric capacitor (FeCAP) is a ferroelectric capacitor. Each ferroelectric capacitor has its programmable capacitance state or value to be used as a synaptic weight. In a neural network 200 where synaptic weights are represented by ferroelectric capacitors, the capacitance state of each ferroelectric capacitor corresponds to the strength of the synaptic connection. Ferroelectric materials exhibit hysteresis properties, meaning that their polarization state (and therefore capacitance) can be maintained without continuous power, which in turn allows these synaptic units to store synaptic weights in a non-volatile memory manner. During the training of the neural network 100 / 200, the synaptic weight of each capacitive synaptic unit can be changed by reprogramming the capacitance state of the corresponding ferroelectric capacitor by applying appropriate voltage pulses to the ferroelectric capacitor.

[0101] Figure 4 A cross-sectional view of an example capacitive synaptic unit SC according to some embodiments of this disclosure is shown. Figure 4In this design, the capacitive synaptic unit SC is a ferroelectric capacitor (FeCAP), comprising a bottom electrode 410 (labeled "BE"), a ferroelectric layer 420 (labeled "FE") above the bottom electrode 410, a high-k dielectric layer 430 (labeled "High-k") above the ferroelectric layer 420, an oxide semiconductor layer 440 (labeled "OS") above the high-k dielectric layer 430, and a top electrode 450 (labeled "TE") above the oxide semiconductor layer 440. The ferroelectric layer 420, the high-k dielectric layer 430, and the oxide semiconductor layer 440 are collectively referred to as a switchable multilayer stack 460. The switchable multilayer stack 460 has a capacitance value that can be switched between at least two capacitance states.

[0102] In some embodiments, the bottom electrode 410 may be made of gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), or indium tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide of these materials, such as TaN, TiN, TiAlN, TiW, combinations thereof, or the like.

[0103] In some embodiments, the ferroelectric layer 420 formed directly on the bottom electrode 410 has a crystal structure composed of a mixture of orthorhombic (O phase) and tetragonal (T phase) HfZrO (HZO). Due to the higher k-value (dielectric constant) of the tetragonal HZO, the use of a mixed orthorhombic / tetragonal HZO in the ferroelectric layer 420 enhances programmed capacitance. The ferroelectric layer 420 is carefully designed to utilize the different dielectric properties of the orthorhombic and tetragonal phases of HZO. The orthorhombic HZO contributes to the stability and durability of the layer, providing a solid foundation for its ferroelectric properties. In contrast, the addition of the tetragonal HZO significantly increases the dielectric constant of the ferroelectric layer 420, which directly translates into improved capacitance under programmed conditions. This mixed-phase composition not only optimizes ferroelectric performance but also customizes the electrical properties of the layer according to the requirements of specific applications (e.g., neural networks).

[0104] The ratio of orthorhombic to tetragonal HZO within the ferroelectric layer 420 is carefully optimized based on the desired balance between stability and capacitance enhancement. For example, a higher ratio of tetragonal HZO (e.g., a T-phase to O-phase ratio greater than 1) may be more suitable for programmed capacitance improvement. By adjusting the fabrication parameters of the ferroelectric layer 420, such as precursor composition, deposition temperature, and / or annealing conditions, the phase composition within the ferroelectric layer 420 can be precisely controlled. This allows for fine-tuning of the properties of the ferroelectric layer based on the specific requirements of the target application (e.g., neural network requirements) to achieve the optimal balance between stability and capacitance.

[0105] In some embodiments, the ferroelectric layer 420 is formed of a ferroelectric material with spontaneous polarization, which can be reversed by an electric field applied by the bottom electrode 410 and / or the top electrode 450. In some embodiments, the ferroelectric material of the ferroelectric layer 420 includes HfZrO, HfAlO, HfLaO, HfCeO, HfO, HfGdO, HfSiO, or the like, wherein orthorhombic (O-phase) crystals coexist with tetragonal (T-phase) crystals in these selected materials. In some embodiments, the ferroelectric layer 420 includes more T-phase crystals than O-phase crystals to promote improved programmed state capacitance. In some embodiments where the ferroelectric layer 420 is HfZrO, the atomic percentage of Zr is in the range of about 60% to 80%, which allows for the desired T-phase, compared to O, to be suitable for improving programmed state capacitance. In some embodiments, the ferroelectric layer 420 has a thickness ranging from about 2 nm to about 20 nm and is deposited over the bottom electrode 410 using any suitable method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or the like.

[0106] In some embodiments, a high-k dielectric layer 430 is situated between the ferroelectric layer 420 and the oxide semiconductor layer 440, serving as an interface layer between the ferroelectric layer 420 and the oxide semiconductor layer 440. The high-k dielectric layer 430 enhances program state capacitance due to its high k value. In some embodiments, the high-k dielectric layer 430 can significantly stabilize the interface region between the ferroelectric layer 420 and the oxide semiconductor layer 440, which improves the long-term reliability and data retention of the synaptic unit SC. Fluctuations in the interface region between the ferroelectric layer 420 and the oxide semiconductor layer 440 due to chemical reactions, interdiffusion, or stress can degrade the device performance of the synaptic unit over time. The high-k dielectric layer 430 acts as a barrier to mitigate these effects, maintaining the structural and electrical integrity of the interface region between the ferroelectric layer 420 and the oxide semiconductor layer 440.

[0107] In some embodiments, the high-k dielectric layer 430 has a thickness less than that of the ferroelectric layer 420 and the oxide semiconductor layer 440. If the high-k dielectric layer 430 is too thick (e.g., thicker than the ferroelectric layer 420 and the oxide semiconductor layer 440), the forward and / or reverse scanning of the synaptic unit SC may require excessive voltage, resulting in increased power consumption. In some embodiments, the thickness of the high-k dielectric layer 430 is in the range of about 0.1 nm to about 1 nm. In some embodiments, the thickness ratio of the ferroelectric layer 420 to the high-k dielectric layer 430 is in the range of about 2 to about 200.

[0108] In some embodiments, the high-k dielectric layer 430 is formed of a different material than the ferroelectric layer 420. For example, the high-k dielectric layer 430 includes Al2O3, HfO2, ZrO2, TiO2, NbO, La2O3, or the like. In some embodiments, the high-k dielectric layer 430 is deposited over the ferroelectric layer 420 using any suitable method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or the like.

[0109] In some embodiments, an oxide semiconductor layer 440 is disposed between the high-k dielectric layer 430 and the top electrode 450. The oxide semiconductor layer 440 allows for a reduction in the erase state capacitance of the synaptic unit SC during a forward scan. The unipolar carrier properties of the oxide semiconductor layer 440 contribute to this reduction, allowing for control over capacitance behavior during the forward scan. In other words, without the oxide semiconductor layer 440, the erase state capacitance of the synaptic unit SC might be undesirably high, which in turn would reduce the memory window of the synaptic unit.

[0110] In some embodiments, the oxide semiconductor layer 440 comprises a metal oxide, such as ZnO, InWO, InGaZnO, InZnO, ITO, or the like. In some embodiments, the oxide semiconductor layer 440 has a thickness in the range of about 2 nm to about 20 nm and is deposited over the high-k dielectric layer 430 using any suitable method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or the like.

[0111] In some embodiments, the top electrode 450 is disposed above the oxide semiconductor layer 440. In some embodiments, the top electrode 450 may be formed of a material such as gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), or indium tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide of these materials, such as TaN, TiN, TiAlN, TiW, combinations thereof, or the like. In some embodiments, the top electrode 450 is formed of a different material than the bottom electrode 410. By selecting different metal materials for the top electrode 450 and the bottom electrode 410, the capacitance-voltage (CV) curve of the synaptic unit SC can be further shifted, thereby further increasing the memory window of the synaptic unit SC.

[0112] Figure 5A and Figure 5B This is a graph showing the capacitance-voltage (CV) simulation results of FeCAPs with different material compositions between the top and bottom electrodes. Figure 5AThe capacitance-voltage (CV) characteristics of a FeCAP stack including a ferroelectric layer 420, a high-k dielectric layer 430, and an oxide semiconductor layer 440 between the top and bottom electrodes are plotted. Figure 5A In the middle, the dielectric constant ε r The (epsilon) value is displayed on the vertical axis, and the voltage applied to the FeCAP is displayed on the horizontal axis. Curve C1 represents the CV characteristic produced by a forward scan from a determined negative voltage to a determined positive voltage. Curve C2 represents the CV characteristic produced by a reverse scan (also known as a backward scan) from a determined positive voltage to a determined negative voltage. A forward scan is associated with an "erase" or "reset" operation performed on a FeCAP memory device. This is because the applied voltage redirects the polarization of the ferroelectric material in the FeCAP, effectively resetting the FeCAP's state to the baseline or "erase" state. A reverse scan is associated with a "program" or "write" operation performed on a FeCAP memory device. By using a reverse scan, the ferroelectric material reverses or changes from its initial state to a specific polarization state, resulting in a different capacitance value compared to a forward scan.

[0113] Curves C1 and C2 exhibit asymmetric CV characteristics, showing a high capacitance state in the reverse scan curve C2 and a low capacitance state in the forward scan curve C1 at DC 0V. The dielectric constant (ε) here... r The ) indicates the capacitor state. FeCAP's memory window MW1 refers to the dielectric constant ε in the reverse scan curve C2 (i.e., the program state). + The difference between the dielectric constant ε- in the forward scan curve C1 (i.e., the erase state) and that in the reverse scan curve C2. In the simulation results, the memory window MW1 is greater than 10. For example, the dielectric constant ε- in the reverse scan curve C2... + The dielectric constant ε- in the forward scan curve C1 is in the range of approximately 31 to 34, while it is in the range of approximately 19 to 20.

[0114] Figure 5B The capacitance-voltage (CV) characteristics of a reference FeCAP, which includes a ferroelectric layer but lacks a high-k dielectric layer 430 and an oxide semiconductor layer, are plotted between the top and bottom electrodes. Figure 5B In the middle, the dielectric constant ε rThe voltage (epsilon) is displayed on the vertical axis, and the voltage applied to the reference FeCAP is displayed on the horizontal axis. Curve C3 represents the CV characteristic produced by a forward scan from the determined negative voltage to the determined positive voltage. Curve C4 represents the CV characteristic produced by a reverse scan (or backward scan) from the determined positive voltage to the determined negative voltage. Curves C3 and C4 show asymmetrical CV characteristics, exhibiting a high capacitance state in the reverse scan curve C4 and a low capacitance state in the forward scan curve C3 at DC 0V. The dielectric constant (ε) here... r The ) indicates the capacitor state. Referring to FeCAP, the memory window MW2 refers to the dielectric constant ε in the reverse scan curve C4. + The difference between the dielectric constant ε- and that in the forward scan curve C3. In the simulation results, the memory window MW2 is in the range of 5 to 6, which is about 40% to 50% smaller than the memory window MW1. Figure 5A and Figure 5B The simulation results indicate that the memory window can be significantly improved by stacking a ferroelectric layer 420, a high-k dielectric layer 430, and an oxide semiconductor layer 440 between the top and bottom electrodes.

[0115] Figure 6 This is a graph illustrating durability tests conducted on FeCAPs with different material compositions between the top and bottom electrodes. The graph plots the dielectric constant ε on the vertical axis. r (epsilon) represents the measurement cycle count relative to the horizontal axis, thus revealing the durability of different FeCAP structures under repeated use. Curves C5 and C6 depict the program-state dielectric constant ε of a FeCAP configured with a layered stack including a ferroelectric layer 420, a high-k dielectric layer 430, and an oxide semiconductor layer (440), respectively. + The changes in the dielectric constant ε- in the erase state are also shown. Curves C5 and C6 plot the evolution of the memory window from the initial memory window MW3 to the final memory window MW4 after 300 measurement cycles. Curves C7 and C8 represent the changes in the program-state dielectric constant and the erase-state dielectric constant of the reference FeCAP lacking the high-k dielectric layer 430 and the oxide semiconductor layer 440. Similarly, curves C7 and C8 track the progress of the memory window from the initial memory window MW5 to the final memory window MW6 after 300 measurement cycles.

[0116] Comparative analysis shows that, compared to the reference FeCAP, the modified FeCAP, with its ferroelectric layer, high-k dielectric layer, and oxide semiconductor layer, exhibits superior durability and data retention. This is reflected in the smaller difference between the initial memory window MW3 and the final memory window MW4 in the modified FeCAP compared to the difference between the initial memory window MW5 and the final memory window MW6 in the reference FeCAP. Furthermore, the final memory window MW4 of the modified FeCAP still exceeds the value by 10, surpassing the initial memory window MW5 of the reference FeCAP.

[0117] Figures 7 to 15 A cross-sectional view illustrating an intermediate stage in the formation of an example integrated circuit (IC) structure 500 having capacitive synaptic units (e.g., FeCAP) according to some embodiments of this disclosure is shown. Although Figures 7 to 15 The cross-sectional view shown is described with reference to one method, but it should be understood that... Figures 7 to 15 The structure shown is not limited to this method, but can exist independently of it. Although Figures 7 to 15 The description is a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed method is also applicable to other structures.

[0118] Figure 7 The illustration shows a cross-sectional view of an example semiconductor structure 500 including a semiconductor substrate 502 according to some embodiments, in which various electronic devices can be formed, and a portion of a multi-level interconnect structure (e.g., layers 50A and 50B) can be formed above the substrate 502. Generally, Figure 7 A transistor 504 is illustrated on a substrate 502, with multiple interconnect layers formed on top of it. (Example:) Figure 7 As omitted at the top, multiple interconnect layers can be similarly stacked in the manufacturing process of integrated circuits. As shown, transistor 504 is a FinFET. In some other embodiments, transistor 504 is a planar FET, nanosheet FET, or other suitable FET. One or more transistors 504 can be used in logic circuits, static random access memory (SRAM) circuits, peripheral circuits, I / O circuits, and / or analog circuits.

[0119] Figure 7The substrate 502 shown may comprise a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer, which is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or alloys of these materials (e.g., Ga...). x Al 1-x As, Ga x Al 1-x N、In x Ga 1-x As, and the like), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and the like), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0120] Figure 7 The FinFET device 504 shown is a three-dimensional MOSFET structure formed in fin-shaped strips of semiconductor protrusions 506 called fins. Figure 7 The cross-section shown is taken along the longitudinal axis of the fin in a direction parallel to the current flow direction between the source and drain regions 508. The fin 506 can be formed by patterning the substrate using optical lithography and etching techniques. For example, spacer image transfer (SIT) patterning techniques can be used. In this method, a sacrificial layer is formed over the substrate and patterned using suitable optical lithography and etching processes to form a mandrel. Spacers are formed next to the mandrel using a self-aligned process. The sacrificial layer is then removed using a suitable selective etching process. Each remaining spacer can then be used as a hard mask to pattern individual fins 506 by etching trenches into the substrate 502 using, for example, reactive ion etching (RIE). Figure 7 A single fin 506 is shown, although the substrate 502 may contain any number of fins.

[0121] Figure 7The diagram illustrates a shallow trench isolation (STI) region 510 formed along the opposing sidewalls of fin 506. The STI region 510 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trenches around the fin, followed by recessing the top surface of the dielectric material. The dielectric material of the STI region 510 can be deposited using high-density plasma chemical vapor deposition (HDP-CVD), low-pressure CVD (LPCVD), sub-atmospheric CVD (SACVD), flowable CVD (FCVD), spin coating, and / or similar methods, or combinations thereof. After deposition, an annealing or curing process can be performed. In some cases, the STI region 510 may include a liner, such as, for example, a thermal oxide liner grown through a silicon oxide surface. The recessing process can use, for example, a planarization process (e.g., chemical mechanical polishing (CMP)), followed by a selective etching process (e.g., wet etching, dry etching, or a combination thereof). The selective etching process recesses the top surface of the dielectric material in the STI region 510, causing the upper portion of the fin 506 to protrude from the surrounding insulating STI region 510. In some cases, the patterned hard mask used to form the fin 506 can also be removed by the planarization process.

[0122] In some embodiments, Figure 6 The gate structure 512 of the FinFET device 504 shown is a high-k metal gate (HKMG) gate structure, which can be formed using a post-gate process. In the post-gate process, after forming the STI region 510, a sacrificial dummy gate structure (not shown) is formed. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, or the like) may be deposited. Next, a dummy gate material (e.g., amorphous silicon, polysilicon, or the like) may be deposited over the dummy gate dielectric, followed by planarization (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, or the like) may be formed over the dummy gate material. Then, the dummy gate structure is formed by patterning the hard mask and transferring the pattern to the dummy gate dielectric and dummy gate material using suitable optical lithography and etching techniques. The dummy gate structure may extend along multiple sides of the protruding fins and extend between the fins above the surface of the STI region 510. As described in more detail below, the dummy gate structure may be replaced by the HKMG gate structure 512, such as... Figure 6 As shown in the figure. The materials used to form the dummy gate structure and hard mask can be deposited using any suitable method such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or the like, or by thermal oxidation of the semiconductor surface, or a combination of these methods.

[0123] like Figure 7 As shown, the source and drain regions 508 of the FinFET 504 and the spacer 514 are formed, for example, in a self-aligned manner with the dummy gate structure. The spacer 514 can be formed by deposition and anisotropic etching of a spacer dielectric layer performed after the dummy gate patterning is completed. The spacer dielectric layer may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof. The anisotropic etching process removes the spacer dielectric layer from above the top of the dummy gate structure, leaving the spacer 514 along the sidewalls of the dummy gate structure.

[0124] The source and drain regions (also collectively referred to as source / drain regions or S / D regions) 508 are semiconductor regions in direct contact with the semiconductor fin 506. In some embodiments, the source and drain regions 508 may include heavily doped regions and relatively lightly doped drain extensions, or LDD regions. Generally, spacers 514 are used to space the heavily doped regions from the dummy gate structure, and the LDD regions may be formed prior to the formation of spacers 514, thus extending below spacers 514, and in some embodiments, further extending into a portion of the semiconductor fin 506 below the dummy gate structure. For example, the LDD regions may be formed by implanting dopants (e.g., As, P, B, In, or the like) using an ion implantation process.

[0125] In some embodiments, the source and drain regions 508 may include epitaxial growth regions. For example, after forming the LDD regions, spacers 514 may be formed, and then, by first etching the fins 506 to form grooves, and then depositing crystalline semiconductor material in the grooves using a selective epitaxial growth (SEG) process (this can fill the grooves and extend beyond the initial surface of the fins to form a structure such as...). Figure 7 The convex source-drain structure shown is used to self-align with spacer 514 to form heavily doped source and drain regions. The crystalline semiconductor material can be an element (e.g., Si, or Ge, or the like) or an alloy (e.g., Si...). 1-x C x , or Si 1-x Gex Materials (or similar). The SEG process can use any suitable epitaxial growth method, such as vapor / solid / liquid phase epitaxy (VPE, SPE, LPE), metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), or similar. High doses (e.g., approximately 10...) 15 cm -2 Up to 10 20 cm -2 The dopant can be introduced in situ into the heavily doped source and drain regions 508 during SEG, or through an ion implantation process performed after SEG, or through a combination thereof.

[0126] A first interlayer dielectric (ILD) 516 is deposited over this structure. In some embodiments, a contact etch stop layer (CESL) (not shown) suitable for the dielectric (e.g., silicon nitride, silicon carbide, or the like, or combinations thereof) may be deposited prior to depositing the ILD material. A planarization process (e.g., CMP) may be performed to remove excess ILD material and any remaining hard masking material from above the dummy gate to form a top surface in which the top surface of the dummy gate material is exposed and substantially coplanar with the top surface of the first ILD 516. Then, a structure such as Figure 7 The HKMG gate structure 512 shown is formed by first removing a dummy gate structure using one or more etching techniques to create trenches between individual spacers 514. Next, a replacement gate dielectric layer 518 comprising one or more dielectric materials is deposited, followed by a replacement conductive gate layer 520 comprising one or more conductive materials to completely fill the trenches. Excess portions of the gate structure layers 518 and 520 can be removed from the top surface of the first ILD 516 using, for example, a CMP process. The resulting structure is as follows: Figure 7 As shown, the surfaces are substantially coplanar, including the exposed top surface of the first ILD 516, spacers 514, and the remaining portions of the HKMG gate layers 518 and 520 embedded between the individual spacers 514.

[0127] The gate dielectric layer 518 comprises, for example, a high-k dielectric material, such as oxides and / or silicates of metals (e.g., oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), silicon nitride, silicon oxide, and the like, or combinations thereof, or multiples thereof. In some embodiments, the conductive gate layer 520 may be a multilayer metal gate stack comprising a barrier layer, a work function layer, and a gate fill layer continuously formed on top of the gate dielectric layer 518. Examples of materials for the barrier layer include TiN, TaN, Ti, Ta, or the like, or multiple combinations thereof. The work function layer may include TiN, TaN, Ru, Mo, Al for p-type FETs, and Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr for n-type FETs. Other suitable work function materials, or combinations thereof, or multiples thereof may be used. The gate fill layer for the remaining portion of the filling trench may comprise metals such as Cu, Al, W, Co, Ru, or the like, or combinations thereof, or multiples thereof. The material used to form the gate structure can be deposited by any suitable method, such as CVD, PECVD, physical vapor deposition (PVD), ALD, PEALD, electrochemical plating (ECP), electroless plating, and / or the like.

[0128] The second ILD layer 522 can be deposited above the first ILD layer 516, such as Figure 7 As shown in the figure. In some embodiments, the insulating material forming the first ILD layer 516 and the second ILD layer 522 may comprise silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), silicon-free glass (USG), low dielectric constant (low k) dielectrics (such as fluorosilicone glass (FSG), silicon carbide (SiOCH), carbon-doped oxide (CDO), flowable oxides, or porous oxides (e.g., dry gel / aerogel)), or the like, or combinations thereof. The dielectric material used to form the first ILD layer 516 and the second ILD layer 522 may be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, and / or the like, or combinations thereof.

[0129] like Figure 7 As shown, electrodes of an electronic device formed in substrate 502 can be electrically connected to conductive features in the first interconnect layer 50A using conductive connectors (e.g., contact 524) formed through an intermediate dielectric layer. Figure 7In the illustrated embodiment, contact 524 is electrically connected to the source and drain regions 508 of the FinFET 504. Contact 524, connected to the gate electrode, may be formed above the STI region 510, and therefore is not... Figure 7 The cross-sectional view shows that the contacts can be formed using optical lithography. For example, a patterned mask can be formed above the second ILD 522 and used to extend through the etched opening of the second ILD 522 to expose a portion of the gate structure 512, and further extend through the first ILD 516 and the CESL (if present) liner etched opening below the first ILD 516 to expose portions of the source and drain regions 508.

[0130] In some embodiments, a conductive liner may be formed in openings in the first ILD layer 516 and the second ILD layer 522. The openings are then filled with a conductive filler material. The liner includes a barrier metal to reduce the diffusion of conductive material from the contact 524 outwards into the surrounding dielectric material. In some embodiments, the liner may include two barrier metal layers. The first barrier metal contacts the semiconductor material in the source and drain regions 508 and may subsequently chemically react with the heavily doped semiconductor in the source and drain regions 508 to form a low-resistance ohmic contact, after which unreacted metal may be removed. For example, if the heavily doped semiconductor in the source and drain regions 508 is silicon or a silicon-germanium alloy semiconductor, the first barrier metal may comprise Ti, Ni, Pt, Co, other suitable metals, or alloys thereof. The second barrier metal layer of the conductive liner may additionally comprise other metals (e.g., TiN, TaN, Ta, or other suitable metals, or alloys thereof). Conductive filler material (e.g., W, Al, Cu, Ru, Ni, Co, alloys thereof, compositions thereof, and the like) can be deposited over the conductive liner layer to fill the contact openings using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, or similar, or any combination thereof). Next, a planarization process (e.g., CMP) can be used to remove all excess conductive material from the surface of the second ILD 522. The resulting conductive socket extends into the first ILD layer 516 and the second ILD layer 522 and forms contacts 524, thereby forming a physical and electrical connection with the electrodes of an electronic device, such as... Figure 7 The three-gate FinFET 504 shown is illustrated.

[0131] like Figure 7 As shown, according to the back-end-of-line (BEOL) scheme adopted in integrated circuit design, multiple interconnect layers can be formed and vertically stacked on the contact sockets 524 formed in the first ILD layer 516 and the second ILD layer 522. Figure 7In the BEOL scheme shown, the various interconnect layers have similar characteristics. However, it should be understood that other embodiments may utilize alternative integration schemes in which the various interconnect layers may use different characteristics. For example, the contact 524, shown as a vertical connector, may extend to form conductive lines for lateral current transmission.

[0132] In this disclosure, the second interconnect layer includes conductive vias and conductive lines embedded in an inter-metal dielectric (IMD) layer. In addition to providing insulation between various conductive elements, the IMD layer may include one or more dielectric etch-stop layers to control the etching process that forms openings in the IMD layer. Generally, conductive vias conduct current vertically and are used to electrically connect two conductive features located in vertically adjacent layers, while conductive lines conduct current laterally and are used to distribute electrical signals and power within a layer. Figure 7 In the BEOL configuration shown, conductive via 53A connects contact 524 to conductive wire 54A, and at subsequent levels, vias connect lower wirings to upper wirings (e.g., a pair of wires 54A and 54B can be connected via via 53B). Other embodiments may employ different configurations. For example, via 53A may be omitted from the first level, and contact 524 may be configured to connect directly to wire 54A.

[0133] The first interconnect layer 50A can be formed using, for example, a dual damascene process. First, a dielectric stack for forming the IMD layer 55A can be deposited using one or more layers of dielectric materials listed in the description of the first ILD layer 516 and the second ILD layer 522. In some embodiments, the IMD layer 55A includes an etch-stop layer (not shown) located at the bottom of the dielectric stack. The etch-stop layer comprises one or more insulating layers (e.g., SiN, SiC, SiCN, SiCO, CN, combinations thereof, or the like) having an etch rate different from that of the overlying material. The technique used to deposit the dielectric stack for the IMD can be the same as the technique used to form the first ILD layer 516 and the second ILD layer 522.

[0134] The IMD layer 55A can be patterned using appropriate optical lithography and etching techniques (e.g., anisotropic RIE using fluorocarbon chemicals) to form openings for vias and wiring. The openings for vias may be vertical holes extending through the IMD layer 55A to expose the top conductive surface of the contact 524, and the openings for wiring may be longitudinal trenches formed in the upper portion of the IMD layer 55A. In some embodiments, the method for patterning holes and trenches in the IMD layer 55A utilizes a via-first approach, wherein a first optical lithography and etching process forms the holes for vias, and a second optical lithography and etching process forms the trenches for wiring. Other embodiments may use different methods, such as a trench-first approach, a partially via-first approach, or an embedded etch-stop layer approach. The etching technique may utilize multiple steps. For example, a first main etching step may remove a portion of the dielectric material of the IMD layer 55A and terminate on an etch-stop dielectric layer. The etchant may then be switched to remove the etch-stop layer dielectric material. The parameters of various etching steps (e.g., chemical composition, flow rate, gas pressure, reactor power, etc.) can be tuned to produce a tapered sidewall profile with the desired internal cone angle.

[0135] Several conductive materials can be deposited to fill the holes and trenches forming the conductive features 53A and 54A in the first interconnect layer 50A. The openings can first be lined with a conductive diffusion barrier material, and then completely filled with a conductive filler material deposited over the conductive diffusion barrier liner. In some embodiments, a thin conductive seed layer can be deposited over the conductive diffusion barrier liner to help initiate an electrochemical plating (ECP) deposition step to completely fill the openings with the conductive filler material.

[0136] The diffusion barrier conductive liner in via 53A and terminal 54A comprises one or more layers of TaN, Ta, TiN, Ti, Co, or the like, or combinations thereof. The conductive filler layer in via 53A and terminal 54A may comprise a metal such as Cu, Al, W, Co, Ru, or the like, or combinations thereof, or multiple layers thereof. The conductive material used to form conductive features 53A and 54A may be deposited by any suitable method, for example, CVD, PECVD, PVD, ALD, PEALD, ECP, electroless plating, and the like. In some embodiments, the conductive seed layer may be the same conductive material as the conductive filler layer and deposited using a suitable deposition technique (e.g., CVD, PECVD, ALD, PEALD, or PVD, or the like).

[0137] Any excess conductive material above the IMD 55A outside the opening can be removed by a planarization process (e.g., CMP) to form a top surface containing the dielectric region of IMD 55A, which is substantially coplanar with the conductive region of conductive line 54A. The planarization step embeds the conductive via 53A and conductive line 54A into IMD 55A, as... Figure 7 As shown in the image.

[0138] Figure 7 The interconnect layer vertically positioned above the first interconnect layer 50A is the second interconnect layer 50B. In some embodiments, the structures of various interconnect layers (e.g., the first interconnect layer 50A and the second interconnect layer 50B) may be similar. Figure 7 In the example shown, the second interconnect layer 50B includes conductive vias 53B and conductive lines 54B embedded in an insulating film IMD 55B having a planar top surface. The materials and processing techniques described above in the context of the first interconnect layer 50A can also be used to form the second interconnect layer 50B and subsequent interconnect layers.

[0139] Although an exemplary electronic device (FinFET 504) and an example interconnect structure connected to the electronic device have been described, it should be understood that those skilled in the art will appreciate that the above examples are provided for illustrative purposes only to further explain the application of this embodiment, and are not intended to limit this embodiment in any way.

[0140] Figure 8 Draw Figure 7 An enlarged view of area 501 shows the interconnect layer 50B in the initial stage of manufacturing capacitive synaptic units. Figure 6 The through-hole 53B and conductive line 54B are embedded in the insulating film IMD 55B. Conductive line 54B can be used as a word line or bit line of a capacitive synaptic unit. The top dielectric surface of IMD 55B is shown to be substantially coplanar with the top conductive surface of conductive line 54B within process variations.

[0141] exist Figure 9 In this process, an inter-metal dielectric (IMD) layer 530 is formed above the interconnect layer 50B. In some embodiments, the IMD layer 530 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), a low-k dielectric material, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorosilicone glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. The IMD layer 530 may be formed using, for example, CVD, ALD, spin-on-glass (SOG), or other suitable techniques.

[0142] Next, a bottom electrode via (BEVA) structure 540 is formed in the IMD layer 530 to contact the conductive line 54B. In some embodiments, the formation of the BEVA structure 540 includes patterning the IMD layer 530 to form a via opening O1 extending through the IMD layer 530 to expose the conductive line 102, conformally depositing barrier material lining the sidewalls and bottom surface of the via opening O1, depositing filler metal that overfills the via opening O1, and then performing a chemical mechanical polishing (CMP) process to remove excess filler metal and excess barrier material outside the via opening O1, while retaining the barrier material in the via opening O1 as a barrier layer 542 lining the via opening O1, and retaining the filler metal in the via opening O1 as a filler metal structure 544, the underside of which is covered by the barrier layer 542.

[0143] In some embodiments, the barrier layer 542 facilitates the deposition of the filling metal structure 544 and helps reduce the outward diffusion of the metal material filling the metal structure 544. In some embodiments, the barrier layer 542 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable materials. The filling metal structure 544 includes a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive materials.

[0144] exist Figure 10 In this configuration, a multilayer stack of FeCAP material is sequentially deposited over the BEVA structure 540. In some embodiments, the multilayer stack of FeCAP material can be formed via, for example, the following steps: depositing a bottom electrode layer 410' over the BEVA structure 540, then depositing a ferroelectric layer 420' over the bottom electrode layer 410', then depositing a high-k dielectric layer 430' over the ferroelectric layer 420', then depositing an oxide semiconductor layer 440' over the high-k dielectric layer 430', and then depositing a top electrode layer 450' over the oxide semiconductor layer 440'. Details regarding the materials, thicknesses, and other aspects of the bottom electrode layer 410', ferroelectric layer 420', high-k dielectric layer 430', oxide semiconductor layer 440', and top electrode layer 450' are consistent with previous descriptions. Figure 4The materials, thicknesses, and other details of the bottom electrode 410, ferroelectric layer 420, high-k dielectric layer 430, oxide semiconductor layer 440, and top electrode 450 are the same, and therefore will not be repeated for the sake of brevity. In some embodiments, one or more of the bottom electrode layer 410', ferroelectric layer 420', high-k dielectric layer 430', oxide semiconductor layer 440', and top electrode layer 450' are deposited using any suitable deposition method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or similar methods.

[0145] After depositing a multilayer stack of FeCAP material over the BEVA structure 540, a hard mask layer 550' is deposited over the top electrode layer 450' using a suitable deposition technique such as CVD or PECVD. In some embodiments, the hard mask layer 550' comprises a material different from the multilayer stack of FeCAP material. For example, the hard mask layer 550' comprises silicon oxynitride (SiON), silicon nitride, the like, or other suitable dielectric material. Next, a patterned photoresist layer PR is formed over the hard mask layer 550' using a suitable optical lithography process.

[0146] exist Figure 11 In this process, a hard mask layer 550' is patterned into a patterned hard mask 550 by using a photoresist layer PR as an etching mask, and then a top electrode layer 450' is patterned into a top electrode 450 by using the patterned hard mask 550 as an etching mask. In some embodiments, the hard mask layer 550' and the top electrode layer 450' are patterned in a single consecutive etching step. In some other embodiments, the hard mask layer 550' and the top electrode layer 450' are patterned in different etching steps with different etchant chemicals.

[0147] exist Figure 12In this process, a spacer layer 560' is deposited over a patterned hard mask 550. In some embodiments, the spacer layer 560' may include SiN, but in other embodiments, it may include SiC, SiON, silicon oxycarbide (SiOC), the like, and / or combinations thereof. CVD, PVD, ALD, the like, and / or combinations thereof may be used to form the spacer layer 560'. The spacer layer 560' may be formed as a substantially conformal layer, so that the thickness of the vertical portion of the spacer layer 560 on the vertical sidewalls of the top electrode 450 and the patterned hard mask 550 is substantially the same as the thickness of the horizontal portion of the spacer layer 560'.

[0148] exist Figure 13 In this process, an etching process is performed on the spacer layer 560' to remove the horizontal portion of the oxide semiconductor layer 440', while leaving a portion of the spacer layer 560' on the sidewalls of the top electrode 450 and the hard mask 550, serving as a sidewall spacer 560. This step can be interchangeably referred to as a self-aligned spacer (SPA) etching process because the resulting sidewall spacer 560 can be self-aligned with the stack of the top electrode 450 and the hard mask 550 without additional optical lithography processes. The SPA etching process may include a selective anisotropic dry etching process, which etches the spacer layer 560' at a faster etch rate than etching the hard mask 550 and the oxide semiconductor layer 440'.

[0149] exist Figure 14 In this process, one or more etching processes using a hard mask 550 and sidewall spacers 560 as etching masks are used to pattern the oxide semiconductor layer 440', high-k dielectric layer 430', ferroelectric layer 420', and bottom electrode layer 410' into a patterned oxide semiconductor layer 440, a patterned high-k dielectric layer 430, a patterned ferroelectric layer 420, and a patterned bottom electrode 410. The resulting bottom electrode 410, ferroelectric layer 420, high-k dielectric layer 430, oxide semiconductor layer 440, and top electrode 450 can be used together as an FeCAP structure 400, which can be used as a capacitive synaptic unit in a neural network, such as... Figures 1 to 2 As shown.

[0150] The step of patterning layers 410' to 440' can be interchangeably referred to as a self-aligned etching process because the resulting oxide semiconductor layer 440, high-k dielectric layer 430, ferroelectric layer 420, and bottom electrode 410 can be self-aligned with the footprint of the hard mask 550 and sidewall spacers 560 without additional optical lithography processes. By way of example, and not limitation, the self-aligned etching process may include a selective anisotropic dry etching process, which etches the material of layers 410' to 440' at a faster etch rate than etching the hard mask layer 550 and sidewall spacers 560. In some embodiments, the self-aligned etching process includes a plasma dry etching process using chlorine-based or fluorine-based chemicals. Because the high-k dielectric layer 430, ferroelectric layer 420, and bottom electrode 410 are formed using a hard mask 550 and sidewall spacers 560 as etching masks, the high-k dielectric layer 430, ferroelectric layer 420, and top electrode 410 have a width greater than the width of the hard mask 550 and the top electrode 450.

[0151] exist Figure 15 In this configuration, an IMD layer 570 is deposited over the FeCAP structure 400. In some embodiments, the IMD layer 570 may comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), a low-k dielectric material, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorosilicone glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. The IMD layer 530 may be formed using, for example, CVD, ALD, spin-on-glass (SOG), or other suitable techniques.

[0152] Next, a top electrode via (TEVA) structure 582 and conductive line 584 are formed in the IMD layer 570 using, for example, a dual damascene process. For example, the IMD layer 570 can be patterned using suitable optical lithography and etching techniques (e.g., anisotropic RIE using fluorocarbon chemicals) to form openings for the TEVA structure 582 and conductive line 584. The opening for the TEVA structure 582 may be a vertical hole extending through the IMD layer 570 and the hard mask 550 to expose the top electrode 450, and the opening for the conductive line 584 may be a longitudinal trench formed in the upper portion of the IMD layer 570. In some embodiments, the method for patterning the holes and trenches in the IMD layer 570 utilizes a via-first approach, wherein a first optical lithography and etching process forms the hole for the TEVA structure 582, and a second optical lithography and etching process forms the trench for the conductive line 584. Other embodiments may use different methods, for example, a trench-first approach. Once the vias and trenches for the TEVA structure 582 and conductive lines 584 are formed, one or more conductive materials are deposited to overfill the vias and trenches. A CMP process is then performed to remove excess conductive material outside the vias and trenches, while retaining the remaining conductive material for use in the TEVA structure 582 and conductive lines 584. In some embodiments, the TEVA structure 582 and conductive lines 584 include a diffusion barrier layer such as TaN, Ta, TiN, Ti, Co, the like, or combinations thereof, and a filler metal layer such as Cu, Al, W, Co, Ru, the like, or combinations thereof. The conductive lines 584 can be used as bit lines or word lines electrically coupled to the top electrode 450 of the FeCAP structure 400 via the TEVA structure 582.

[0153] Figure 16 This is a cross-sectional view of an integrated circuit structure according to some embodiments of the present disclosure. The IC structure generally includes... Figure 7 The IC structure shown is the same as the IC structure 500, except that the IC structure further includes one or more transistor interconnect layers (e.g., layers 60A and 60B). Each transistor interconnect layer includes one or more BEOL transistors 610 and one or more FeCAP structures 400 disposed above the one or more BEOL transistors 610. The transistor interconnect layer 60A is separated from the underlying interconnect layer 50B by an inter-layer dielectric layer 600, and the transistor interconnect layer 60B is separated from the underlying transistor interconnect layer 60A by another inter-layer dielectric layer 600.

[0154] In some embodiments, each FeCAP structure 400 in a transistor interconnect layer can be used as a synaptic unit of a neural network, and each FeCAP structure 400 includes a bottom electrode 410, a top electrode 450, and a capacitor-switchable multilayer stack 460 disposed between the bottom electrode 410 and the top electrode 450. The capacitor-switchable multilayer stack 460 includes, for example, Figure 15 The diagram shows a ferroelectric layer 420, a high-k dielectric layer 430, and an oxide semiconductor layer 440. For clarity, these layers are not shown in the diagram. Figure 16 The multi-layered stacking is shown in 460.

[0155] In some embodiments, one or more BEOL transistors 610 may be used in neural networks, for example, as transistors and / or WL multiplexers in neuron circuits (in... Figure 2 The transistors in the image are referred to as "MUX" in the image. In some embodiments, one or more BEOL transistors 610 are thin-film transistors, each thin-film transistor including a back gate structure 602 formed over an interlayer dielectric layer 600 using suitable deposition and etching techniques, a gate dielectric layer 604 formed over the back gate structure 602 using suitable deposition and etching techniques, a semiconductor layer 606 formed over the gate dielectric layer 604 using suitable deposition and etching techniques, and source / drain metal electrodes 608 formed over a separation region in the semiconductor layer 606 using suitable deposition and etching techniques. In some embodiments, the semiconductor layer 606 is formed of an oxide semiconductor, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium zinc oxide (GZO), or the like. In some other embodiments, the semiconductor layer 606 is formed of polysilicon.

[0156] Each of the transistor interconnect layers 60A and 60B includes a vertically extending via 622 and a laterally extending conductive line 624 above the corresponding via 622. The via 622 and conductive line 624 can be formed in one or more dielectric layers 628 using, for example, a dual damascene process. In some embodiments, each of the transistor interconnect layers 60A and 60B includes one or more through-vias 626 extending through the corresponding inter-layer dielectric layer 600 to provide electrical connections between the transistor interconnect layers 60A and 60B, and electrical connections between the transistor interconnect layer 60A and the underlying interconnect layers 50A, 50B, and the front-end-of-line (FEOL) transistor 504. In some embodiments, the BEOL transistor 610 in the transistor interconnect layer 60A is a preneuron layer (e.g., as shown in the image). Figures 1 to 2 The neurons in the input neuron layer 110 / 210 shown, and the BEOL transistor 610 in the transistor interconnect layer 60B are the neurons in the post neuron layer (such as...). Figures 1 to 2The neurons in the hidden neuron layers 120 / 220 shown, and the FeCAP structure 400 in the interconnection layers 60A and / or 60B are used as synaptic units to connect neurons in the pre-neuron layer to neurons in the post-neuron layer.

[0157] Based on the above discussion, it is clear that this disclosure provides advantages in various embodiments. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor is any specific advantage required for all embodiments. One advantage is that the multi-layer stacking between the top and bottom electrodes of the FeCAP allows for improved memory window of the FeCAP. Another advantage is improved data retention performance and durability of the FeCAP.

[0158] In some embodiments, the capacitor structure includes a bottom electrode, a top electrode, and a multilayer stack disposed between the bottom electrode and the top electrode. The multilayer stack has a capacitance value switchable between at least two capacitance states. The multilayer stack includes a ferroelectric layer disposed between the bottom electrode and the top electrode, and an oxide compound layer above the ferroelectric layer. In some embodiments, the ferroelectric layer comprises a tetragonal phase and an orthorhombic phase. In some embodiments, the multilayer stack further includes a high-k dielectric layer between the ferroelectric layer and the oxide compound layer. In some embodiments, the high-k dielectric layer has a thickness less than the thickness of the ferroelectric layer and / or the oxide compound layer. In some embodiments, the oxide compound layer is in contact with the top electrode, and the ferroelectric layer is spaced apart from the top electrode. In some embodiments, the top electrode has a width less than the width of the oxide compound layer. In some embodiments, the capacitor structure further includes a hard mask above the top electrode, and the hard mask has a width less than the width of the oxide compound layer.

[0159] In some embodiments, the neural network circuit includes a plurality of first electronic neurons, a plurality of second electronic neurons, and a weight matrix including a plurality of synaptic units, each synaptic unit connecting one of the plurality of first electronic neurons to another of the second electronic neurons. Each synaptic unit includes a capacitor having a bottom electrode, a multilayer stack, and a top electrode above the multilayer stack. The multilayer stack has a capacitance value switchable between at least two capacitance states. The multilayer stack has a ferroelectric layer between the bottom electrode and the top electrode, and a high-k dielectric layer above the ferroelectric layer. In some embodiments, the high-k dielectric layer is thinner than the ferroelectric layer. In some embodiments, the multilayer stack further includes an oxide compound layer. In some embodiments, the oxide compound layer is spaced apart from the ferroelectric layer by the high-k dielectric layer. In some embodiments, the oxide compound layer is thicker than the high-k dielectric layer. In some embodiments, the high-k dielectric layer has opposing surfaces that respectively contact the oxide compound layer and the ferroelectric layer. In some embodiments, the capacitors of each synaptic unit have a top electrode and a bottom electrode that clamp the multilayer stack, and the top electrode and the bottom electrode are made of different materials.

[0160] In some embodiments, a method includes forming a bottom electrode layer over a substrate, forming a ferroelectric layer over the bottom electrode layer, forming an oxide compound layer over the ferroelectric layer, forming a top electrode layer over the oxide compound layer, patterning the top electrode layer as a top electrode, forming sidewall spacers on opposite sidewalls of the top electrode, and patterning the oxide compound layer and the ferroelectric layer after forming the sidewall spacers. In some embodiments, the method further includes forming a high-k dielectric layer over the ferroelectric layer before forming the oxide compound layer. In some embodiments, the high-k dielectric layer is thinner than the ferroelectric layer. In some embodiments, the method further includes patterning the bottom electrode layer as a bottom electrode after forming the sidewall spacers.

[0161] In some embodiments, a capacitor structure includes a bottom electrode, a multilayer stack above the bottom electrode, and a top electrode above the multilayer stack. The multilayer stack includes a ferroelectric layer between the bottom electrode and the top electrode, and a high-k dielectric layer above the ferroelectric layer. In some embodiments, a capacitor structure includes a bottom electrode located on an intermetallic dielectric layer and overlapping a bottom electrode via structure in the intermetallic dielectric layer; a multilayer stack overlapping the bottom electrode, the multilayer stack including a ferroelectric layer contacting the bottom electrode, a high-k dielectric layer contacting the ferroelectric layer, and an oxide semiconductor layer contacting the high-k dielectric layer; a top electrode overlapping the multilayer stack; and sidewall spacers located on opposite sidewalls of the top electrode and contacting the oxide semiconductor layer.

[0162] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A capacitor structure, characterized in that, Include: One bottom electrode; One top electrode; and A multilayer stack is disposed between the bottom electrode and the top electrode, the multilayer stack comprising: A ferroelectric layer is disposed between the bottom electrode and the top electrode; and An oxide compound layer is located above the ferroelectric layer.

2. The capacitor structure as described in claim 1, characterized in that, The multi-layer stack further includes: A high-k dielectric layer is located between the ferroelectric layer and the oxide compound layer.

3. The capacitor structure as described in claim 2, characterized in that, The high-k dielectric layer has a thickness that is smaller than that of the ferroelectric layer.

4. The capacitor structure as described in claim 2, characterized in that, The high-k dielectric layer has a thickness that is less than that of the oxide compound layer.

5. The capacitor structure as described in claim 1, characterized in that, The oxide compound layer is in contact with the top electrode.

6. The capacitor structure as described in claim 1, characterized in that, The ferroelectric layer is spaced apart from the top electrode.

7. The capacitor structure as described in claim 1, characterized in that, The top electrode has a width smaller than that of the oxide compound layer.

8. A capacitor structure, characterized in that, Include: One bottom electrode; A multi-layer stack above the bottom electrode; and A top electrode is located above the multilayer stack, which includes a ferroelectric layer between the bottom electrode and the top electrode, and a high-k dielectric layer above the ferroelectric layer.

9. The capacitor structure as described in claim 8, characterized in that, The high-k dielectric layer is thinner than the ferroelectric layer.

10. A capacitor structure, characterized in that, Include: A bottom electrode is located on an intermetallic dielectric layer and overlaps a bottom electrode via structure in the intermetallic dielectric layer. A multilayer stack overlaps the bottom electrode, the multilayer stack including a ferroelectric layer contacting the bottom electrode, a high-k dielectric layer contacting the ferroelectric layer, and an oxide semiconductor layer contacting the high-k dielectric layer. A top electrode, superimposed on this multi-layer stack; and The sidewall spacers are located on opposite sidewalls of the top electrode and contact the oxide semiconductor layer.

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