Inertial sensor test system
The inertial sensor testing system, which combines partitioning and multiple interfaces, solves the problem of low sensor detection efficiency in existing technologies, and enables simultaneous detection and efficient data transmission of sensors of different models and types.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WUHAN HENGYONG TECH DEV CO LTD
- Filing Date
- 2025-05-20
- Publication Date
- 2026-05-26
AI Technical Summary
Existing inertial sensor testing systems suffer from low sampling rates and insufficient buffers when simultaneously testing a large number of sensors, leading to data loss. Furthermore, they cannot simultaneously test different types and models of sensors, resulting in low testing efficiency and a high failure rate.
The inertial sensor testing system, which adopts a partitioned configuration, combines multiple SPI master controllers with block memory and network port modules to simultaneously detect sensors of different models and types. It uses Ethernet and RS422 electrical interfaces for data transmission, improving data transmission efficiency and real-time interaction.
It enables simultaneous detection of sensors of different models and types, increases the upper limit of the number of synchronous tests, solves the problem of data loss and incompleteness during data transmission, and improves testing efficiency and fault handling capabilities.
Smart Images
Figure CN224285963U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of sensor testing technology, and in particular to an inertial sensor testing system. Background Technology
[0002] Currently, inertial sensor testing typically uses a main controller connected to multiple accelerometers or gyroscopes. However, when simultaneously testing a large number of inertial sensors, the sampling capacity of the data acquisition unit (data logger) is limited, potentially exceeding its capabilities. Furthermore, with multi-channel synchronous sampling, the maximum sampling rate of the data logger is further reduced. Additionally, remote placement of the data logger, considering the number of sampling points, can lead to insufficient buffer space and data loss.
[0003] As the number of inertial sensors to be tested increases, existing equipment can only perform tests sequentially from 1 to n, leading to a sharp increase in data processing volume. If any sensor fails, the test must be restarted, resulting in low testing efficiency and a high failure rate. Furthermore, existing testing methods cannot simultaneously test different types and models of sensors. Utility Model Content
[0004] The main objective of this invention is to provide an inertial sensor testing system that aims to solve at least one of the aforementioned technical problems.
[0005] To achieve the above objectives, this utility model provides an inertial sensor testing system, comprising:
[0006] Host computer;
[0007] The test module includes multiple SPI master controllers, a network port module, and a storage module; wherein, one end of each SPI master controller is connected to at least one inertial sensor under test, the other end of each SPI master controller is connected to one end of the storage module, the other end of the storage module is connected to the network port module, and the test module communicates with the host computer through the network port module.
[0008] In some embodiments, the network port module includes: an RS422 electrical interface and an Ethernet interface; the test module interacts with the host computer through the RS422 electrical interface and / or the Ethernet interface.
[0009] In the event of a data transmission error, the test module will feed back the abnormal status of the transmission link to the host computer in real time through the RS422 electrical interface.
[0010] In some embodiments, the inertial sensor testing system further includes a physical layer chip and a PL port; the Ethernet interface, physical layer chip, PL port, and host computer are connected in sequence.
[0011] In some embodiments, the inertial sensor testing system further includes: a serial port chip; the Ethernet interface, RS422 electrical interface, serial port chip, and host computer are connected in sequence.
[0012] In some embodiments, the storage module is a block memory, including multiple storage blocks, the number of which corresponds one-to-one with the number of SPI master controllers, and each storage block is used to store the test data read by the corresponding SPI master controller.
[0013] In some embodiments, the block memory includes a first read / write terminal, a second read / write terminal, an enable terminal, and a data terminal; the first read / write terminal or the second read / write terminal is connected to the SPI master controller, and the enable terminal and the data terminal are respectively connected to the Ethernet interface.
[0014] In some embodiments, each of the SPI master controllers includes a clock signal terminal, a master-to-slave data output terminal, a master-to-slave data output terminal, and multiple chip select signal terminals; wherein...
[0015] The clock signal terminal, master-output-slave-in data terminal, and master-in-slave-output data terminal of the SPI master controller are respectively connected to the clock signal terminal, master-output-slave-in data terminal, and master-in-slave-out data terminal of the inertial sensor under test.
[0016] The multiple chip select signal terminals of the SPI master controller are respectively connected to the multiple inertial sensors under test one by one.
[0017] In some embodiments, each of the SPI master controllers further includes: a clock signal terminal, a reset signal terminal, a write enable signal terminal, an enable signal terminal, an address signal terminal, and a data signal terminal; the clock signal terminal, reset signal terminal, write enable signal terminal, enable signal terminal, address signal terminal, and data signal terminal of the SPI master controller are connected to the storage module.
[0018] In some embodiments, the inertial sensor testing system further includes a power supply interface; the power supply interface is used to supply power to the testing module.
[0019] In some embodiments, one end of the SPI master controller is connected to multiple inertial sensors of the same or different types.
[0020] This invention provides an inertial sensor testing system, comprising: a host computer; and a testing module including multiple SPI master controllers, a network port module, and a storage module. Each SPI master controller has one end connected to at least one inertial sensor under test, and the other end of each SPI master controller connected to one end of the storage module. The other end of the storage module is connected to the network port module, and the testing module communicates with the host computer through the network port module. In this invention, the testing system employs a partitioned testing approach, enabling simultaneous testing of different models and types of sensors and increasing the maximum number of sensors that can be tested simultaneously. The use of the network port module improves the quantity and efficiency of data transmission, enabling real-time data interaction with the host computer. Attached Figure Description
[0021] Figure 1 This is a structural block diagram of an embodiment of the inertial sensor testing system of this utility model;
[0022] Figure 2 This is a schematic diagram of the hardware connection involved in the embodiment of this utility model;
[0023] Figure 3 This is a schematic diagram of the architecture involved in the embodiment of this utility model;
[0024] Figure 4 This is a schematic diagram illustrating an example of a testing method involved in an embodiment of this utility model.
[0025] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0027] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0028] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model. It should be understood that the specific embodiments described herein are only for explaining this utility model and are not intended to limit this utility model.
[0029] This invention proposes an inertial sensor testing system.
[0030] Reference Figure 1 , Figure 1 This is a structural block diagram of an embodiment of the inertial sensor testing system of this utility model.
[0031] like Figure 1 As shown, the inertial sensor testing system includes:
[0032] Host computer 100;
[0033] The test module 200 includes multiple SPI master controllers, a network port module, and a storage module; wherein, one end of each SPI master controller is connected to at least one inertial sensor under test, the other end of each SPI master controller is connected to one end of the storage module, the other end of the storage module is connected to the network port module, and the test module communicates with the host computer through the network port module.
[0034] Specifically, the inertial sensor testing system is configured with partitioned connections. Multiple SPI master controllers (SPI interfaces) are set in the testing module 200. By connecting the inertial sensor under test (such as an accelerometer, gyroscope, etc.) to multiple SPI master controllers, the traditional SPI one-master-multiple-slave transmission mode is changed. This embodiment adopts the SPI multi-master-multiple-slave mode for data acquisition and transmission, realizing partitioned testing.
[0035] In this embodiment, multiple SPI master controllers (SPI interfaces) are used to connect to partitioned inertial sensors under test, and the testing module performs the testing. Using a partitioned testing approach allows for simultaneous testing of sensors of different models and types, and increases the maximum number of sensors that can be tested simultaneously.
[0036] In one embodiment, one end of the SPI master controller is connected to multiple inertial sensors of the same or different types.
[0037] Specifically, an SPI master controller and at least one inertial sensor under test connected to it are referred to as a partition. In this embodiment, the partition setting in the inertial sensor test system is to set multiple partitions. The SPI master controller is a general type. The inertial sensors under test connected to the SPI master controller of each partition can be of the same type or different types. The inertial sensors under test connected to the SPI master controllers of different partitions can also be of the same type or different types.
[0038] For example, the inertial sensor under test includes, but is not limited to, accelerometers, gyroscopes, inclinometers, and inertial measurement units (IMUs). It is understood that the inertial sensor testing system can also be used for testing other types of sensors, and this embodiment does not limit this application.
[0039] In one embodiment, the inertial sensor testing system is a 96-mesh testing system, which includes six SPI master controllers, each of which is connected to 16 inertial sensors under test.
[0040] It should be noted that this embodiment uses... Figure 2 The following example illustrates the inertial sensor under test, which consists of 96 accelerometers. Figure 2 As shown, the test module in this test system includes six SPI master controllers (SPI interface 1 to SPI interface 6), each of which connects to 16 accelerometers. In practical applications, the test system described in this embodiment can connect different numbers and types of sensors according to test requirements.
[0041] In one embodiment, such as Figure 2 As shown, the network port module includes an RS422 electrical interface and an Ethernet interface; the test module interacts with the host computer through the RS422 electrical interface and / or the Ethernet interface.
[0042] In the event of a data transmission error, the test module will feed back the abnormal status of the transmission link to the host computer in real time through the RS422 electrical interface.
[0043] Specifically, existing PL interfaces have shortcomings in handling large data volume transmission. This embodiment changes the data transmission interface format, using an Ethernet interface combined with an RS422 electrical interface to transmit data to the host computer. This data transmission method enables synchronous batch transmission of partitioned data, resolving issues such as discontinuous packet counts, frame loss, or incompleteness that may occur during transmission. The data transmission interface (Ethernet interface combined with RS422 electrical interface) improves the quantity and efficiency of data transmission, while also enabling real-time information and data interaction with the host computer.
[0044] For example, the Ethernet interface can be a Gigabit Ethernet interface. Through the Gigabit Ethernet interface (or RS422 electrical interface), information and data interaction between the host computer and the test module can be realized. The host computer can send control commands to the test module. At the same time, the test module can feed back test fault information data to the host computer for processing and display in real time through the RS422 electrical interface.
[0045] In one embodiment, such as Figure 3 As shown, the inertial sensor testing system further includes: a physical layer chip PL_PHY and a PL network port; the Ethernet interface PL_ENET, the physical layer chip PL_PHY, the PL network port, and the host computer are connected in sequence.
[0046] In one embodiment, such as Figure 2 As shown, the inertial sensor testing system further includes: a serial port chip; the Ethernet interface PL_ENET, the RS422 electrical interface, the serial port chip, and the host computer are connected in sequence.
[0047] Specifically, the host computer usually refers to the main control computer or controller of the test system, responsible for sending instructions and receiving data. For example... Figure 3 As shown, the PL port (e.g., Ethernet interface) is used to connect to the network for data transmission; PL_PHY represents the physical layer chip (physical layer interface), which is responsible for handling the physical transmission of Ethernet signals; PL_ENET represents the Ethernet interface, which together with PL_PHY constitutes the Ethernet communication module.
[0048] For example, such as Figure 3 As shown, the programmable logic (PL) of the test module can be a ZYNQ (XC7020) model. The PL, or FPGA part, of the test module includes multiple SPI master controllers, a network port module, and a block memory. The Ethernet interface PL_ENET is connected to the physical layer chip PL_PHY, as shown in the reference. Figure 3PL_MDC, PL_MDIO, PL_RGMII, and PL_INT are commonly used interface names in FPGA (Field-Programmable Gate Array) design, representing the following meanings and functions: PL_MDC (Management Data Clock) is the management data clock signal used to synchronize the transmission of management data (MDIO). In FPGA design, PL_MDC is typically used to communicate with external Ethernet switches or other network devices to configure and manage their parameters. PL_MDIO (Management Data Input / Output) is the management data input / output signal used to transmit configuration and management data between the FPGA and external network devices. Through PL_MDIO, the FPGA can read and write to the registers of external devices, thereby enabling device configuration and management. PL_RGMII (Reduced Gigabit Media Independent Interface) is a simplified gigabit media independent interface used to connect the FPGA to an external Ethernet switch or PHY (Physical Layer) chip. The PL_RGMII interface includes transmit and receive data lines, clock lines, and control lines to achieve high-speed data transmission between the FPGA and external network devices. PL_INT (Interrupt) is an interrupt signal used to notify external devices that an event has occurred that requires FPGA processing. For example, an external device may use the PL_INT signal to notify the FPGA that there is data that needs to be processed, an error has occurred, or other important events that require the FPGA's attention.
[0049] In this embodiment, the network port module includes an RS422 electrical interface and an Ethernet interface. By using network port transmission, it is possible to quickly transmit large amounts of data generated by batch testing, thereby solving problems such as discontinuous packet counts, frame loss, and incomplete data transmission failures during the transmission process.
[0050] In one embodiment, the storage module is a block memory, comprising multiple storage blocks, the number of which corresponds one-to-one with the number of SPI master controllers, and each storage block is used to store test data read by the corresponding SPI master controller.
[0051] Specifically, in this embodiment, the storage module of the test module can be a block RAM (BRAM). The BRAM is partitioned into multiple storage blocks, and each SPI master controller stores test data into its corresponding storage block within the BRAM. In practical applications, the number of storage blocks can be greater than or equal to the number of SPI master controllers; this embodiment does not impose any limitation on this.
[0052] Understandably, each SPI master controller stores the test data into the corresponding storage block in the block RAM. The test data of each partition (one SPI master controller and its connected multiple inertial sensors under test) can be verified separately. This avoids the drawbacks of time-consuming serial resampling caused by problems such as bit errors and incomplete data when the amount of existing data increases. At the same time, the partition can simultaneously test different models and types of inertial sensors, such as accelerometers, thereby making the test system described in this embodiment more suitable for testing high sampling rate sensors.
[0053] In one embodiment, such as Figure 3 As shown, the block RAM includes a first read / write terminal PORTA, a second read / write terminal PORTB, an enable terminal EN, and a data terminal DATA; the first read / write terminal PORTA or the second read / write terminal PORTB is connected to the SPI master controller, and the enable terminal EN and the data terminal DATA are respectively connected to the Ethernet interface PL_ENET.
[0054] For example, in block RAM, PORTA and PORTB typically represent two ports of the BRAM, each with its own independent read / write control signals and data lines.
[0055] In one example, PORTA (first read / write port) is a port of the BRAM used for read and write operations, typically including the following signals: ram_clk: clock signal, used for synchronizing read and write operations; ram_rst: reset signal, used to initialize the contents of the BRAM; ram_we: write enable signal, used to control write operations; en: enable signal, used to control read and write operations; ram_ad: address signal, used to specify the address for read and write operations; ram_da: data signal, used to transmit data for read and write operations. PORTB (second read / write port) is another port of the BRAM, also used for read and write operations, typically including signals similar to PORTA, which will not be elaborated here.
[0056] refer to Figure 3 The block RAM is connected to the Ethernet interface PL_ENET, such as... Figure 3As shown, the ENET_EN and ENET_DATA outputs from the Block RAM are related to the Ethernet interface PL_ENET. ENET_EN (EthernetEnable) is an enable signal used to control the enable state of the Ethernet interface PL_ENET. When ENET_EN is high, the Ethernet interface PL_ENET is activated and data transmission is possible; when ENET_EN is low, the Ethernet interface PL_ENET is disabled and data transmission is not possible. ENET_DATA is a data signal used to transmit Ethernet data, typically including send and receive data lines to achieve functions such as data transmission and device configuration.
[0057] In this embodiment, the two ports PORTA and PORTB of the block memory (BRAM) can perform read and write operations simultaneously or independently. This dual-port design allows the BRAM to serve multiple data streams at the same time, improving the parallel processing capability of the test system.
[0058] In one embodiment, such as Figure 3 As shown, each of the SPI master controllers includes a clock signal terminal sck, a master-to-slave data terminal mosi, a master-to-slave data terminal miiso, and multiple chip select signal terminals cs; wherein,
[0059] The clock signal terminal sck, master-output-slave-in data terminal mosi, and master-in-slave-output data terminal miso of the SPI master controller are respectively connected to the clock signal terminal sck, master-output-slave-in data terminal mosi, and master-in-slave-out data terminal miso of the inertial sensor under test.
[0060] The multiple chip select signal terminals (cs) of the SPI master controller are respectively connected to the multiple inertial sensors under test.
[0061] Specifically, such as Figure 3 As shown, SPI_Master represents the SPI master controller (e.g., Figure 3 Six SPI master controllers are shown as examples, each capable of testing 16 SPI slave devices, where the SPI slave devices are inertial sensors under test, such as accelerometers (ACC).
[0062] For example, such as Figure 3As shown, ACC1 represents the first accelerometer. ACC1 has the following pins: sck represents the SPI clock signal, used for synchronous data transmission; mosi represents the master-slave input / output data line, used to send data from the master controller (SPI master controller) to the slave device (accelerometer ACC); miso represents the master-slave output data line, used to receive data from the slave device (accelerometer ACC) to the master controller (SPI master controller); cs1 represents chip select signal 1, used to select the first slave device (e.g., accelerometer ACC). Figure 3 As shown in ACC1); CS2 represents chip select signal 2, used to select the second slave device (e.g., ACC1); Figure 3 As shown in ACC2); CS16 represents chip select signal 16, used to select the sixteenth slave device (e.g., ACC2); Figure 3 (ACC16 shown).
[0063] refer to Figure 3 ACC2 represents the second accelerometer, and ACC16 represents the sixteenth accelerometer. The pinouts for each accelerometer are similar to those for ACC1, and will not be repeated here. The main function of these pins is to implement SPI communication. SCK, MOSI, and MISO are the basic signal lines for SPI communication, while CS1, CS2...CS16 are chip select signals used to select a specific slave device for communication.
[0064] In one embodiment, such as Figure 3 As shown, each of the SPI master controllers further includes: a clock signal terminal ram_clk, a reset signal terminal ram_rst, a write enable signal terminal ram_we, an enable signal terminal en, an address signal terminal ram_ad, and a data signal terminal ram_da; the clock signal terminal ram_clk, the reset signal terminal ram_rst, the write enable signal terminal ram_we, the enable signal terminal en, the address signal terminal ram_ad, and the data signal terminal ram_da of the SPI master controller are connected to the storage module.
[0065] Specifically, such as Figure 3 As shown, SPI_Master×1 represents the first SPI master controller, and SPI_Master×6 represents the sixth SPI master controller. Each SPI master controller has the following pins: ram_clk (clock signal) for synchronous read / write operations; ram_rst (reset signal) for initializing the contents of the Block RAM; ram_we (write enable signal) for controlling write operations; en (en) for controlling read / write operations; ram_ad (address signal) for specifying the address for read / write operations; and ram_da (data signal) for transmitting data during read / write operations.
[0066] In one example, such as Figure 3 As shown, the storage module is a Block RAM. The SPI master controller is connected to the second read / write port PORTB of the Block RAM. PORTB (second read / write port) is a port of the BRAM, including a clock signal terminal ram_clk, a reset signal terminal ram_rst, a write enable signal terminal ram_we, an enable signal terminal en, an address signal terminal ram_ad, and a data signal terminal ram_da. The clock signal terminal ram_clk, reset signal terminal ram_rst, write enable signal terminal ram_we, enable signal terminal en, address signal terminal ram_ad, and data signal terminal ram_da of the SPI master controller are respectively connected to the clock signal terminal ram_clk, reset signal terminal ram_rst, write enable signal terminal ram_we, enable signal terminal en, address signal terminal ram_ad, and data signal terminal ram_da of the Block RAM.
[0067] In one embodiment, such as Figure 2 As shown, the inertial sensor testing system further includes a power supply interface; the power supply interface is used to supply power to the testing module.
[0068] Specifically, depending on the different power requirements of the components in the test module, various power supply interface combinations can be used for power supply. For example, an external power adapter can be used to provide a stable power supply, batteries can be used, USB can be used, and Ethernet can be used to power the system, so as to meet the diverse needs of the inertial sensor test system and improve the flexibility and reliability of the test system. This embodiment does not limit the specific power supply method.
[0069] It is understandable that for testing large quantities of inertial sensors, such as accelerometers (e.g., more than 100 products), the inertial sensor testing system provided in this embodiment can achieve large-scale testing, be compatible with higher sampling rate MEMS devices, transmit large amounts of data at high speeds, and solve various data transmission failures (good robustness).
[0070] This embodiment provides an inertial sensor testing system, including: a host computer; and a testing module comprising multiple SPI master controllers, a network port module, and a storage module. Each SPI master controller has one end connected to at least one inertial sensor under test, and the other end connected to one end of the storage module. The other end of the storage module is connected to the network port module, and the testing module communicates with the host computer through the network port module. In this embodiment, the testing system employs a partitioned testing approach, enabling simultaneous testing of sensors of different models and types, and increasing the maximum number of simultaneous tests. The network port module improves data transmission volume and efficiency, enabling real-time data interaction with the host computer. Data is transmitted to the host computer via a combination of a gigabit network port and an RS422 electrical interface, allowing for synchronous batch transmission of partitioned data. This solves problems such as discontinuous packet counts, frame loss, or incomplete data frames that may occur during transmission.
[0071] It should be noted that, referring to Figure 4 , Figure 4 This is a schematic flowchart illustrating an example of the testing method involved in an embodiment of this utility model. (In conjunction with...) Figure 2 , Figure 3 and Figure 4 The test procedure of the inertial sensor test system proposed in this embodiment is illustrated by way of example.
[0072] like Figure 2 and Figure 3 As shown, the inertial sensor testing system connects to the inertial sensor under test (INS) in sections via its input terminal (SPI master controller side). The testing unit processes the data and transmits it to the host computer via its output terminal (network module side). Specifically, multiple SPI interfaces (SPI master controllers) are used to connect to the INS in sections, and the testing unit performs the testing. The details are as follows: Figure 3 As shown, test data is received via the SPI interface and transmitted to the host computer for data analysis, and finally stored in the block RAM.
[0073] In one embodiment, the system can be divided into six partitions, each with a set of SPI interfaces. Each partition uses a hardware connection method of one master controlling n slaves. The master control software is developed via SPI. The six master groups simultaneously receive data from the slaves they control. Each master verifies the received slave data (determines whether the slave data is valid). If the verification is correct, the data is stored in the corresponding master partition of the BRAM; otherwise, the slave data corresponding to that master is discarded, and the data transmission for that link is restarted to ensure that all received slave data is error-free and stored in the corresponding register. After the data storage is error-free, the network port module controls the read signal of the BRAM port to read the accelerometer test data stored in the BRAM and send it to the host computer according to the protocol frame format. During the data transmission process, the entire transmission link is monitored, and the transmission status of the data link is sent through the RS422 electrical interface. During the data transmission process via the network port, there may be non-contiguous data frames, manifested as discontinuous frame counts or incomplete valid data frames. A retransmission request mechanism can be added during the network port transmission process. If the data is error-free, the data is transmitted to the host computer. If there is an error in the data, the abnormal status of the transmission link will be transmitted to the host computer via the RS422 electrical interface and displayed, so that testers can promptly troubleshoot abnormal problems in the transmission link and thus ensure that the data transmission is error-free.
[0074] For example, refer to Figure 4 The inertial sensor testing system receives SPI data read commands from the host computer; it synchronously reads test data from the inertial sensor under test through multiple SPI master controllers; each SPI master controller is connected to multiple inertial sensors under test at one end; it determines whether the test data is valid; if the test data is valid, it stores the test data in blocks to a block memory; it establishes an Ethernet connection with the host computer; if the connection is successfully established, it transmits the test data to the host computer through the network port module. The network port module includes an RS422 electrical interface and an Ethernet interface, such as... Figure 4 As shown, during transmission via the network port module, the validity of the test data received by the host computer is determined. If the test data received by the host computer is invalid, the number of frame data errors is recorded. When the number of frame data errors in the same frame is less than or equal to a preset threshold, the process returns to the step of establishing an Ethernet connection with the host computer. When the number of frame data errors in the same frame exceeds the preset threshold, a data frame error signal is output and the current test ends. In case of data transmission errors, the abnormal status of the transmission link is fed back to the host computer in real time via the RS422 electrical interface for processing and display. For example, Figure 4 As shown, the preset number of times threshold can be set to 5, or it can be set according to the actual situation. This embodiment does not impose any restrictions on this.
[0075] It should be noted that technical details not described in detail in the test process embodiments of the inertial sensor test system can be found in the inertial sensor test system provided in any embodiment of this utility model, and will not be repeated here.
[0076] It should be understood that the above are merely illustrative examples and do not constitute any limitation on the technical solution of this utility model. In specific applications, those skilled in the art can make settings as needed, and this utility model does not impose any restrictions on this.
[0077] It should be noted that the framework described above is merely illustrative and does not limit the scope of protection of this utility model. In practical applications, those skilled in the art can select some or all of it to achieve the purpose of this embodiment according to actual needs, and no restrictions are imposed here.
[0078] Furthermore, it should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or system that includes that element.
[0079] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0080] The above are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.
Claims
1. An inertial sensor test system, characterized by, include: Host computer; The test module includes multiple SPI master controllers, a network port module, and a storage module; wherein, one end of each SPI master controller is connected to at least one inertial sensor under test, the other end of each SPI master controller is connected to one end of the storage module, the other end of the storage module is connected to the network port module, and the test module communicates with the host computer through the network port module.
2. The system of claim 1, wherein, The network port module includes an RS422 electrical interface and an Ethernet interface; the test module interacts with the host computer through the RS422 electrical interface and / or the Ethernet interface. In the event of a data transmission error, the test module will feed back the abnormal status of the transmission link to the host computer in real time through the RS422 electrical interface.
3. The system of claim 2, wherein, The inertial sensor testing system further includes a physical layer chip and a PL network port; the Ethernet interface, physical layer chip, PL network port, and host computer are connected in sequence.
4. The system of claim 2, wherein, The inertial sensor testing system further includes: a serial port chip; the Ethernet interface, RS422 electrical interface, serial port chip, and host computer are connected in sequence.
5. The system as described in claim 1, characterized in that, The storage module is a block memory, comprising multiple storage blocks. The number of storage blocks corresponds one-to-one with the number of SPI master controllers. Each storage block is used to store the test data read by the corresponding SPI master controller.
6. The system as described in claim 5, characterized in that, The block memory includes a first read / write terminal, a second read / write terminal, an enable terminal, and a data terminal; the first read / write terminal or the second read / write terminal is connected to the SPI master controller, and the enable terminal and the data terminal are respectively connected to the Ethernet interface.
7. The system as described in claim 1, characterized in that, Each of the SPI master controllers includes a clock signal terminal, a master-slave input / output data terminal, a master-slave output data terminal, and multiple chip select signal terminals; wherein... The clock signal terminal, master-output-slave-in data terminal, and master-in-slave-output data terminal of the SPI master controller are respectively connected to the clock signal terminal, master-output-slave-in data terminal, and master-in-slave-out data terminal of the inertial sensor under test. The multiple chip select signal terminals of the SPI master controller are respectively connected to the multiple inertial sensors under test one by one.
8. The system as described in claim 7, characterized in that, Each of the SPI master controllers further includes: a clock signal terminal, a reset signal terminal, a write enable signal terminal, an enable signal terminal, an address signal terminal, and a data signal terminal; the clock signal terminal, reset signal terminal, write enable signal terminal, enable signal terminal, address signal terminal, and data signal terminal of the SPI master controller are connected to the storage module.
9. The system as described in claim 1, characterized in that, The inertial sensor testing system further includes a power supply interface; the power supply interface is used to supply power to the testing module.
10. The system as described in any one of claims 1 to 9, characterized in that, One end of the SPI master controller is connected to multiple inertial sensors of the same or different types.