Data reading circuit of SPAD array

Abstract

The utility model relates to the technical field of electronic circuits, and discloses a data reading circuit of an SPAD array, which comprises an SPAD array, an SA module and a digital processing module, the SPAD array comprises N SPAD modules, and each SPAD module comprises an SPAD unit, a buf driver and a transmission gate which are connected in sequence; the SA module comprises a first MOS tube, a second MOS tube, an SA comparator and an SR latch, the conduction state of the first MOS tube and the conduction state of the second MOS tube are controlled through the digital processing module, the BUS is pre-charged to VDDVREF (namely half of digital power supply voltage) before data transmission, the voltage change range during data transmission is narrowed, meanwhile, the SA comparator is used for quickly responding to voltage change and comparing, and the data transmission speed is improved. And the data transmission time is obviously shortened.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, and in particular to a data readout circuit for a SPAD array. Background Technology

[0002] Currently, most SPAD (single-photon avalanche diode) arrays rely on multi-level buffer modules for data transmission to achieve long-distance data transmission. For example... Figure 1 As shown, all SPAD arrays are connected to the digital module via a bus, and the data output from the SPAD arrays is transmitted to the digital processing module for further processing via the bus. However, as the specifications of SPAD arrays continue to increase, the size of the SPAD chips will increase significantly, which will also significantly increase the parasitic resistance (R) and parasitic capacitance (C) parameters on the bus used for data transmission. This leads to a significant increase in data transmission latency, a significant decrease in transmission efficiency, and a significant increase in power consumption.

[0003] Specifically, the increased parasitic RC parameters of the Bus significantly increase the signal propagation delay, impacting data real-time performance. Simultaneously, the increased parasitic RC parameters exacerbate signal attenuation on the Bus, requiring higher drive capability to maintain signal integrity and directly reducing data transmission efficiency. Furthermore, overcoming signal attenuation caused by Bus parasitic parameters typically necessitates increasing buffer drive capability, leading to a significant increase in power consumption.

[0004] Therefore, a new data readout circuit is urgently needed to solve these problems in order to meet the requirements of efficient and low-power data transmission for large-scale SPAD arrays. Utility Model Content

[0005] In view of the shortcomings of the prior art, the purpose of this utility model is to provide a data readout circuit for a SPAD array that can use the detection mechanism of an SA comparator to reduce the flip range of data transmission, thereby ensuring data transmission efficiency and reducing power consumption waste during data transmission.

[0006] To solve the above technical problems, the present invention adopts the following technical solution:

[0007] A data readout circuit for a SPAD array includes: a SPAD array, an SA module, and a digital processing module;

[0008] The SPAD array includes: N SPAD modules, each SPAD module including a SPAD unit, a buf driver and a transmission gate connected in sequence; the output terminals of the N SPAD modules are all connected to a BUS bus; a gate enable signal is connected to the transmission gate, where N is a positive integer greater than 0;

[0009] The SA module includes: a first MOSFET, a second MOSFET, an SA comparator, and an SR latch. The gate of the first MOSFET is connected to a first enable signal, and the drain of the first MOSFET is connected to the negative input terminal of the SA comparator. The gate of the second MOSFET is connected to the output terminal of an inverter, and the input terminal of the inverter is connected to a second enable signal. The drain of the second MOSFET is connected to the positive input of the SA comparator and connected to the BUS bus. The sources of the first and second MOSFETs are connected to the VDD_VREF power supply terminal. The positive output terminal of the SA comparator is connected to the S terminal of the SR latch, and the negative output terminal of the SA comparator is connected to the R terminal of the SR latch. The output of the SR latch serves as the output of the SA module. The voltage of VDD_VREF is half of the digital power supply voltage.

[0010] The digital processing module is used to output the gating enable signal, the first enable signal, and the second enable signal, and to receive the output of the SA module and perform digital processing.

[0011] In the data readout circuit of the SPAD array, when the first enable signal is low and the second enable signal is high, the voltage at the two input terminals of the SA comparator is charged to VDD_VREF, and the output of the SR latch is held.

[0012] When the first enable signal is low and the second enable signal is low, the positive input terminal of the SA comparator, i.e. the BUS bus voltage, is disconnected from the VDD_VREF power supply terminal, the BUS bus is floating, and the SR latch output is held.

[0013] When both the first enable signal and the second enable signal are low, and the gate enable signal is also low, the output voltage of the SPAD module is superimposed on the BUS bus. The SA comparator compares the BUS bus voltage with the negative input voltage of the SA comparator, and the SR latch outputs 1 or 0.

[0014] In the data readout circuit of the SPAD array, the SA comparator includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The gate of the first PMOS transistor is the positive output terminal of the SA comparator, the gate of the second PMOS transistor is the negative output terminal of the SA comparator, the gate of the third NMOS transistor is the positive input terminal of the SA comparator, and the gate of the fourth NMOS transistor is the negative input terminal of the SA comparator. The gate of the first PMOS transistor is connected to the gate of the first NMOS transistor, the drain of the second PMOS transistor, the drain of the fourth PMOS transistor, and the drain of the second NMOS transistor. The gate of the second PMOS transistor is connected to the gate of the second NMOS transistor, the drain of the first PMOS transistor, and the drain of the third PMOS transistor. The source of each PMOS transistor is connected to the digital power supply VDD terminal. The source of the first NMOS transistor is connected to the drain of the fifth PMOS transistor and the drain of the third NMOS transistor. The source of the second NMOS transistor is connected to the drain of the sixth PMOS transistor and the drain of the fourth NMOS transistor. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the drain of the third PMOS transistor. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor and the drain of the fourth PMOS transistor. The source of the third NMOS transistor and the source of the fourth NMOS transistor are connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the SA enable signal. The gates of the third PMOS transistor and the fifth PMOS transistor are connected to the SA enable signal. The gates of the fourth PMOS transistor and the sixth PMOS transistor are connected to the SA enable signal. The source of the fifth NMOS transistor is grounded.

[0015] In the data readout circuit of the SPAD array, the SA comparator operates when the third PMOS transistor, fourth PMOS transistor, fifth PMOS transistor, sixth PMOS transistor, and fifth NMOS transistor are turned on, and the SA comparator does not operate when the third PMOS transistor, fourth PMOS transistor, fifth PMOS transistor, sixth PMOS transistor, and fifth NMOS transistor are turned off.

[0016] In the data readout circuit of the SPAD array, the SA module further includes a third MOS transistor. The gate of the third MOS transistor is connected to the first enable signal, the drain of the third MOS transistor is connected to the drain of the first MOS transistor and the negative input terminal of the SA comparator, and the source of the third MOS transistor is grounded.

[0017] In the data readout circuit of the SPAD array, the SA module further includes a fourth MOS transistor. The gate of the fourth MOS transistor is connected to the first enable signal, the drain of the fourth MOS transistor is connected to the positive input terminal of the SA comparator, and the source of the fourth MOS transistor is grounded.

[0018] In the data readout circuit of the SPAD array, the first MOS transistor is a PMOS, the third MOS transistor is an NMOS, the second MOS transistor is a PMOS, and the fourth MOS transistor is an NMOS.

[0019] In the data readout circuit of the SPAD array, the SA module does not work when the first enable signal is high, the second enable signal is low, and the gate enable signal is high.

[0020] In the data readout circuit of the SPAD array, when the output data of a SPAD module is 0, the BUS voltage value drops and the SR latch outputs 0.

[0021] When a SPAD module outputs a value of 1, the BUS voltage rises, and the SR latch outputs 1.

[0022] In the data readout circuit of the SPAD array, the first MOS transistor and the second MOS transistor are the same.

[0023] Compared to existing technologies, the data readout circuit for the SPAD array provided by this invention, by setting an SA module between the SPAD array and the digital processing module, wherein the SA module includes a first MOSFET, a second MOSFET, an SA comparator, and an SR latch, and the first and second MOSFETs are positioned between the digital power supply and the input of the SA comparator, and the conduction state of the first and second MOSFETs is controlled by the digital processing module, it achieves pre-charging of the BUS bus to VDD_VREF (i.e., half of the digital power supply voltage) before data transmission, reducing the voltage variation range during data transmission. Simultaneously, the SA comparator quickly responds to voltage changes and compares them, significantly shortening the data transmission time. Furthermore, the outputs of N SPAD modules are connected to the same BUS bus, supporting parallel data transmission. The module for data transmission can be flexibly selected by controlling the gate enable signal of the transmission gate. Moreover, the SA comparator can quickly and accurately compare the BUS bus voltage and output the detection result, ensuring efficient data readout and improving transmission efficiency. In addition, limiting the BUS bus voltage variation range to a small range during pre-charging reduces charge consumption, thereby reducing power waste. Attached Figure Description

[0024] Figure 1 A circuit block diagram of the data readout circuit for a SPAD array provided by the prior art.

[0025] Figure 2 The circuit block diagram of the data readout circuit of the SPAD array provided by this utility model.

[0026] Figure 3 This is a circuit diagram of a first preferred embodiment of the SA module in the data readout circuit of the SPAD array provided by this utility model.

[0027] Figure 4 A circuit diagram of the SA comparator in the data readout circuit of the SPAD array provided by this utility model.

[0028] Figure 5 This is a circuit diagram of a second preferred embodiment of the SA module in the data readout circuit of the SPAD array provided by this utility model.

[0029] Figure 6 The circuit diagram is shown in the third preferred embodiment of the SA module in the data readout circuit of the SPAD array provided by this utility model.

[0030] Figure 7 Timing diagram of each signal in the data readout circuit of the SPAD array provided by this utility model.

[0031] Explanation of reference numerals in the attached figures

[0032] SPAD array 10, SA module 20, digital processing module 30, SPAD module 11, buf driver 12, transmission gate 13, first MOSFET Q1, second MOSFET Q2, comparator CMP1, SR latch SR1, third MOSFET Q3, fourth MOSFET Q4, first PMOS transistor PM1, second PMOS transistor PM2, third PMOS transistor PM3, fourth PMOS transistor PM4, fifth PMOS transistor PM5, sixth PMOS transistor PM6, first NMOS transistor NM1, second NMOS transistor NM2, third NMOS transistor NM3, fourth NMOS transistor NM4, fifth NMOS transistor NM5, first enable signal ENN_VREF, second enable signal PRE_SA_ENN, gate enable signal READ_ENN, digital power supply voltage VDD Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0034] The data readout circuit of the SPAD array 10 provided by this utility model mainly solves the problem in a large-size SPAD array 10 that the BUS bus is pre-charged to 1 / 2VDD (i.e., digital power supply voltage VDD) through the SA module 20. When a SPAD module 11 outputs VDD, the BUS bus voltage can quickly change from 1 / 2VDD to VDD. This results in low charge consumption and low power consumption. Similarly, when a SPAD outputs 0, the BUS bus voltage quickly changes from 1 / 2VDD to 0, thereby reducing data transmission delay, improving transmission efficiency, and reducing power consumption waste.

[0035] Please see Figure 2 The data readout circuit of the SPAD array 10 provided in the first preferred embodiment of this utility model includes: SPAD array 10, SA (SenseAmplifier) ​​module 20 and digital processing module 30. SPAD array 10 is connected to SA module 20 through BUS bus. The output terminal of SA module 20 is connected to digital processing module 30. Digital processing module 30 is also connected to SA module 20 and is used to output different control signals to control the working state of SA module 20.

[0036] In this embodiment, the SPAD array 10 includes N SPAD modules 11, where N is a positive integer greater than 0. The outputs of all N SPAD modules 11 are connected to a BUS bus. Each SPAD module 11 includes a SPAD unit (not shown in the figure), a buf driver 12, and a transmission gate 13 connected in sequence. The SPAD unit, buf driver 12, and transmission gate 13 are connected in sequence, and the transmission gate 13 is connected to the SA module 20 via the BUS bus. A gate enable signal READ_ENN is connected to the transmission gate 13 to control the data output of the SPAD unit. When a SPAD module 11 outputs 0 data, the BUS bus voltage decreases, and the SR latch SR1 outputs 0; when a SPAD module 11 outputs 1 data, the BUS bus voltage increases, and the SR latch SR1 outputs 1.

[0037] Please refer to the following: Figure 3 The SA module 20 includes a first MOSFET Q1, a second MOSFET Q2, an SA comparator CMP1, and an SR latch SR1. The first MOSFET Q1 and the second MOSFET Q2 are the same, both being P-channel field-effect transistors. When the gate of the MOSFET is at a low level, the MOSFET is turned on.

[0038] The gate of the first MOSFET Q1 is connected to the first enable signal ENN_VREF, and the drain of the first MOSFET Q1 is connected to the negative input terminal of the SA comparator CMP1. The gate of the second MOSFET Q2 is connected to the output terminal of an inverter, and the input terminal of the inverter is connected to the second enable signal PRE_SA_ENN. The drain of the second MOSFET Q2 is connected to the positive input of the SA comparator CMP1 and connected to the BUS bus. The sources of the first MOSFET Q1 and the second MOSFET Q2 are connected to the VDD_VREF power supply terminal. The positive output terminal of the SA comparator CMP1 is connected to the S terminal of the SR latch SR1, and the negative output terminal of the SA comparator CMP1 is connected to the R terminal of the SR latch SR1. The output of the SR latch SR1 serves as the output of the SA module 20.

[0039] Wherein, the voltage VDD_VREF is half of the digital power supply voltage VDD, that is, VDD_VREF = 1 / 2VDD. The digital processing module 30 is used to output the gate enable signal READ_ENN to control the output data of the SPAD module 11. The digital processing module 30 is also used to output the first enable signal ENN_VREF and the second enable signal PRE_SA_ENN to control the on and off states of the first MOSFET Q1 and the second MOSFET Q2, respectively. The digital processing module 30 is also used to receive the output of the SA module 20, thereby outputting the output data of the SPAD module 11.

[0040] SA comparator CMP1 is mainly used to compare the voltages at two input terminals. When the voltages at both input terminals are high, SA comparator CMP1 is working. When the voltages at both input terminals are low, SA comparator CMP1 is working. That is, when the first enable signal ENN_VREF is high, the second enable signal PRE_SA_ENN is low, and the gate enable signal READ_ENN is high, SA module 20 is not working. The high and low level states of the first enable signal ENN_VREF, the second enable signal PRE_SA_ENN, and the gate enable signal READ_ENN are controlled by digital processing module 30.

[0041] The data readout circuit of the SPAD array 10 of this invention includes the following stages in operation, as shown in the specific timing diagram. Figure 7 As shown:

[0042] 1. Pre-charging stage

[0043] Before data reading, the first enable signal ENN_VREF is changed from high to low, pre-charging the voltage at the negative input of SA comparator CMP1 to VDD_VREF (i.e., 1 / 2VDD). Then, the second enable signal PRE_SA_ENN is pulled high, pre-charging the voltage at the positive input of SA comparator CMP1 to VDD_VREF as well. The timing diagram is as follows. Figure 7 As shown. At this time, the voltage values ​​at both input terminals of SA comparator CMP1 are 1 / 2VDD, that is, VREF_SA=VBUS=1 / 2VDD. The pre-charge stage ensures that the input terminals of SA comparator CMP1 are at a known reference voltage level (i.e., 1 / 2VDD) before the comparison begins.

[0044] This invention ensures that during the pre-charging phase, the digital processing module 30 controls the high and low levels of the first enable signal ENN_VREF and the second enable signal PRE_SA_ENN respectively, so that the voltage at the two input terminals of the SA comparator CMP1 is charged to 1 / 2VDD. This ensures that when the SPAD module 11 outputs data, the voltage can quickly change from 1 / 2VDD to VDD. That is, when the first enable signal ENN_VREF is low and the second enable signal PRE_SA_ENN is high, the voltage at the two input terminals of the SA comparator CMP1 is charged to VDD_VREF, and the output of the SR latch SR1 is maintained at this time.

[0045] 2. Data Reading Stage

[0046] When the first enable signal ENN_VREF is low and the second enable signal PRE_SA_ENN is low, the positive input terminal of SA comparator CMP1, i.e. the BUS bus voltage, is disconnected from the VDD_VREF power supply terminal, making the BUS bus floating. The output of SR latch SR1 is held, waiting for the SPAD unit output to change the voltage value on the BUS bus.

[0047] That is, after the second enable signal PRE_SA_ENN remains high for a period of time, the digital processing module 30 pulls it low to 0. At this time, the second MOSFET Q2 is turned off, disconnecting the direct connection between the BUS bus and the digital power supply voltage VDD, making the BUS bus float (i.e., unconnected), waiting for the SPAD unit to output and change the voltage value on the BUS bus. When the gate enable signal READ_EN = 1 and READ_ENN = 0 on the transmission gate 13 of a certain SPAD module 11, the SPAD module 11 outputs SPAD_OUT1 to the BUS bus. When VREF_SA = 1, the SA module 20 outputs SA_DOUT to reflect the output result of the SPAD module 11.

[0048] When the SPAD module 11 performs data transmission, according to the size of the data to be transmitted, the voltage value of the BUS bus will change accordingly:

[0049] If the data to be transmitted is 0, the VBUS voltage value drops and is lower than VREF_SA (1 / 2VDD).

[0050] If the data to be transmitted is 1, the VBUS voltage value rises and is higher than VREF_SA (1 / 2VDD).

[0051] 3. Comparison stage

[0052] When the first enable signal ENN_VREF and the second enable signal PRE_SA_ENN are both at low level, and the gated enable signal READ_ENN is also at low level, the output voltage of the SPAD module 11 is superimposed on the BUS bus, and the SA comparator CMP1 compares the BUS bus voltage with the voltage at the negative input terminal of the SA comparator CMP1, causing the SR latch SR1 to output 1 or 0.

[0053] Specifically, by outputting a high-level SA_EN signal through the digital processing module 30, the SA comparator CMP1 starts to work (such as Figure 7 in the T3 time period), compares the voltage VBUS of the BUS bus with the voltage value of the reference voltage ENN_VREF, and according to the comparison result of the SA comparator CMP1, the SR latch SR1 outputs a data signal DOUT:

[0054] If VBUS < ENN_VREF (that is, the data to be transmitted is 0), DOUT outputs 0.

[0055] If VBUS > ENN_VREF (that is, the data to be transmitted is 1), DOUT outputs 1.

[0056] 4. End stage

[0057] After all the data of the SPAD unit is read out, the digital processing module 30 configures PRE_SA_ENN = 0 and ENN_VREF = 1, reduces the voltages of VREF_SA and VBUS to 0, and ends the data detection.

[0058] The data readout circuit of the present invention limits the fluctuation range of the voltage value of the BUS bus between 0 and 1 / 2VDD by adding the SA module 20 to the BUS bus, reduces the flip range of data transmission, reduces the power consumption loss during data transmission, and at the same time shortens the data transmission time and improves the data detection efficiency.

[0059] Please refer to Figure 4The SA comparator CMP1 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5. The six PMOS transistors and five NMOS transistors form a cross-coupled circuit structure, which can be used to quickly compare two input voltages and is suitable for high-speed data readout applications.

[0060] In a specific implementation, the gate of the first PMOS transistor PM1 is the positive output terminal of the SA comparator CMP1, the gate of the second PMOS transistor PM2 is the negative output terminal of the SA comparator CMP1, the gate of the third NMOS transistor NM3 is the positive input terminal of the SA comparator CMP1, and the gate of the fourth NMOS transistor NM4 is the negative input terminal of the SA comparator CMP1.

[0061] The gate of the first PMOS transistor PM1 is connected to the gate of the first NMOS transistor NM1, the drain of the second PMOS transistor PM2, the drain of the fourth PMOS transistor PM4, and the drain of the second NMOS transistor NM2. The gate of the second PMOS transistor PM2 is connected to the gate of the second NMOS transistor NM2, the drain of the first PMOS transistor PM1, the drain of the third PMOS transistor PM3, and the drain of the first NMOS transistor NM1. The sources of all PMOS transistors are connected to the digital power supply VDD terminal. The source of the first NMOS transistor NM1 is connected to the drain of the fifth PMOS transistor PM5 and the drain of the third NMOS transistor NM3. The source of the second NMOS transistor NM2 is connected to the drain of the sixth PMOS transistor PM6 and the drain of the fourth NMOS transistor NM4. The drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1 and the drain of the third PMOS transistor. The drain of the second NMOS transistor NM2 is connected to the drain of the second PMOS transistor PM2 and the drain of the fourth PMOS transistor. The source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are connected to the drain of the fifth NMOS transistor NM5. The gate of the fifth NMOS transistor NM5 is connected to the SA enable signal. The gate of the third PMOS transistor PM3 and the gate of the fifth PMOS transistor PM5 are connected to the SA enable signal. The gate of the fourth PMOS transistor PM4 and the gate of the sixth PMOS transistor PM6 are connected to the SA enable signal. The source of the fifth NMOS transistor NM5 is grounded.

[0062] When the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, and the fifth NMOS transistor NM5 are turned on, the SA comparator CMP1 operates; when the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, and the fifth NMOS transistor NM5 are turned off (i.e., cut off), the SA comparator CMP1 does not operate.

[0063] The SA comparator CMP1 utilizes a cross-coupling structure consisting of six PMOS transistors (PM1-PM6) and five NMOS transistors (NM1-NM5) along with a positive feedback mechanism, resulting in a very fast response speed suitable for high-speed data readout applications. Furthermore, due to the positive feedback, the CMP1 exhibits very high gain, amplifying even minute input voltage differences and enhancing comparison sensitivity. Additionally, the CMP1 remains inactive when the SA_EN signal is invalid, reducing power consumption. Even when operational, the high-speed response of the CMP1 allows for comparison completion in a short time, further reducing power consumption.

[0064] Please see Figure 5 In the data readout circuit of the SPAD array 10 provided in the second preferred embodiment of this utility model, the SA module 20 further includes a third MOS transistor Q3. The third MOS transistor Q3 is an NMOS transistor, which is turned on when its gate is at a high level. The gate of the third MOS transistor Q3 is connected to the first enable signal ENN_VREF, the drain of the third MOS transistor Q3 is connected to the drain of the first MOS transistor Q1 and the negative input terminal of the SA comparator CMP1, and the source of the third MOS transistor Q3 is grounded.

[0065] The third MOSFET Q3 is used to turn on during the comparison phase, clamping the negative input voltage of the SA comparator CMP1 to 0V, thereby improving the accuracy and stability of the comparator CMP1. In other phases, the third MOSFET Q3 does not directly participate in the operation but provides protection for the circuit. Since the other parts of the data readout circuit in the second preferred embodiment are the same as those in the first preferred embodiment described above, they will not be repeated here.

[0066] Please see Figure 6 In the data readout circuit of the SPAD array 10 provided in the third preferred embodiment of this utility model, the SA module 20 further includes a fourth MOS transistor Q4. The fourth MOS transistor Q4 is an NMOS transistor, which is turned on when its gate is at a high level. The gate of the fourth MOS transistor Q4 is connected to the first enable signal ENN_VREF, the drain of the fourth MOS transistor Q4 is connected to the positive input terminal of the SA comparator CMP1, and the source of the fourth MOS transistor Q4 is grounded.

[0067] Since the gate of the fourth MOSFET Q4 is connected to the ENN_VREF signal, during the comparison phase, when ENN_VREF is high, the fourth MOSFET Q4 is turned on, pulling the negative input terminal (ENN-) of the SA comparator CMP1 low to near ground potential (0V), thereby improving the accuracy and stability of the comparison. Since the other parts of the data readout circuit in the third preferred embodiment are the same as those in the second preferred embodiment described above, they will not be repeated here.

[0068] In the data readout circuit of this utility model, the digital processing module 30, in addition to generating the various control signals mentioned above (such as PRE_SA_ENN, ENN_VREF, READ_ENN, SA_EN, etc.), is also used to precisely control the timing of each signal to ensure the orderly progress of the entire data readout process. The timing control is shown in Figure 7.

[0069] During the pre-charging phase, the digital processing module 30 pulls PRE_SA_ENN high to pre-charge the BUS bus to 1 / 2VDD and pulls ENN_VREF low to ensure that the reference voltage VREF_SA is stable at 1 / 2VDD.

[0070] During the data transmission phase, PRE_SA_ENN is first pulled low to put the BUS bus into a floating state, waiting for the output of SPAD module 11. As needed, the READ_ENN of a certain SPAD unit is pulled low to transmit the output signal of SPAD module 11 to the BUS bus.

[0071] During the data comparison phase, SA_EN is first pulled high to start SA module 20, the voltage VBUS of the BUS bus is compared with the reference voltage VREF_SA, and the comparison result is output to DOUT through SR latch SR1.

[0072] At the end of the process, PRE_SA_ENN and ENN_VREF are pulled high, and the voltage of the BUS bus and the reference voltage VREF_SA is reduced to 0, thus ending the data detection.

[0073] It should be noted that the digital processing module 30 can directly use the TDC module commonly used in ranging systems.

[0074] In summary, this invention precharges the BUS bus to VDD_VREF (half of the digital power supply voltage). During data transmission, the BUS bus voltage only needs to vary slightly around VDD_VREF, instead of varying across the entire range from 0 to VDD. This pre-charging mechanism reduces the magnitude of voltage changes, thereby shortening data transmission time. Furthermore, the reduced voltage variation range during data transmission decreases charge consumption and lowers power consumption.

[0075] Meanwhile, the data readout circuit, through the SA comparator, can quickly respond to changes in the BUS bus voltage and compare it with the reference voltage VDD_VREF. This fast comparison capability allows data to be detected and output in a short time, further reducing data transmission latency. The SA comparison mechanism is particularly suitable for large-scale SPAD arrays 10, enabling efficient reading of large amounts of data. Furthermore, through parallel data transmission and the fast comparator, the data readout efficiency of large-scale SPAD arrays 10 can be significantly improved.

[0076] Furthermore, the data readout circuit uses the method of connecting the output terminals of N SPAD modules 11 to the BUS bus, allowing the data of multiple SPAD modules 11 to be transmitted in parallel on the same bus. By controlling the gate enable signal of the transmission gate 13, the SPAD module 11 that needs to transmit data can be flexibly selected. Moreover, the comparator can directly compare the data voltage on the BUS bus quickly and accurately, and output the result through the SR latch, realizing an efficient voltage comparison mechanism to ensure that the data can be read quickly and accurately.

[0077] It is understood that those skilled in the art can make equivalent substitutions or modifications based on the technical solution and inventive concept of this utility model, and all such substitutions or modifications should fall within the protection scope of the appended claims of this utility model.

Claims

1. A data readout circuit for a SPAD array, characterized in that, include: SPAD array, SA module, and digital processing module; The SPAD array includes: N SPAD modules, each SPAD module including a SPAD unit, a buf driver and a transmission gate connected in sequence; the output terminals of the N SPAD modules are all connected to a BUS bus; a gate enable signal is connected to the transmission gate, where N is a positive integer greater than 0; The SA module includes: a first MOSFET, a second MOSFET, an SA comparator, and an SR latch. The gate of the first MOSFET is connected to a first enable signal, and the drain of the first MOSFET is connected to the negative input terminal of the SA comparator. The gate of the second MOSFET is connected to the output terminal of an inverter, and the input terminal of the inverter is connected to a second enable signal. The drain of the second MOSFET is connected to the positive input of the SA comparator and connected to the BUS bus. The sources of the first and second MOSFETs are connected to the VDD_VREF power supply terminal. The positive output terminal of the SA comparator is connected to the S terminal of the SR latch, and the negative output terminal of the SA comparator is connected to the R terminal of the SR latch. The output of the SR latch serves as the output of the SA module. The voltage of VDD_VREF is half of the digital power supply voltage. The digital processing module is used to output the gating enable signal, the first enable signal, and the second enable signal, and to receive the output of the SA module and perform digital processing.

2. The data readout circuit of the SPAD array according to claim 1, characterized in that, When the first enable signal is low and the second enable signal is high, the voltage at both input terminals of the SA comparator is charged to VDD_VREF, and the output of the SR latch is held. When the first enable signal is low and the second enable signal is low, the positive input terminal of the SA comparator, i.e. the BUS bus voltage, is disconnected from the VDD_VREF power supply terminal, the BUS bus is floating, and the SR latch output is held. When both the first enable signal and the second enable signal are low, and the gate enable signal is also low, the output voltage of the SPAD module is superimposed on the BUS bus. The SA comparator compares the BUS bus voltage with the negative input voltage of the SA comparator, and the SR latch outputs 1 or 0.

3. The data readout circuit of the SPAD array according to claim 1, characterized in that, The SA comparator includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The gate of the first PMOS transistor is the positive output terminal of the SA comparator, the gate of the second PMOS transistor is the negative output terminal of the SA comparator, the gate of the third NMOS transistor is the positive input terminal of the SA comparator, and the gate of the fourth NMOS transistor is the negative input terminal of the SA comparator. The gate of the first PMOS transistor is connected to the gate of the first NMOS transistor, the drain of the second PMOS transistor, the drain of the fourth PMOS transistor, and the drain of the second NMOS transistor. The gate of the second PMOS transistor is connected to the gate of the second NMOS transistor, the drain of the first PMOS transistor, the drain of the third PMOS transistor, and the first NMOS transistor. The drain of each PMOS transistor is connected to the digital power supply VDD terminal. The source of the first NMOS transistor is connected to the drain of the fifth PMOS transistor and the drain of the third NMOS transistor. The source of the second NMOS transistor is connected to the drain of the sixth PMOS transistor and the drain of the fourth NMOS transistor. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the drain of the third PMOS transistor. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor and the drain of the fourth PMOS transistor. The source of the third NMOS transistor and the source of the fourth NMOS transistor are connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the SA enable signal. The gates of the third PMOS transistor and the fifth PMOS transistor are connected to the SA enable signal. The gates of the fourth PMOS transistor and the sixth PMOS transistor are connected to the SA enable signal. The source of the fifth NMOS transistor is grounded.

4. The data readout circuit of the SPAD array according to claim 3, characterized in that, The SA comparator operates when the third, fourth, fifth, sixth, and fifth PMOS transistors are turned on; the SA comparator does not operate when the third, fourth, fifth, sixth, and fifth PMOS transistors are turned off.

5. The data readout circuit of the SPAD array according to claim 1, characterized in that, The SA module also includes a third MOS transistor, the gate of which is connected to the first enable signal, the drain of which is connected to the drain of the first MOS transistor and the negative input terminal of the SA comparator, and the source of which is grounded.

6. The data readout circuit of the SPAD array according to claim 5, characterized in that, The SA module also includes a fourth MOS transistor, the gate of which is connected to the first enable signal, the drain of which is connected to the positive input terminal of the SA comparator, and the source of which is grounded.

7. The data readout circuit of the SPAD array according to claim 6, characterized in that, The first MOSFET is a PMOS, the third MOSFET is an NMOS, the second MOSFET is a PMOS, and the fourth MOSFET is an NMOS.

8. The data readout circuit of the SPAD array according to claim 1, characterized in that, When the first enable signal is high, the second enable signal is low, and the gating enable signal is high, the SA module does not work.

9. The data readout circuit of the SPAD array according to claim 2, characterized in that, When a SPAD module outputs 0 data, the BUS voltage drops and the SR latch outputs 0. When a SPAD module outputs a value of 1, the BUS voltage rises, and the SR latch outputs 1.

10. The data readout circuit of the SPAD array according to claim 1, characterized in that, The first MOSFET is the same as the second MOSFET.

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