A supercapacitor hardware protection circuit

Abstract

The utility model relates to super capacitor management technical field discloses a kind of super capacitor hardware protection circuit, including multiple super capacitor circuits and a dry contact point, multiple the parallel connection between the super capacitor circuit, and the chip U2 of the super capacitor circuit is all led out and is connected with dry contact point, the super capacitor circuit includes super capacitor monomer, chip U1, chip U2, MOS tube, light emitting diode LED, capacitor C1, triode Q1 and Q2, and resistance R1, R2, R3, R4, R5 and R6, the anode of the super capacitor monomer is connected to the Vin pin of chip U1, the Vout pin of the chip U1 is connected to MOS tube conduction pin on resistance R3. In the utility model, the protection circuit of super capacitor pack is formed by the series connection of multiple identical circuits, to avoid damage or safety hazard of super capacitor due to inconsistency of monomer, to ensure consistency of super capacitor pack monomer by this circuit, to avoid safety hazard caused by overcharge, to prolong the life of product.

Description

Technical Field

[0001] This utility model relates to the field of supercapacitor management technology, and in particular to a supercapacitor hardware protection circuit. Background Technology

[0002] When more than two supercapacitors are used, the precision deviations in the materials, manufacturing, assembly, and processes of the supercapacitors themselves will increase after multiple cycles of use. In addition, the attenuation differences during use will also affect the consistency of the supercapacitor pack.

[0003] If the voltage of one supercapacitor is mismatched with the voltages of the other individual cells, the capacity of the entire supercapacitor pack will be reduced. Capacity mismatch in supercapacitor packs includes: charging state-of-charge (SOC) mismatch, and capacity and energy mismatch. Therefore, it is necessary to reduce the voltage difference between the various supercapacitor packs to maintain consistency.

[0004] Therefore, those skilled in the art have provided a supercapacitor hardware protection circuit to solve the problems mentioned in the background art. Utility Model Content

[0005] The purpose of this invention is to address the shortcomings of existing technologies and provide a hardware protection circuit for supercapacitors. This circuit ensures the consistency of individual cells within the supercapacitor pack, avoids safety hazards caused by overcharging, and extends the product's lifespan.

[0006] To achieve the above objectives, this utility model provides a supercapacitor hardware protection circuit, including multiple supercapacitor circuits and a dry contact. The multiple supercapacitor circuits are connected in parallel, and the chip U2 of each supercapacitor circuit is led out and connected to the dry contact.

[0007] The supercapacitor circuit includes a supercapacitor cell, chip U1, chip U2, MOSFET, LED, capacitor C1, transistors Q1 and Q2, and resistors R1, R2, R3, R4, R5 and R6. The positive terminal of the supercapacitor cell is connected to the Vin pin of chip U1. The Vout pin of chip U1 is connected to the on pin of the MOSFET through resistor R3. The MOSFET is an N-channel enhancement type, and its output terminal is connected to the negative terminal of the supercapacitor cell. The positive terminal of the supercapacitor cell is connected to the DS pin of the MOSFET through resistor R1 and then to the negative terminal of the supercapacitor cell #1.

[0008] The positive terminal of the supercapacitor cell is connected to the C pin of transistor Q1, and the E pin of transistor Q1 is connected to the positive terminal of light-emitting diode LED through resistor R4. The negative terminal of light-emitting diode LED is connected to the negative terminal of supercapacitor cell.

[0009] The positive terminal of the supercapacitor cell is connected to pin 1 of chip U2 through resistor R2, and pin 2 of chip U2 is connected to pin C of transistor Q2. Pin E of transistor Q2 is connected to the negative terminal of the supercapacitor cell.

[0010] Furthermore, the Vout pin of the chip U1 is connected to the negative terminal of the supercapacitor cell through resistors R3 and R6.

[0011] Furthermore, the Vout pin of the chip U1 is connected to the conduction pin of the transistor Q1 through resistor R3.

[0012] Furthermore, the Vout pin of the chip U1 is connected to the conduction pin of the transistor Q2 through resistors R3 and R5.

[0013] Furthermore, the GND pin of the chip U1 is connected to the negative terminal of the supercapacitor cell.

[0014] Furthermore, the positive terminal of the supercapacitor cell is connected to a capacitor C1 at the front end of the chip U1, and the other end of the capacitor C1 is connected to the negative terminal of the supercapacitor cell.

[0015] Furthermore, pins 3 and 4 of the chip U2 in the multiple supercapacitor circuits are both connected, and pin 3 is connected to a dry contact.

[0016] Furthermore, the individual supercapacitors within the multiple supercapacitor circuits are interconnected.

[0017] This utility model has the following beneficial effects:

[0018] 1. This utility model proposes a hardware protection circuit for a supercapacitor. Based on the characteristics of the individual supercapacitor voltage, a maximum fixed voltage value is uniformly set for the individual voltages of the entire supercapacitor pack. When the individual voltage exceeds the set voltage, the protection circuit activates, and the monitoring circuit, through a passive dry contact, stops the external charging device from charging. Simultaneously, the equalization circuit is activated to consume the energy of the overvoltaged individual cells, reducing their voltage. When the voltage drops to a certain level, the equalization circuit stops, and the monitoring circuit returns to normal.

[0019] 2. The present invention proposes a hardware protection circuit for a supercapacitor, which forms a protection circuit for the supercapacitor pack by connecting multiple identical circuits in series. This circuit avoids damage or safety hazards to the supercapacitor due to inconsistency among individual cells. It ensures the consistency of the individual cells in the supercapacitor pack, avoids safety hazards caused by overcharging, and extends the product's lifespan. Attached Figure Description

[0020] Figure 1 This is a circuit connection diagram of a supercapacitor hardware protection circuit proposed in this utility model. Detailed Implementation

[0021] The present invention will now be further described with reference to the accompanying drawings.

[0022] like Figure 1 As shown, this utility model provides a specific embodiment:

[0023] A supercapacitor hardware protection circuit includes multiple supercapacitor circuits and a dry contact. The multiple supercapacitor circuits are connected in parallel, and the individual supercapacitors within the multiple supercapacitor circuits are interconnected. The chip U2 of each supercapacitor circuit is led out and connected to the dry contact.

[0024] The supercapacitor circuit includes a supercapacitor cell, chip U1, chip U2, MOSFET, LED, capacitor C1, transistors Q1 and Q2, and resistors R1, R2, R3, R4, R5 and R6. The positive terminal of the supercapacitor cell is connected to the Vin pin of chip U1. The Vout pin of chip U1 is connected to the on pin of the MOSFET through resistor R3. The MOSFET is an N-channel enhancement type, and its output terminal is connected to the negative terminal of the supercapacitor cell. The positive terminal of the supercapacitor cell is connected to the DS pin of the MOSFET through resistor R1 and then to the negative terminal of the supercapacitor cell #1.

[0025] The positive terminal of the supercapacitor cell is connected to the C pin of transistor Q1, and the E pin of transistor Q1 is connected to the positive terminal of light-emitting diode LED through resistor R4. The negative terminal of light-emitting diode LED is connected to the negative terminal of supercapacitor cell.

[0026] When the voltage of a single supercapacitor cell exceeds the set voltage of chip U1, the Vout pin of U1 outputs a high level, which drives the MOSFET through resistor R3. The MOSFET is an N-channel enhancement-mode MOSFET that conducts under high voltage. The positive terminal of the supercapacitor cell is connected to the negative terminal of the supercapacitor cell through power resistor R1 and the DS pin of the MOSFET, dissipating the energy of the supercapacitor cell. At the same time, the Vout pin of chip U1 outputs a high level, which turns on transistors Q1 and Q2. When transistor Q1 is turned on, the voltage of the positive terminal of the supercapacitor cell reaches the negative terminal of the supercapacitor cell through the C and E pins of transistor Q1, resistor R4, and LED, lighting up the LED for identification indication.

[0027] The positive terminal of the supercapacitor cell is connected to pin 1 of chip U2 through resistor R2, and pin 2 of chip U2 is connected to pin C of transistor Q2. The E terminal of transistor Q2 is connected to the negative terminal of the supercapacitor cell.

[0028] The positive voltage of the supercapacitor cell reaches the negative terminal of the supercapacitor cell through resistor R2, chip U2, and the pin of transistor Q2. When chip U2 is turned on, pins 3 and 4 are short-circuited, and the state of the dry contact changes from open to closed, controlling the external charging device to stop charging, protecting the supercapacitor and preventing overcharging.

[0029] The Vout pin of chip U1 is connected to the negative terminal of the supercapacitor cell through resistors R3 and R6. The Vout pin of chip U1 is connected to the on pin of transistor Q1 through resistor R3. The Vout pin of chip U1 is connected to the on pin of transistor Q2 through resistors R3 and R5. The GND pin of chip U1 is connected to the negative terminal of the supercapacitor cell. The positive terminal of the supercapacitor cell is connected to a capacitor C1 at the front end of chip U1, and the other end of capacitor C1 is connected to the negative terminal of the supercapacitor cell. Pins 3 and 4 of chip U2 in multiple supercapacitor circuits are all connected, and pin 3 is connected to a dry contact.

[0030] Working principle: When supercapacitor cell 1# is working, when the voltage of supercapacitor cell 1# exceeds the voltage set by chip U1, the Vout pin of chip U1 outputs a high level, which drives MOSFET M1 through resistor R3. MOSFET M1 is an N-channel enhancement type and conducts under high voltage. The positive terminal of supercapacitor cell 1# is connected to the negative terminal of supercapacitor cell 1# through power resistor R1 and the DS pin of MOSFET M1, dissipating the energy of supercapacitor cell 1#. At the same time, the Vout pin of chip U1 outputs a high level, which turns on transistors Q1 and Q2. After transistor Q1 is turned on, the positive voltage of supercapacitor cell 1# reaches the negative terminal of supercapacitor cell 1# through the C and E pins of transistor Q1, resistor R4, and LED1, lighting up the LED for identification indication.

[0031] The positive voltage of supercapacitor cell 1# reaches the negative terminal of supercapacitor cell 1# through resistor R2, chip U2, and transistor Q2. When chip U2 is turned on, pins 3 and 4 are short-circuited, and the state of the dry contact changes from open to closed, controlling the external charging device to stop charging, protecting the supercapacitor and preventing overcharging.

[0032] As the power resistor R1 consumes energy from supercapacitor cell #1, the voltage of supercapacitor cell #1 gradually decreases. When the voltage drops below a certain value, the Vout pin of chip U1 outputs a low level. The MOSFET M1 through resistor R3 changes from the on state to the off state. Therefore, the voltage cannot pass through resistor R1 and MOSFET M1 to the negative terminal of supercapacitor cell #1, stopping the discharge of supercapacitor cell #1. At the same time, resistors R3 and R5 disconnect the base terminals of transistors Q1 and Q2. The disconnection of transistor Q1 causes the LED to stop emitting light through resistor R4. The disconnection of transistor Q2 prevents the voltage from passing through resistor R2 and pins 1 and 2 of chip U2, causing pins 3 and 4 of the opto-MOSFET U2 chip to change from the closed state to the open state.

[0033] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A supercapacitor hardware protection circuit, comprising multiple supercapacitor circuits and a dry contact, characterized in that: Multiple supercapacitor circuits are connected in parallel, and the chip U2 of each supercapacitor circuit is led out and connected to a dry contact. The supercapacitor circuit includes a supercapacitor cell, chip U1, chip U2, MOSFET, LED, capacitor C1, transistors Q1 and Q2, and resistors R1, R2, R3, R4, R5 and R6. The positive terminal of the supercapacitor cell is connected to the Vin pin of chip U1. The Vout pin of chip U1 is connected to the on pin of the MOSFET through resistor R3. The MOSFET is an N-channel enhancement type, and its output terminal is connected to the negative terminal of the supercapacitor cell. The positive terminal of the supercapacitor cell is connected to the DS pin of the MOSFET through resistor R1 and then to the negative terminal of the supercapacitor cell #1. The positive terminal of the supercapacitor cell is connected to the C pin of transistor Q1, and the E pin of transistor Q1 is connected to the positive terminal of light-emitting diode LED through resistor R4. The negative terminal of light-emitting diode LED is connected to the negative terminal of supercapacitor cell. The positive terminal of the supercapacitor cell is connected to pin 1 of chip U2 through resistor R2, and pin 2 of chip U2 is connected to pin C of transistor Q2. Pin E of transistor Q2 is connected to the negative terminal of the supercapacitor cell.

2. The supercapacitor hardware protection circuit according to claim 1, characterized in that: The Vout pin of the chip U1 is connected to the negative terminal of the supercapacitor cell through resistors R3 and R6.

3. The supercapacitor hardware protection circuit according to claim 1, characterized in that: The Vout pin of the chip U1 is connected to the conduction pin of the transistor Q1 through resistor R3.

4. The supercapacitor hardware protection circuit according to claim 1, characterized in that: The Vout pin of the chip U1 is connected to the conduction pin of the transistor Q2 through resistors R3 and R5.

5. A supercapacitor hardware protection circuit according to claim 1, characterized in that: The GND pin of the chip U1 is connected to the negative terminal of the supercapacitor cell.

6. The supercapacitor hardware protection circuit according to claim 1, characterized in that: The positive terminal of the supercapacitor cell is connected to a capacitor C1 at the front end of the chip U1, and the other end of the capacitor C1 is connected to the negative terminal of the supercapacitor cell.

7. A supercapacitor hardware protection circuit according to claim 1, characterized in that: Pins 3 and 4 of the chip U2 in the multiple supercapacitor circuits are both connected, and pin 3 is connected to a dry contact.

8. A supercapacitor hardware protection circuit according to claim 1, characterized in that: The individual supercapacitors in the multiple supercapacitor circuits are all interconnected.

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