An AI chip packaging structure with high integration
By employing substrate stacking and thermal conductive layer design in the AI chip packaging structure, the problems of excessive substrate area and warpage risk are solved, achieving highly integrated chip packaging while maintaining chip computing power and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- AMQ INTELLIGENT TECH LTD
- Filing Date
- 2025-05-15
- Publication Date
- 2026-05-29
AI Technical Summary
In existing technologies, AI chip packaging structures suffer from problems such as excessively large substrate area, high risk of warping, and high cost, making it difficult to reduce substrate area and lower costs while ensuring chip computing power.
The AI chip packaging structure adopts a stacked arrangement. By stacking multiple substrates in the vertical direction and placing metal layers and heat-conducting layers between the substrates, electrical connection and heat dissipation are achieved. The space height is used to reduce the substrate area, avoid warping, and maintain the chip's computing power through the connection of multiple DRAM chips to the SOC chip.
It achieves the goal of maintaining chip computing power without increasing substrate area, while reducing costs, improving heat dissipation, and avoiding warping risks through substrate stacking structure.
Smart Images
Figure CN224306186U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor packaging, and in particular to a highly integrated AI chip packaging structure. Background Technology
[0002] With the development of AI, there are higher requirements for the signal transmission rate between chips, which necessitates shorter conduction distances between DRAM (Dynamic RAM) and SOC (System on a Chip) chips to improve chip computing power. Currently, there are two solutions to this requirement. One approach is to integrate the DRAM and SOC chips onto the same substrate to solve the problem of long communication paths between them. This solution requires multiple DRAM chips to be laid flat on the substrate, resulting in a large substrate area. This not only occupies a significant amount of space on the system-on-a-PCB but also introduces uncontrollable risks such as substrate warping.
[0003] Another approach is to use HBM chips for packaging. HBM is a high-bandwidth memory chip formed by stacking multiple DRAMs vertically together via TSVs (vertical electrical interconnects through the silicon substrate). This type of packaging is costly, difficult to manufacture, and faces trade barriers that make procurement challenging.
[0004] Therefore, there is a lack of packaging structures for AI chips on the market that can ensure the computing power of AI chips, reduce the area of the required substrate, be easy to process and have low cost, and reduce the occurrence of uncontrollable risks. Utility Model Content
[0005] This invention provides a highly integrated AI chip packaging structure, the purpose of which is to reduce the substrate area while ensuring chip computing power.
[0006] To achieve the above objectives, embodiments of this utility model provide a highly integrated AI chip packaging structure, comprising:
[0007] The first unit includes a first substrate, on which a SOC chip is electrically connected;
[0008] The second unit includes a second substrate and a metal layer. The second substrate is disposed above the first substrate, the via is located above the SOC chip, and the metal layer is disposed within the via.
[0009] A first thermally conductive layer is disposed between the metal layer and the SOC chip, the first substrate and the second substrate are electrically connected, and DRAM chips are electrically connected to the first substrate and the second substrate.
[0010] Preferably, one or more second units are provided. When there are two or more second units, several second units are stacked in the vertical direction, and a heat dissipation pad is provided between two adjacent second substrates. A second heat-conducting layer is provided between the heat dissipation pad and the metal layer on the two adjacent second substrates.
[0011] Preferably, the heat dissipation pad and the metal layer are provided with a plurality of through holes.
[0012] Preferably, the thickness of the metal layer is the same as the thickness of the second substrate.
[0013] Preferably, the metal layer is formed by electroplating copper or chemical copper plating.
[0014] Preferably, solder balls are used for electrical connection and mechanical support between the first substrate and the second substrate, and between two adjacent second substrates.
[0015] Preferably, the first thermally conductive layer and the second thermally conductive layer are formed of a thermal interface material.
[0016] The above-mentioned solution of this utility model has the following beneficial effects:
[0017] Compared to existing packaging methods for optimized AI chips, this application uses a stacked arrangement to achieve electrical connection between various substrates. On the one hand, this reduces the area of a single substrate, avoiding problems such as warping and low substrate production yield caused by excessively large substrate areas. On the other hand, arranging DRAM chips on different substrates can maintain the chip's computing power.
[0018] Furthermore, since the substrates are arranged in a stacked manner in this application, and the DRAM chips on the substrates will generate a lot of heat when they are working, in order to reduce the heat inside the chip, the internal heat is guided out through the metal layers on each second substrate, especially the heat generated by the SOC chip, thereby improving the heat dissipation effect.
[0019] Other features and advantages of this invention will be described in detail in the following detailed description section. Attached Figure Description
[0020] Figure 1 This is a cross-sectional view of the double-layer structure of this utility model;
[0021] Figure 2 This is a cross-sectional view of the three-layer structure of this utility model.
[0022] [Explanation of Labels in the Attached Image]
[0023] 10-First substrate, 11-SOC chip,
[0024] 20-Second substrate, 21-Metal layer, 22-First thermal conductive layer, 23-DRAM chip, 24-Via,
[0025] 30- Heat dissipation pad
[0026] 40-Second thermal conductive layer
[0027] 50-tin ball. Detailed Implementation
[0028] To make the technical problems, technical solutions and advantages of this utility model clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.
[0029] like Figure 1 and 2 As shown, an embodiment of this utility model provides a highly integrated AI chip packaging structure, including a first unit and a second unit. The first unit includes a first substrate 10, on which a SOC chip 11 is electrically connected. The second unit includes a second substrate 20, which is disposed above the first substrate 10. A through-hole is provided on the second substrate 20, extending through the second substrate 20 along its thickness direction and located directly above the SOC chip 11. A metal layer 21 is disposed within the through-hole, and the metal layer 21 and the area of the second substrate 20 excluding the through-hole constitute a complete substrate. A first thermally conductive layer 22 is also disposed between the metal layer 21 and the SOC chip 11, serving to connect the metal layer 21 and the SOC chip 11 for heat conduction. The first substrate 10 and the second substrate 20 are electrically connected. Multiple DRAM chips 23 are also disposed on the first substrate 10 and the second substrate 20, and are electrically connected to both substrates 10 and 20.
[0030] Compared to methods that increase computing power by increasing substrate area, this application makes full use of space height and stacks substrates to reduce the area of a single substrate, avoiding problems such as warping or low production yield caused by excessively large substrates. Simultaneously, multiple DRAM chips 23 can be mounted on vertically stacked substrates, ensuring chip computing power. More importantly, this application does not require costly HBM chips to connect multiple DRAM chips 23 to the SOC chip 11.
[0031] Preferably, in this application, the second unit can be provided as one or more as needed.
[0032] When there are two or more second units, the multiple second units are stacked vertically, and each second unit includes a second substrate 20 and a metal layer 21 located on the second substrate 20. A heat dissipation pad 30 is provided between the second substrates 20 of two adjacent second units. The upper and lower surfaces of the heat dissipation pad 30 are coated with a thermal interface material to form a second thermally conductive layer 40. The second thermally conductive layer 40 is used to connect the metal layers 21 on the two adjacent second substrates 20.
[0033] In this application, the metal layer 21 on the second substrate 20 is formed by electroplating copper or chemical copper plating, and the thickness of the formed metal layer 21 is the same as the thickness of the second substrate 20. Preferably, a via 24 is provided on the metal layer 21, extending along the thickness direction of the metal layer 21.
[0034] The SOC chip 11 is electrically connected to the first substrate 10, and a thermal interface material is coated on the upper end of the SOC chip 11 to form a first thermal conductive layer 22. The first thermal conductive layer 22 can not only guide the heat generated by the SOC chip 11 to the metal layer 21 and dissipate heat through the metal layer 21, but also protect the SOC chip 11.
[0035] Solder balls 50 are also disposed around the SOC chip 11. The solder balls 50 are used to connect the first substrate 10 and the second substrate 20, serving as electrical connections and mechanical supports. Solder balls 50 are also disposed below the first substrate 10 to facilitate the connection of the first substrate 10 with other devices.
[0036] Understandably, the first substrate 10 and the second substrate 20 can also be electrically connected and mechanically supported by copper pillars, such as growing copper pillars on the first substrate 10 and applying solder to the lower surface of the second substrate 20 at the position corresponding to the copper pillars to connect the copper pillars.
[0037] When there are two or more second units, adjacent second substrates 20 are electrically connected and mechanically supported by solder balls 50. The metal layers 21 between adjacent second units are connected by a second thermally conductive layer 40 to achieve heat dissipation.
[0038] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.
Claims
1. A highly integrated AI chip packaging structure, characterized in that, include: The first unit includes a first substrate (10), on which a SOC chip (11) is electrically connected; The second unit includes a second substrate (20) and a metal layer (21). The second substrate (20) is disposed above the first substrate (10). The via is located above the SOC chip (11). The metal layer (21) is disposed inside the via. A first thermally conductive layer (22) is provided between the metal layer (21) and the SOC chip (11), the first substrate (10) and the second substrate (20) are electrically connected, and DRAM chips (23) are electrically connected on the first substrate (10) and the second substrate (20).
2. The highly integrated AI chip packaging structure according to claim 1, characterized in that: The second unit is provided with one or more. When there are two or more second units, several second units are stacked in the vertical direction, and a heat dissipation pad (30) is provided between two adjacent second substrates (20). A second heat-conducting layer (40) is provided between the heat dissipation pad (30) and the metal layer (21) on the two adjacent second substrates (20).
3. The highly integrated AI chip packaging structure according to claim 2, characterized in that: The heat dissipation pad (30) and the metal layer (21) are provided with a plurality of through holes (24).
4. The highly integrated AI chip packaging structure according to claim 1, characterized in that: The thickness of the metal layer (21) is the same as the thickness of the second substrate (20).
5. The highly integrated AI chip packaging structure according to claim 4, characterized in that: The metal layer (21) is formed by electroplating copper or chemical copper plating.
6. The highly integrated AI chip packaging structure according to claim 2, characterized in that: The first substrate (10) and the second substrate (20), and the two adjacent second substrates (20) are electrically connected and mechanically supported by solder balls (50).
7. The highly integrated AI chip packaging structure according to claim 1, characterized in that: The first thermally conductive layer (22) and the second thermally conductive layer (40) are formed of a thermal interface material.