Semiconductor photonic device

Abstract

Various embodiments of this utility model relate to a semiconductor photonic device. A bus optical waveguide structure, an optical modulator structure, and a modulator heater structure are formed from semiconductor layers of the semiconductor photonic device, such that the bus optical waveguide structure, optical modulator structure, and modulator heater structure are continuous and physically connected. The physical connection between the optical modulator structure and the modulator heater structure provides a direct path for heat to be supplied from the modulator heater structure through the semiconductor layer to the optical modulator structure. An isolation region, which may include a doped region of the semiconductor layer, is included between the modulator heater structure and the bus optical waveguide structure and the optical modulator structure. The isolation region electrically isolates the modulator heater structure from the optical modulator structure. Therefore, the modulator heater structure and the optical modulator structure are physically connected and electrically isolated.

Description

Technical Field

[0001] This utility model relates to a semiconductor photonic device. Background Technology

[0002] Semiconductor photonic devices can be configured to enable high-speed and secure data transmission between integrated circuits and / or semiconductor dies using optical signals. The optical signals can be transmitted via a bus waveguide within the semiconductor photonic device. The bus waveguide confines the optical signal, reducing optical loss and improving propagation efficiency. Data can be encoded into optical signals by modulating the light into optical pulses using an optical modulator structure. These optical pulses are then transmitted to the bus waveguide for propagation to other areas of the semiconductor photonic device. Utility Model Content

[0003] This invention provides a semiconductor photonic device. The semiconductor photonic device includes a bus optical waveguide structure. The semiconductor photonic device also includes an optical modulator structure adjacent to a first side of the bus optical waveguide structure. The semiconductor photonic device further includes a modulator heater structure adjacent to a second side of the bus optical waveguide structure, with the second side opposite to the first side. The bus optical waveguide structure, the optical modulator structure, and the modulator heater structure are physically connected in the semiconductor layer of the semiconductor photonic device. The modulator heater structure includes an isolation region located between the heater section of the modulator heater structure and the bus optical waveguide structure.

[0004] Another embodiment of this utility model provides a semiconductor photonic device. The semiconductor photonic device includes a bus optical waveguide structure extending along a first direction within the device. The device also includes a closed-loop optical modulator structure adjacent to a first side of the bus optical waveguide structure. Furthermore, the device includes a modulator heater structure extending along the first direction and adjacent to a second side of the bus optical waveguide structure, with the second side opposite to the first side. The bus optical waveguide structure, the closed-loop optical modulator structure, and the modulator heater structure are arranged in the semiconductor photonic device in a second direction substantially perpendicular to the first direction. The bus optical waveguide structure and the modulator heater structure are physically connected by a first connecting segment between them. The bus optical waveguide structure and the closed-loop optical modulator structure are physically connected by a second connecting segment between them. The modulator heater structure includes an isolation region located between a heater segment and the first connecting segment.

[0005] Another aspect of this invention provides a method for forming a semiconductor photonic device. The method includes forming an optical modulator structure, a bus optical waveguide structure adjacent to the optical modulator structure, and a modulator heater structure adjacent to the bus optical waveguide structure in a semiconductor layer above a first dielectric layer of the semiconductor photonic device, wherein the optical modulator structure, the bus optical waveguide structure, and the modulator heater structure are physically connected in the semiconductor layer. The method further includes doping a first portion of the modulator heater structure with a first dopant type. The method further includes doping a second portion of the modulator heater structure located below the first portion with a second dopant type different from the first dopant type. The method further includes doping a third portion of the modulator heater structure located above the first portion with the first dopant type. The method further includes forming a second dielectric layer on the optical modulator structure, the bus optical waveguide structure, and the modulator heater structure.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figures 1A to 1D This is a diagram of an exemplary embodiment of the exemplary semiconductor photonic device described herein.

[0008] Figures 2A to 2T These are diagrams illustrating exemplary embodiments of the semiconductor photonic device (or a portion thereof) described herein.

[0009] Figure 3 This is a flowchart of an exemplary process related to the formation of the semiconductor photonic device described herein. Detailed Implementation

[0010] This utility model provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the utility model. These are, of course, merely examples and are not intended to be limiting. For instance, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for the purpose of brevity and clarity, and not to indicate any relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one component or feature and another shown in the figures. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0012] Photonic integrated circuits in semiconductor photonic devices may include bus waveguide structures and optical modulator structures. The bus waveguide structure and optical modulator structure may be included within one or more dielectric layers of the semiconductor photonic device. The resonant wavelength of the optical modulator structure may be sensitive to variations in the manufacturing process and operating temperature. To stabilize the resonant wavelength of the optical modulator structure, a modulator heater structure may be located near the optical modulator structure to provide heat. The heat provided by the modulator heater structure allows the operating temperature of the optical modulator structure to remain consistent throughout the operation of the semiconductor photonic device, thereby stabilizing the resonant wavelength of the optical modulator structure.

[0013] While some of the heat generated by the modulator heater structure is transferred to the optical modulator structure, the dielectric layer surrounding the modulator heater structure also absorbs heat generated by the modulator heater structure (e.g., heat that could otherwise be used to heat the optical modulator structure). This results in inefficient operation of the modulator heater structure because a larger amount of heat needs to be generated to compensate for the heat loss due to the heat absorbed by the dielectric layer, thereby increasing the power consumption of the semiconductor photonic device.

[0014] In some embodiments described herein, the semiconductor photonic device includes a bus optical waveguide structure and an optical modulator structure. Both the bus optical waveguide structure and the optical modulator structure are formed of semiconductor layers. A modulator heater structure is also formed of semiconductor layers, such that the bus optical waveguide structure, the optical modulator structure, and the modulator heater structure are continuous and physically connected. This physical connection between the optical modulator structure and the modulator heater structure provides a direct path for heat to be transferred from the modulator heater structure through the semiconductor layers to the optical modulator structure. This direct path, combined with the semiconductor layers providing greater thermal conductivity than the surrounding dielectric layers, enables the modulator heater structure to achieve high operating efficiency and maintain higher temperature uniformity during operation.

[0015] An isolation region, which may include a doped region of a semiconductor layer, may be included between the modulator heater structure and the bus optical waveguide structure and optical modulator structure. The isolation region electrically isolates the modulator heater structure from the bus optical waveguide structure and optical modulator structure. Therefore, the modulator heater structure and the optical modulator structure are physically connected but electrically isolated. This allows the modulator heater structure and the optical modulator structure to operate independently of each other, and prevents, reduces, and / or minimizes interference from the modulator heater structure on the operation of the optical modulator structure.

[0016] Figures 1A to 1D This is a diagram of an exemplary embodiment of the exemplary semiconductor photonic device 100 described herein. Figure 1A A top view of the semiconductor photonic device 100 is shown. Figure 1A As shown, the semiconductor photonic device 100 includes a photonic integrated circuit 102. The photonic integrated circuit 102 can be configured to perform high-speed and secure data transmission using optical signals between the integrated circuits and / or semiconductor dies of the semiconductor photonic device 100, and / or between the semiconductor photonic device 100 and another device external to the semiconductor photonic device 100. Therefore, the photonic integrated circuit 102 may include an optical modulator structure 104 and a bus optical waveguide structure 106 optically coupled to the optical modulator structure 104.

[0017] In the semiconductor photonic device 100, the optical modulator structure 104 and the bus optical waveguide structure 106 can be adjacent and / or side by side in the x direction so that optical signals can be coupled between the optical modulator structure 104 and the bus optical waveguide structure 106.

[0018] The bus optical waveguide structure 106 can extend in the y-direction along one side of the optical modulator structure 104. The bus optical waveguide structure 106 can confine the optical signal, which can reduce optical loss and improve the propagation efficiency of the optical signal. The bus optical waveguide structure 106 can include an elongated waveguide (including a planar waveguide), a ribbed waveguide, and / or another type of waveguide structure. An input optical signal can enter the bus optical waveguide structure 106 at a first end, and an output optical signal (e.g., a modulated optical signal) can be provided by the bus optical waveguide structure 106 at a second (opposite) end. In the coupling region laterally adjacent to the optical modulator structure 104, the optical signal can be coupled between the bus optical waveguide structure 106 and the optical modulator structure 104.

[0019] Optical modulator structure 104 includes a micro ring modulator (MRM) or another type of closed-loop modulator structure including a closed-loop optical waveguide structure 108. The closed-loop optical waveguide structure 108 is a continuous waveguide structure connected to itself without endpoints. The structure of optical modulator structure 104 differs from another type of modulator, such as a Mach-Zender modulator (MZM), which has endpoints corresponding to its input and output. Instead of optical signal propagation through the input and output of the MZM to couple to the MZM and from the MZM, the optical signal is coupled to the closed-loop optical waveguide structure 108 and from the closed-loop optical waveguide structure 108 via evanescent coupling. When the fading field of the optical signal propagating through the bus optical waveguide structure 106 extends to a portion of the closed-loop optical waveguide structure 108 adjacent to the bus optical waveguide structure 106, fading coupling occurs from the bus optical waveguide structure 106 and the closed-loop optical waveguide structure 108. Similarly, when the fading field of the optical signal propagating through the closed-loop optical waveguide structure 108 extends to a portion of the bus optical waveguide structure 106, fading coupling occurs from the closed-loop optical waveguide structure 108 to the bus optical waveguide structure 106.

[0020] The optical modulator structure 104 can serve as a resonance chamber and can modulate an input optical signal coupled from the bus optical waveguide structure 106 to generate a modulated optical signal coupled back to the bus optical waveguide structure 106. The optical modulator structure 104 includes a cathode 110 and an anode 112 located on opposite sides of the closed-loop optical waveguide structure 108. The cathode 110 can be included around and outside the closed-loop optical waveguide structure 108, and the anode 112 can be included around and inside the closed-loop optical waveguide structure 108. An electrical input (e.g., voltage, current) can be applied to the cathode 110 and / or the anode 112 to change the refractive index of the material of the closed-loop optical waveguide structure 108, allowing the input optical signal to be modulated within the closed-loop optical waveguide structure 108. The cathode 110 can be electrically and / or physically connected to one or more contacts 114, and the anode 112 can be electrically and / or physically connected to one or more contacts 116. Contacts 114 and 116 enable electrical input to be applied to cathode 110 and anode 112, respectively.

[0021] like Figure 1AAs further shown, the photonic integrated circuit 102 includes a modulator heater structure 118. The modulator heater structure 118 may be laterally and / or horizontally adjacent to the bus optical waveguide structure 106 in the x-direction, such that the bus optical waveguide structure 106 is located between the modulator heater structure 118 and the optical modulator structure 104. Therefore, the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118 are arranged in the x-direction such that the modulator heater structure 118 is adjacent to a first side of the bus optical waveguide structure 106 in the x-direction, and the optical modulator structure 104 is adjacent to a second side of the bus optical waveguide structure 106 opposite to the first side in the x-direction. The modulator heater structure 118 may extend in the y-direction along the side of the bus optical waveguide structure 106, substantially parallel to the bus optical waveguide structure 106.

[0022] The modulator heater structure 118 includes a heater section 120 and heater terminals 122a and 122b at opposite ends of the heater section 120 in the y-direction. The heater section 120 is configured to generate heat and provide that heat to the optical modulator structure 104. The heater section 120 can be configured to generate heat through resistive heating. For example, an electrical input (e.g., current, voltage) can be applied to heater terminals 122a and / or 122b, and the heater section 120 converts the electrical input from electrical energy to thermal energy (e.g., heat). The electrical input can be provided to heater terminals 122a and 122b via contacts 124.

[0023] The heater section 120 may extend in the y-direction such that opposite ends of the heater section 120 extend at least to opposite sides of the closed-loop optical waveguide structure 108 of the optical modulator structure 104, and are substantially aligned with opposite sides of the closed-loop optical waveguide structure 108. This allows the heater section 120 to distribute heat completely across the diameter of the closed-loop optical waveguide structure 108 of the optical modulator structure 104. In some embodiments, one or more ends of the heater section 120 extend beyond one or more sides of the closed-loop optical waveguide structure 108 in the y-direction.

[0024] The x-direction width of heater terminals 122a and 122b can be larger than the x-direction width of heater section 120. This improves the heating performance of heater section 120 because the electrical input path through heater section 120 between heater terminals 122a and 122b narrows, increasing the resistivity of heater section 120 and resulting in more heat being generated when the x-direction width of heater section 120 is approximately equal to or greater than the x-direction width of heater terminals 122a and 122b.

[0025] Figure 1B The semiconductor photonic device 100 is shown along... Figure 1AA cross-sectional view of line AA, which spans the section of the optical modulator structure 104 in the x-direction. (See image below.) Figure 1B As shown, in the semiconductor photonic device 100, a light modulator structure 104 may be formed and / or included in a semiconductor layer 126, which is located above the semiconductor substrate 128 and the first dielectric layer 130 in the z-direction. The semiconductor layer 126 may include layers of silicon (Si), germanium (Ge), and / or other semiconductor materials. The semiconductor substrate 128 may include the same semiconductor material as the semiconductor layer 126, or may include different semiconductor materials. The first dielectric layer 130 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials.

[0026] The second dielectric layer 132 may be included above the first dielectric layer 130, such that the optical modulator structure 104 is encapsulated by the first dielectric layer 130 and the second dielectric layer 132. The second dielectric layer 132 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials.

[0027] like Figure 1B As shown, the optical modulator structure 104 includes multiple segments in the semiconductor layer 126, including a cathode 110, an anode 112, and a closed-loop optical waveguide structure 108. The closed-loop optical waveguide structure 108 may be located between the cathode 110 and the anode 112, and may be electrically and / or physically connected to the cathode 110 and the anode 112 via connector segments 134 and 136, respectively.

[0028] The semiconductor layer 126 in the optical modulator structure 104 can have different z-direction thicknesses. For example, the z-direction thickness of the semiconductor layer 126 in the cathode 110 and anode 112 can be greater than the z-direction thickness of the semiconductor layer 126 in the connector sections 134 and 136. As another example, the z-direction thickness of the semiconductor layer 126 in the closed-loop optical waveguide structure 108 can be greater than the z-direction thickness of the semiconductor layer 126 in the connector sections 134 and 136. The connector sections 134 and 136 allow an electrical input to be applied to the closed-loop optical waveguide structure 108 to change the refractive index in the closed-loop optical waveguide structure 108, thereby modulating the input optical signal.

[0029] like Figure 1B As further shown, multiple regions of the semiconductor layer 126 can be doped to form PN junctions (p-type / n-type junctions) or PIN junctions (p-type / intrinsic / n-type junctions) in the closed-loop optical waveguide structure 108. When an electrical input is applied to the cathode 110 and the anode 112, the PN junctions (or PIN junctions) create an electric field in the closed-loop optical waveguide structure 108, and the electric field changes the refractive index of the closed-loop optical waveguide structure 108.

[0030] Multiple regions of semiconductor layer 126 include doped regions 138 and 140 included in the closed-loop optical waveguide structure 108. A portion of doped region 138 is also included in connector section 134, and a portion of doped region 140 is also included in connector section 136. Multiple regions of semiconductor layer 126 may also include doped regions 142, 144, and 146 included in cathode 110. A portion of doped region 142 may also be included in connector section 134. Multiple regions of semiconductor layer 126 may also include doped regions 148, 150, and 152 included in anode 112. A portion of doped region 148 may also be included in connector section 136.

[0031] In some embodiments, doped regions 138, 142, 144, and 146 include n-type doped regions (e.g., regions of semiconductor layer 126 doped with one or more n-type dopants). n-type dopants may include phosphorus (P), arsenic (As), and / or antimony (Sb), etc. In some embodiments, doped regions 140, 148, 150, and 152 include p-type doped regions (e.g., regions of semiconductor layer 126 doped with one or more p-type dopants). p-type dopants may include boron (B), aluminum (Al), and / or gallium (Ga), etc. Alternatively, doped regions 138, 142, 144, and 146 include p-type doped regions, and doped regions 140, 148, 150, and 152 include n-type doped regions.

[0032] Doped region 142 may have a higher dopant concentration than doped region 138 to facilitate current flow from cathode 110 to closed-loop optical waveguide structure 108, to achieve low optical loss in closed-loop optical waveguide structure 108, and / or to achieve high modulation efficiency in closed-loop optical waveguide structure 108, etc. In some embodiments, the dopant concentration in doped region 138 is approximately 5 × 10⁻⁶. 13 Atoms per cubic centimeter to approximately 5 × 10⁻⁶ 14 Within the atomic / cubic centimeter range, the dopant concentration in doped region 142 is approximately 1 × 10⁻⁶. 14 Atoms per cubic centimeter to approximately 1 × 10⁻⁶ 15 Within the range of atoms / cubic centimeters. However, other values ​​and / or ranges of dopant concentration for doped regions 138 and 142 are also within the scope of this disclosure.

[0033] Doped region 146 may have a higher dopant concentration than doped region 144 to achieve low contact resistance of cathode 110, low optical loss of closed-loop optical waveguide structure 108, and / or high modulation efficiency of closed-loop optical waveguide structure 108, etc. In some embodiments, the dopant concentration in doped region 144 is approximately 5 × 10⁻⁶. 13 Atoms per cubic centimeter to approximately 5 × 10⁻⁶ 14 Within the atomic / cubic centimeter range, the dopant concentration in doped region 146 is approximately 1 × 10⁻⁶. 15 Atoms per cubic centimeter to approximately 5 × 10⁻⁶ 15 Within the range of atoms / cubic centimeters. However, other values ​​and / or ranges of dopant concentration for doped regions 144 and 146 are also within the scope of this disclosure.

[0034] The doped region 148 may have a higher dopant concentration than the doped region 140 to facilitate current flow from the anode 112 to the closed-loop optical waveguide structure 108, to achieve low optical loss in the closed-loop optical waveguide structure 108, and / or to achieve high modulation efficiency in the closed-loop optical waveguide structure 108, etc. In some embodiments, the dopant concentration in the doped region 140 is approximately 5 × 10⁻⁶. 13 Atoms per cubic centimeter to approximately 5 × 10⁻⁶ 14 Within the atomic / cubic centimeter range, the dopant concentration in doped region 148 is approximately 1 × 10⁻⁶. 14 Atoms per cubic centimeter to approximately 1 × 10⁻⁶ 15 Within the atomic / cubic centimeter range. However, other values ​​and / or ranges of dopant concentration for doped regions 140 and 148 are also within the scope of this disclosure.

[0035] Doped region 152 may have a higher dopant concentration than doped region 150 to achieve low contact resistance of anode 112, low optical loss of closed-loop optical waveguide structure 108, and / or high modulation efficiency of closed-loop optical waveguide structure 108, etc. In some embodiments, the dopant concentration in doped region 150 is approximately 5 × 10⁻⁶. 13 Atoms per cubic centimeter to approximately 5 × 10⁻⁶ 14 Within the atomic / cubic centimeter range, the dopant concentration in doped region 152 is approximately 1 × 10⁻⁶. 15 Atoms per cubic centimeter to approximately 5 × 10⁻⁶ 15 Within the range of atoms / cubic centimeters. However, other values ​​and / or ranges of dopant concentration for doped regions 150 and 152 are also within the scope of this disclosure.

[0036] like Figure 1B As further shown, silicide layer 154 may be included on and / or on doped region 146 of cathode 110, and / or silicide layer 156 may be included on and / or on doped region 152 of anode 112. Silicide layer 154 and silicide layer 156 may each include a metal silicide layer, such as titanium silicide and / or another type of metal silicide. Silicide layer 154 may be included to achieve sufficiently low contact resistance between doped region 146 of cathode 110 and contact 114 electrically coupled to cathode 110. Silicide layer 156 may be included to achieve sufficiently low contact resistance between doped region 152 of anode 112 and contact 116 electrically coupled to anode 112.

[0037] Contacts 114 and 116 may each be included in and extend through the second dielectric layer 132. Contact 114 may extend between the silicide layer 154 and the metallization layer 158 above the optical modulator structure 104, and may be electrically and / or physically connected to the silicide layer 154 and the metallization layer 158. Contact 116 may extend between the silicide layer 156 and the metallization layer 160 above the optical modulator structure 104, and may be electrically and / or physically connected to the silicide layer 156 and the metallization layer 160.

[0038] Contacts 114 and 116, and metallization layers 158 and 160, may each comprise conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au). Contacts 114 and 116 may each comprise through-holes, trenches, contact plugs, and / or other types of conductive structures. Metallization layers 158 and 160 may each comprise through-holes, trenches, contact plugs, and / or other types of metallization layers.

[0039] Figure 1CThe semiconductor photonic device 100 is shown along... Figure 1A Another cross-sectional view of line BB, which in the x-direction spans the segment of optical modulator structure 104, the segment of bus optical waveguide structure 106, and the segment of heater segment 120 spanning modulator heater structure 118. (See image below.) Figure 1C As shown, the closed-loop optical waveguide structure 108, the bus optical waveguide structure 106, and the heater section 120 of the modulator heater structure 118 of the optical modulator structure 104 are formed together and / or included in the semiconductor layer 126. Therefore, the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118 are physically connected together in the semiconductor layer 126. The bus optical waveguide structure 106 and the modulator heater structure 118 are connected via connector sections 162 of the semiconductor layer 126, and the optical modulator structure 104 and the bus optical waveguide structure 106 are connected via connector sections 164 of the semiconductor layer 126. The z-direction thickness of the semiconductor layer 126 in the bus optical waveguide structure 106, the closed-loop optical waveguide structure 108, and the heater section 120 of the modulator heater structure 118 can be greater than the z-direction thickness of the semiconductor layer 126 in connector sections 162 and 164.

[0040] Heat can be supplied from the heater section 120 of the modulator heater structure 118 to the optical modulator structure 104 via connector sections 162 and 164. In other words, heat can be supplied directly from the heater section 120 of the modulator heater structure 118 to the optical modulator structure 104 through the semiconductor layer 126, instead of through an intermediate dielectric layer (e.g., the first dielectric layer 130 and / or the second dielectric layer 132). This allows the thermal efficiency of the modulator heater structure 118 in supplying heat to the optical modulator structure 104 to be greater than that of supplying heat through the dielectric layer, because the semiconductor material of the semiconductor layer 126 has a higher thermal conductivity.

[0041] In the cross-sectional view along line BB, the closed-loop optical waveguide structure 108 segment and the bus optical waveguide structure 106 segment of the optical modulator structure 104 may include undoped regions 166 of the semiconductor layer 126. At least a portion of the connector segment 164 between the bus optical waveguide structure 106 and the closed-loop optical waveguide structure 108, and the connector segment 162 between the bus optical waveguide structure 106 and the heater segment 120 of the modulator heater structure 118, may each include undoped regions 166 of the semiconductor layer 126.

[0042] An isolation region 168 is included in a semiconductor layer 126 between the heater section 120 of the modulator heater structure 118 and the closed-loop optical waveguide structure 108 of the bus optical waveguide structure 106 and the optical modulator structure 104. The isolation region 168 includes doped regions of the semiconductor layer 126 with a different dopant type than the doped regions 170 and 172 of the semiconductor layer 126 included in the modulator heater structure 118. For example, the isolation region 168 may be doped with an n-type dopant, while the doped regions 170 and 172 may be doped with a p-type dopant. As another example, the isolation region 168 may be doped with a p-type dopant, while the doped regions 170 and 172 may be doped with an n-type dopant. This forms a PN junction between the isolation region 168 and the doped regions 170 and 172. The PN junction acts as a diode between the heater section 120 of the modulator heater structure 118 and the closed-loop waveguide modulator structure 108 of the bus optical waveguide structure 106 and the optical modulator structure 104. The PN junction prevents, minimizes, and / or reduces current flow between the heater section 120 of the modulator heater structure 118 and the closed-loop waveguide modulator structure 108 of the bus optical waveguide structure 106 and the optical modulator structure 104. Therefore, the isolation region 168 electrically isolates the heater section 120 of the modulator heater structure 118 from the closed-loop waveguide modulator structure 108 of the bus optical waveguide structure 106 and the optical modulator structure 104.

[0043] The doped regions 170 and 172 of the modulator heater structure 118 may be included above the isolation region 168 in the z-direction, such that the doped regions 170 and 172 and the isolation region 168 are vertically arranged in the modulator heater structure 118. In some embodiments, the isolation region 168 has a width of approximately 5 × 10⁻⁶ m / s. 13 Atoms per cubic centimeter to approximately 5 × 10⁻⁶ 14 The dopant concentration is within the atomic / cubic centimeter range to provide sufficient electrical isolation between the heater section 120 of the modulator heater structure 118 and the closed-loop waveguide modulator structure 108 of the bus optical waveguide structure 106 and the optical modulator structure 104. However, other values ​​and / or ranges of dopant concentration in the isolation region 168 are also within the scope of this disclosure. The doped region 172 may have a higher dopant concentration than the doped region 170 to achieve a low contact resistance in the modulator heater structure 118. In some embodiments, the dopant concentration in the doped region 170 is approximately 5 × 10⁻⁶. 13 Atoms per cubic centimeter to approximately 5 × 10⁻⁶ 14 Within the atomic / cubic centimeter range, the dopant concentration in doped region 172 is approximately 1 × 10⁻⁶. 15 Atoms per cubic centimeter to approximately 5 × 10⁻⁶ 15 Within the range of atoms / cubic centimeters. However, other values ​​and / or ranges of dopant concentration for doped regions 170 and 172 are also within the scope of this disclosure.

[0044] like Figure 1C As further shown, silicide layer 174 may be included on and / or on doped region 172 of modulator heater structure 118. Silicide layer 174 and silicide layer 156 may each include a metal silicide layer, such as titanium silicide and / or another type of metal silicide. Silicide layer 174 may be included to achieve sufficiently low contact resistance of modulator heater structure 118.

[0045] Figure 1D The semiconductor photonic device 100 is shown along... Figure 1A Another cross-sectional view of line CC, which is along the modulator heater structure 118 in the y-direction. (See figure) Figure 1C As shown, a group of contacts 124 may be included at opposite ends of the modulator heater structure 118. For example, one or more first contacts 124 may be electrically and / or physically connected to heater terminal 122a at a first end of heater section 120, and one or more second contacts 124 may be electrically and / or physically connected to heater terminal 122b at a second end of heater section 120.

[0046] Contacts 124 may each be included in and extend through the second dielectric layer 132. Contacts 124 may extend between the silicide layer 174 and the metallization layer 176 above the modulator heater structure 118, and may be electrically and / or physically connected to the silicide layer 174 and the metallization layer 176. Contacts 124 and the metallization layer 176 may each comprise examples of conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au). Contacts 124 may each include vias, trenches, contact plugs, and / or other types of conductive structures. The metallization layer 176 may each include vias, trenches, contact plugs, and / or other types of metallization layers.

[0047] As mentioned above, providing Figures 1A to 1D As an example. Other examples can be found in relation to... Figures 1A to 1D The descriptions are different.

[0048] Figures 2A to 2T This is a diagram of an exemplary embodiment 200 forming the semiconductor photonic device 100 (or a portion thereof) described herein. In some embodiments, one or more of the semiconductor processing operations described in connection with exemplary embodiment 200 may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, and / or wafer / die transport tools, etc. Figures 2A to 2T One or more of them are from the semiconductor photonic device 100 along Figure 1A The cross-sectional views of lines AA, BB, and / or CC are shown.

[0049] come Figure 2A and Figure 2B A substrate 202 may be provided. The substrate 202 may include a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor substrate 128 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate), a first dielectric layer 130 (e.g., a buried oxide or bottom oxide (BOX) layer and / or another type of insulating layer) on and / or on the semiconductor substrate 128, and a semiconductor layer 126 (e.g., a silicon (Si) layer and / or another type of semiconductor layer) on and / or on the first dielectric layer 130.

[0050] Alternatively, the semiconductor substrate 128 can be provided as a semiconductor wafer, and a first dielectric layer 130 can be formed on and / or on the semiconductor substrate 128 using deposition tools, and a semiconductor layer 126 can be formed on and / or on the first dielectric layer 130. The first dielectric layer 130 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), oxidation techniques (e.g., thermal oxidation), and / or another type of deposition technique. The first semiconductor layer 126 can be formed using CVD, PVD, epitaxial, and / or another type of deposition technique.

[0051] like Figure 2C and Figure 2DAs shown, certain portions of semiconductor layer 126 are removed to form the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118 from semiconductor layer 126. Specifically, the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118 are formed in semiconductor layer 126, such that the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118 are physically connected in semiconductor layer 126. The modulator heater structure 118 can be physically connected to the bus optical waveguide structure 106 via connector segments 162 of semiconductor layer 126. The modulator heater structure 118 can be physically connected to the bus optical waveguide structure 106 and the optical modulator structure 104 via connector segments 162 and 164 of semiconductor layer 126. The closed-loop waveguide modulator structure 108 of the optical modulator structure 104 can be physically connected to the cathode 110 and anode 112 of the optical modulator structure 104 through connecting sections 134 and 136, respectively.

[0052] In some embodiments, a pattern in a hard mask layer is used to etch the semiconductor layer 126 to form the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118. Deposition tools can be used to form the hard mask layer on the semiconductor layer 126 (e.g., using CVD, PVD, atomic layer deposition (ALD), oxidation, and / or another type of deposition technique), and a photoresist layer can be formed on the hard mask layer (e.g., using spin coating and / or another type of deposition technique). Exposure tools can be used to expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. Developing tools can develop and remove portions of the photoresist layer to expose the pattern.

[0053] An etching tool can be used to etch the hard mask layer to transfer the pattern from the photoresist layer to the hard mask layer. The etching tool can be used to etch the semiconductor layer 126 based on the pattern in the hard mask layer to form the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118 by removing portions of the semiconductor layer 126 based on the pattern. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool is used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a planarization tool is used to remove the remaining portions of the hard mask layer using chemical mechanical planarization (CMP) techniques and / or another type of planarization technique.

[0054] like Figure 2E and Figure 2F As shown, a first portion of the second dielectric layer 132 can be deposited around the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118. This first portion of the second dielectric layer 132 can be referred to as a shallow trench isolation (STI) region of the second dielectric layer 132. The first portion of the second dielectric layer 132 can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or another type of deposition technique. In some embodiments, an STI pad is first deposited onto the semiconductor layer 126, and then the first portion of the second dielectric layer 132 is deposited onto the STI pad.

[0055] like Figure 2E and Figure 2F As further shown, a planarization tool can be used to perform CMP operations and / or another type of planarization operation to planarize the first portion of the second dielectric layer 132. This makes the top surface of the first portion of the second dielectric layer 132 approximately coplanar with the top surface of the optical modulator structure 104 (e.g., closed-loop optical waveguide structure 108, cathode 110, and anode 112), the bus optical waveguide structure 106, and / or the modulator heater structure 118.

[0056] like Figures 2G to 2N As shown, multiple regions of semiconductor layer 126 can be doped with one or more types of dopants. These multiple regions of semiconductor layer 126 can be doped by ion implantation (e.g., using an ion implantation tool), by diffusion (e.g., using a diffusion tool), and / or by another type of doping operation.

[0057] like Figure 2G As shown, a portion of the semiconductor layer 126 can be doped with a first dopant type to form a doped region 148 of the anode 112. A portion of the doped region 148 may also be included in the connector segment 136 of the semiconductor layer 126.

[0058] like Figure 2H As shown, a portion of semiconductor layer 126 can be doped with a second dopant type (e.g., different from the first dopant type) to form a doped region 142 of cathode 110. A portion of doped region 142 may also be included in the interconnect segment 134 of semiconductor layer 126. In some embodiments, the first dopant type includes one or more p-type dopants, and the second dopant type includes one or more n-type dopants. In some embodiments, the first dopant type includes one or more n-type dopants, and the second dopant type includes one or more p-type dopants.

[0059] like Figure 2IAs shown, a portion of semiconductor layer 126 can be doped with a first dopant type to form a doped region 140 of closed-loop waveguide modulator structure 108. Doped region 140 can be formed laterally adjacent to doped region 148. A portion of doped region 140 can also be included in the connector segment 136 of semiconductor layer 126. Figure 2I As further shown, a portion of the semiconductor layer 126 can be doped with a first dopant type to form a doped region 150 of the anode 112. The doped region 150 can be formed over the doped region 148.

[0060] like Figure 2J As shown, a portion of the semiconductor layer 126 can be doped with a first dopant type to form a doped region 170 of the modulator heater structure 118. The doped region 170 may be adjacent to the undoped region 166 of the semiconductor layer 126 included in the bus optical waveguide structure 106, the closed-loop waveguide modulator structure 108, the connector section 162, and the connector section 164.

[0061] like Figure 2K As shown, a portion of semiconductor layer 126 can be doped with a second dopant type to form a doped region 138 of the closed-loop waveguide modulator structure 108. The doped region 138 can be formed laterally adjacent to the doped region 142. A portion of the doped region 138 can also be included in the connector segment 134 of semiconductor layer 126. Figure 2K As further shown, a portion of the semiconductor layer 126 can be doped with a second type of dopant to form a doped region 144 of the cathode 110. The doped region 144 can be formed over the doped region 142.

[0062] like Figure 2L As shown, a portion of the semiconductor layer 126 can be doped with a second dopant type to form an isolation region 168 of the modulator heater structure 118. The isolation region 168 may be located below and / or beneath the doped region 170 of the modulator heater structure 118. Furthermore, the isolation region 168 may be adjacent to the undoped region 166 of the semiconductor layer 126 included in the bus optical waveguide structure 106, the closed-loop waveguide modulator structure 108, the connector section 162, and the connector section 164.

[0063] like Figure 2M As shown, a portion of the semiconductor layer 126 can be doped with a first dopant type to form a doped region 152 of the anode 112. The doped region 152 can be formed above the doped region 150. Figure 2M As further shown, a portion of the semiconductor layer 126 can be doped with a second type of dopant to form a doped region 146 of the cathode 110. The doped region 146 can be formed over the doped region 144.

[0064] like Figure 2N As shown, a portion of the semiconductor layer 126 can be doped with a first dopant type to form a doped region 172 of the modulator heater structure 118. The doped region 172 can be formed above the doped region 170.

[0065] like Figure 2O and 2P As shown, silicide layer 156 can be formed on and / or on doped region 152 of anode 112, silicide layer 154 can be formed on and / or on doped region 146 of cathode 110, and silicide layer 174 can be formed on and / or on doped region 172 of modulator heater structure 118. Silicate layers 154, 156, and 174 can be deposited using deposition tools employing CVD, PVD, ALD, and / or another deposition technique. In some embodiments, forming silicide layers 154, 156, and 174 may include depositing a metal layer on each of doped regions 146, 152, and 172, and annealing the metal layer to mix it with the semiconductor material of doped regions 146, 152, and 172, thereby forming silicide layers 154, 156, and 174.

[0066] like Figure 2Q and Figure 2R As shown, a second portion of the second dielectric layer 132 can be deposited on the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118, such that the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118 are encapsulated within the first dielectric layer 130 and the second dielectric layer 132. The second portion of the second dielectric layer 132 can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or another type of deposition technique. In some embodiments, planarization tools can be used to perform CMP operations and / or another type of planarization operations to planarize the second portion of the second dielectric layer 132.

[0067] like Figure 2Q As further shown, contact 114 can be formed on cathode 110 such that contact 114 is substantially connected to silicide layer 154 of cathode 110. Similarly, contact 116 can be formed on anode 112 such that contact 116 is substantially connected to silicide layer 156 of anode 112.

[0068] To form contacts 114 and 116, grooves can be formed in a second dielectric layer 132 above the cathode 110 and the anode 112. In some embodiments, the second dielectric layer 132 is etched using a pattern in a photoresist layer to form the grooves. In these embodiments, a deposition tool can be used to form the photoresist layer on the second dielectric layer 132. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the second dielectric layer 132 based on the pattern to form the grooves in the second dielectric layer 132. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to etching the second dielectric layer 132 based on the pattern.

[0069] Material for contacts 114 and 116 can be deposited in the grooves using deposition tools employing CVD, PVD, ALD, electroplating, another deposition technique described above in conjunction with Figure 1, and / or another suitable deposition technique. The material for contacts 114 and 116 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and then the material for contacts 114 and 116 is deposited on the seed layer. In some embodiments, after depositing contacts 114 and 116, a planarization tool can be used to planarize contacts 114 and 116.

[0070] like Figure 2RAs further shown, contacts 124 can be formed on heater terminals 122a and 122b of the modulator heater structure 118, such that contacts 124 are physically connected to the silicide layer 174 over heater terminals 122a and 122b. To form contacts 124, grooves can be formed in a second dielectric layer 132 over heater terminals 122a and 122b. In some embodiments, the second dielectric layer 132 is etched using a pattern in a photoresist layer to form the grooves. In these embodiments, a photoresist layer can be formed on the second dielectric layer 132 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the second dielectric layer 132 based on the pattern to form the grooves in the second dielectric layer 132. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the second dielectric layer 132.

[0071] Material for the contact 124 can be deposited in the groove using deposition tools employing CVD, PVD, ALD, electroplating, another deposition technique described above in conjunction with Figure 1, and / or another suitable deposition technique. The material for the contact 124 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and then the material for the contact 124 is deposited on the seed layer. In some embodiments, after depositing the contact 124, a planarization tool can be used to planarize the contact 124.

[0072] like Figure 2S and Figure 2T As shown, a third portion of the second dielectric layer 132 can be deposited on the second portion of the second dielectric layer 132 and on contacts 114, 116, and 124. The third portion of the second dielectric layer 132 can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation) and / or another type of deposition technique. In some embodiments, after the third portion of the second dielectric layer 132 is formed, a planarization tool can be used to perform a CMP operation and / or another type of planarization operation to planarize the second dielectric layer 132.

[0073] like Figure 2SAs further shown, a metallization layer 158 may be formed on the contact 114, such that the metallization layer 158 is physically connected to the contact 114. Similarly, a metallization layer 160 may be formed on the contact 116, such that the metallization layer 160 is physically connected to the contact 116.

[0074] To form metallization layers 158 and 160, grooves can be formed in the second dielectric layer 132 above contacts 114 and 116. In some embodiments, the second dielectric layer 132 is etched using a pattern in a photoresist layer to form the grooves. In these embodiments, a deposition tool can be used to form the photoresist layer on the second dielectric layer 132. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the second dielectric layer 132 based on the pattern to form the grooves in the second dielectric layer 132. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative to etching the second dielectric layer 132 based on the pattern.

[0075] The materials for metallization layers 158 and 160 can be deposited in the grooves using deposition tools employing CVD, PVD, ALD, electroplating, another deposition technique described above in conjunction with Figure 1, and / or another suitable deposition technique. The materials for metallization layers 158 and 160 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the materials for metallization layers 158 and 160 are deposited on the seed layer. In some embodiments, after depositing metallization layers 158 and 160, planarization tools can be used to planarize the metallization layers 158 and 160.

[0076] like Figure 2TAs further shown, a metallization layer 176 can be formed on the contact 124, such that the metallization layer 176 is physically connected to the contact 124. To form the metallization layer 176, a groove can be formed in the second dielectric layer 132 above the contact 124. In some embodiments, the second dielectric layer 132 is etched using a pattern in a photoresist layer to form the groove. In these embodiments, a photoresist layer can be formed on the second dielectric layer 132 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the second dielectric layer 132 based on the pattern to form the groove in the second dielectric layer 132. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the second dielectric layer 132.

[0077] The material of the metallization layer 176 can be deposited in the groove using deposition tools employing CVD, PVD, ALD, electroplating, another deposition technique described above in conjunction with Figure 1, and / or another suitable deposition technique. The material of the metallization layer 176 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the material of the metallization layer 176 is deposited on the seed layer. In some embodiments, after depositing the metallization layer 176, a planarization tool can be used to planarize the metallization layer 176.

[0078] As mentioned above, providing Figures 2A to 2T As an example. Other examples can be found related to... Figures 2A to 2T The descriptions are different.

[0079] Figure 3 This is a flowchart of an exemplary process 300 related to the formation of the semiconductor photonic device described herein. In some embodiments, Figure 3 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or another type of semiconductor processing tool.

[0080] like Figure 3As shown, process 300 may include forming an optical modulator structure, a bus optical waveguide structure adjacent to the optical modulator structure, and a modulator heater structure adjacent to the bus optical waveguide structure in a semiconductor layer above the first dielectric layer of the semiconductor photonic device (block 310). For example, an optical modulator structure 104, a bus optical waveguide structure 106 adjacent to the optical modulator structure 104, and a modulator heater structure 118 adjacent to the bus optical waveguide structure 106 can be formed in a semiconductor layer 126 above the first dielectric layer 130 of the semiconductor photonic device 100 using one or more semiconductor processing tools, as described herein. In some embodiments, the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118 are physically connected in the semiconductor layer 126.

[0081] like Figure 3 As further shown, process 300 may include doping a first portion (block 320) of the modulator heater structure with a first dopant type. For example, one or more semiconductor processing tools may be used to dope a first portion (e.g., doped region 170) of the modulator heater structure 118 with a first dopant type, as described herein.

[0082] like Figure 3 As further illustrated, process 300 may include doping a second portion of the modulator heater structure below the first portion with a second dopant type different from the first dopant type (block 330). For example, one or more semiconductor processing tools may be used to dope the second portion (e.g., isolation region 168) of the modulator heater structure 118 below the first portion with a second dopant type different from the first dopant type, as described herein.

[0083] like Figure 3 As further shown, process 300 may include a third portion (block 340) of the modulator heater structure above the first portion, doped with a first dopant type. For example, one or more semiconductor processing tools may be used to dope the third portion (e.g., doped region 172) of the modulator heater structure 118 above the first portion with a first dopant type, as described herein.

[0084] like Figure 3 As further shown, process 300 may include forming a second dielectric layer over the optical modulator structure, the bus optical waveguide structure, and the modulator heater structure (block 350). For example, a second dielectric layer 132 may be formed over the optical modulator structure 104, the bus optical waveguide structure 106, and the modulator heater structure 118 using one or more semiconductor processing tools, as described herein.

[0085] Process 300 may include other implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0086] In a first embodiment, process 300 includes forming a silicide layer 174 on a third portion of a modulator heater structure 118, wherein forming a second dielectric layer 132 includes forming a first portion of the second dielectric layer 132 before forming the silicide layer 174, such that the top surface of the first portion of the second dielectric layer 132 is substantially coplanar with the top surface of the modulator heater structure 118, and forming a second portion of the second dielectric layer 132 after forming the silicide layer 174.

[0087] In the second embodiment, forming the second dielectric layer 132, alone or in combination with the first embodiment, includes forming a first portion of the second dielectric layer 132 before a first portion of the doped modulator heater structure 118, and forming a second portion of the second dielectric layer 132 after a third portion of the doped modulator heater structure 118.

[0088] In the third embodiment, the bus optical waveguide structure 106 is located between the optical modulator structure 104 and the modulator heater structure 118 in the semiconductor layer 126, either alone or in combination with one or more of the first and second embodiments.

[0089] In the fourth embodiment, forming the modulator heater structure 118, alone or in combination with one or more of the first to third embodiments, includes forming the modulator heater structure 118 such that the modulator heater structure 118 is located outside the periphery of the optical modulator structure 104.

[0090] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the concentration of the first dopant of the first dopant type in the first portion of the modulator heater structure 118 is lower than the concentration of the second dopant of the first dopant type in the third portion of the modulator heater structure 118.

[0091] although Figure 3 An exemplary block diagram of process 300 is shown, but in some embodiments, process 300 includes... Figure 3 The blocks depicted in the diagram may be additional, fewer, different, or arranged differently. Additionally, or alternatively, two or more blocks in process 300 may be executed in parallel.

[0092] In this manner, the bus optical waveguide structure, the optical modulator structure, and the modulator heater structure are formed from the semiconductor layer of the semiconductor photonic device, making them continuous and physically connected. The physical connection between the optical modulator structure and the modulator heater structure provides a direct path for heat to be transferred from the modulator heater structure through the semiconductor layer to the optical modulator structure. An isolation region, which may include doped regions of the semiconductor layer, is included between the modulator heater structure and the bus optical waveguide structure and the optical modulator structure. The isolation region electrically isolates the modulator heater structure from the optical modulator structure. Therefore, the modulator heater structure and the optical modulator structure are physically connected and electrically isolated.

[0093] As described in more detail above, some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device includes a bus optical waveguide structure. The semiconductor photonic device includes an optical modulator structure adjacent to a first side of the bus optical waveguide structure. The semiconductor photonic device includes a modulator heater structure adjacent to a second side of the bus optical waveguide structure opposite to the first side, wherein the bus optical waveguide structure, the optical modulator structure, and the modulator heater structure are physically connected in a semiconductor layer of the semiconductor photonic device, and wherein the modulator heater structure includes an isolation region located between a heater section of the modulator heater structure and the bus optical waveguide structure.

[0094] In some embodiments, the isolation region includes a doped region of the semiconductor layer. In some embodiments, the isolation region includes a first region of the semiconductor layer, the first region including a first dopant type; and the heater segment includes one or more second regions of the semiconductor layer, the one or more second regions including a second dopant type different from the first dopant type. In some embodiments, the first region and the one or more second regions are vertically aligned in the semiconductor photonic device. In some embodiments, the heater segment extends generally parallel to the bus optical waveguide structure. In some embodiments, the modulator heater structure includes heater terminals located at opposite ends of the heater segment. In some embodiments, the opposite ends of the heater segment are generally aligned with opposite sides of the waveguide of the optical modulator structure.

[0095] As described in more detail above, some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device includes a bus optical waveguide structure extending along a first direction within the device. The semiconductor photonic device includes a closed-loop optical modulator structure adjacent to a first side of the bus optical waveguide structure. The semiconductor photonic device includes a modulator heater structure extending along the first direction and adjacent to a second side of the bus optical waveguide structure opposite to the first side. The bus optical waveguide structure, the closed-loop optical modulator structure, and the modulator heater structure are arranged in the semiconductor photonic device in a second direction substantially perpendicular to the first direction. The bus optical waveguide structure and the modulator heater structure are physically connected by a first connecting segment between the bus optical waveguide structure and the modulator heater structure. The bus optical waveguide structure and the closed-loop optical modulator structure are physically connected by a second connecting segment between the bus optical waveguide structure and the closed-loop optical modulator structure. The modulator heater structure includes an isolation region located between a heater segment of the modulator heater structure and the first connecting segment.

[0096] In some embodiments, an isolation region is located below a heater section; the top of the isolation region is in solid contact with the doped region of the heater section; the side of the isolation region is in solid contact with a first connector section; and the side of the isolation region faces the bus optical waveguide structure and the closed-loop optical modulator structure. In some embodiments, the bus optical waveguide structure, the closed-loop optical modulator structure, the modulator heater structure, the first connector section, and the second connector section are solidly connected in the semiconductor layer of the semiconductor photonic device. In some embodiments, the modulator heater structure includes a first doped semiconductor region having a first doped semiconductor region concentration, and a second doped semiconductor region located on the first doped semiconductor region and having a second doped semiconductor region concentration greater than the first doped semiconductor region concentration. In some embodiments, the first doped semiconductor region is located on top of the isolation region, and the first doped semiconductor region is located between the isolation region and the second doped semiconductor region. In some embodiments, the modulator heater structure includes a silicide layer located on the second doped semiconductor region. In some embodiments, the bus optical waveguide structure is located between the closed-loop optical modulator structure and the isolation region.

[0097] As described in more detail above, some embodiments described herein provide a method. The method includes forming an optical modulator structure, a bus optical waveguide structure adjacent to the optical modulator structure, and a modulator heater structure adjacent to the bus optical waveguide structure in a semiconductor layer above a first dielectric layer of a semiconductor photonic device. The optical modulator structure, the bus optical waveguide structure, and the modulator heater structure are physically connected in the semiconductor layer. The method includes doping a first portion of the modulator heater structure with a first dopant type. The method includes doping a second portion of the modulator heater structure located below the first portion with a second dopant type different from the first dopant type. The method includes doping a third portion of the modulator heater structure located above the first portion with the first dopant type. The method includes forming a second dielectric layer on the optical modulator structure, the bus optical waveguide structure, and the modulator heater structure.

[0098] In some embodiments, the method further includes forming a silicide layer on a third portion of the modulator heater structure, wherein forming the second dielectric layer includes: forming a first portion of the second dielectric layer before forming the silicide layer, such that the top surface of the first portion of the second dielectric layer is substantially coplanar with the top surface of the modulator heater structure; and forming a second portion of the second dielectric layer after forming the silicide layer. In some embodiments, forming the second dielectric layer includes: forming the first portion of the second dielectric layer before doping the first portion of the modulator heater structure; and forming the second portion of the second dielectric layer after doping the third portion of the modulator heater structure. In some embodiments, a bus optical waveguide structure is located between the optical modulator structure and the modulator heater structure in the semiconductor layer. In some embodiments, forming the modulator heater structure includes forming the modulator heater structure such that the modulator heater structure is located outside the periphery of the optical modulator structure. In some embodiments, the concentration of a first dopant of a first dopant type in the first portion of the modulator heater structure is lower than the concentration of a second dopant of the first dopant type in the third portion of the modulator heater structure.

[0099] The terms “approximately” and “substantially” can indicate that the value of a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, in light of this disclosure, the terms “approximately” and “substantially” can refer to a portion of the value of a given quantity.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor photonic device, characterized in that, include: Bus optical waveguide structure; An optical modulator structure is located adjacent to the first side of the bus optical waveguide structure; as well as The modulator heater structure is located adjacent to the second side of the bus optical waveguide structure opposite to the first side. The bus waveguide structure, the optical modulator structure, and the modulator heater structure are physically connected in the semiconductor layer of the semiconductor photonic device, and The modulator heater structure includes an isolation region located between the heater section of the modulator heater structure and the bus optical waveguide structure.

2. The semiconductor photonic device according to claim 1, characterized in that, The isolation region includes the doped region of the semiconductor layer.

3. The semiconductor photonic device according to claim 2, characterized in that, The isolation region includes a first region of the semiconductor layer, the first region including a first dopant type; and The heater section includes one or more second regions of the semiconductor layer, and the one or more second regions include a second dopant type different from the first dopant type.

4. The semiconductor photonic device according to claim 3, characterized in that, The first region and the one or more second regions are arranged vertically in the semiconductor photonic device.

5. The semiconductor photonic device according to claim 1, characterized in that, The heater section extends approximately parallel to the bus optical waveguide structure.

6. A semiconductor photonic device, characterized in that, include: A bus optical waveguide structure extends along a first direction in the semiconductor photonic device; A closed-loop optical modulator structure is located adjacent to the first side of the bus optical waveguide structure. as well as The modulator heater structure extends in the first direction and is adjacent to the second side of the bus optical waveguide structure opposite to the first side. The bus optical waveguide structure, the closed-loop optical modulator structure, and the modulator heater structure are arranged in a second direction that is substantially perpendicular to the first direction in the semiconductor photonic device. The bus optical waveguide structure and the modulator heater structure are physically connected by a first connecting section between the bus optical waveguide structure and the modulator heater structure. The bus optical waveguide structure and the closed-loop optical modulator structure are physically connected through a second connector section between them. The modulator heater structure includes an isolation zone located between the heater section of the modulator heater structure and the first connecting section.

7. The semiconductor photonic device according to claim 6, characterized in that, The isolation zone is located below the heater section; The top of the isolation region is in contact with the doped region of the heater section; The side of the isolation zone is in contact with the solid of the first connecting member section; and The side of the isolation zone faces the bus optical waveguide structure and the closed-loop optical modulator structure.

8. The semiconductor photonic device according to claim 6, characterized in that, The bus optical waveguide structure, the closed-loop optical modulator structure, the modulator heater structure, the first connector segment, and the second connector segment are physically connected in the semiconductor layer of the semiconductor photonic device.

9. The semiconductor photonic device according to claim 6, characterized in that, The modulator heater structure includes: A first doped semiconductor region having a first dopant concentration; and The second doped semiconductor region is located on the first doped semiconductor region and has a second dopant concentration greater than that of the first dopant concentration.

10. The semiconductor photonic device according to claim 6, characterized in that, The bus optical waveguide structure is located between the closed-loop optical modulator structure and the isolation region.

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