A supercapacitor brown-out protection circuit

Abstract

This utility model relates to a supercapacitor power-off protection circuit, including a power input circuit. The power input circuit is connected to a power detection circuit and a voltage reduction circuit. The power detection circuit is connected to a power management chip and a main control chip. The voltage reduction circuit is connected to a supercapacitor circuit. The supercapacitor circuit is also connected to a capacitor voltage detection circuit, which is also connected to the power management chip and the main control chip. Through the power detection circuit and the capacitor voltage detection circuit, this application enables the device to continue operating for 5 to 20 seconds after a sudden power outage or power failure, giving the device time to react and perform relevant data storage and protection.

Description

Technical Field

[0001] This utility model relates to the field of power failure protection circuits, and more specifically, to a supercapacitor power failure protection circuit. Background Technology

[0002] With the increasing prevalence of IoT devices and the widespread use of mobile payments, numerous devices rely on internet data to function. These include POS machines, real-time gateways, large industrial energy storage systems, access control gates, and various types of time and attendance machines. When these data-dependent devices experience a sudden power outage or failure, data loss and transaction failure can occur instantly. For example, at a checkout, a transaction may fail after scanning a QR code, resulting in no payment; gateways may suffer data loss; power outages may cause control units to malfunction; access control gates may fail to open after scanning a QR code; and time and attendance machines may have no attendance records after facial recognition.

[0003] Therefore, a circuit is needed to enable the device to continue working for 5 to 20 seconds after a sudden power outage or power failure, allowing the device time to react and perform relevant data storage and protection. Utility Model Content

[0004] To address the aforementioned shortcomings of existing technologies, a supercapacitor power-off protection circuit is provided.

[0005] The technical solution adopted by this utility model to solve its technical problem is: a supercapacitor power-down protection circuit, including a power input circuit, wherein the power input circuit is connected to a power detection circuit and a voltage reduction circuit, the power detection circuit includes a comparator U71B, a transistor Q57, and a MOSFET Q59, pin 5 of the comparator U71B is connected to the power input circuit, pin 6 of the comparator U71B is connected to the system power supply, pin 7 of the comparator U71B is connected to the base of the transistor Q57, the collector of the transistor Q57 is connected to the system power supply, the collector of the transistor Q57 is also connected to the gate of the MOSFET Q59, the drain of the MOSFET Q59 is connected to the power management chip and the main control chip, and the voltage reduction circuit is connected to a supercapacitor power-down protection circuit. The system includes a supercapacitor circuit, which is connected to pin 8 of comparator U71B. The supercapacitor circuit also includes a capacitor voltage detection circuit, comprising comparator U71A, transistor Q61, and MOSFET Q56. Pin 3 of comparator U71A is connected to the supercapacitor circuit, pin 2 of comparator U71A is connected to the system power supply, pin 8 of comparator U71A is also connected to the supercapacitor circuit, pin 1 of comparator U71A is connected to the base of transistor Q61, the collector of transistor Q61 is connected to the system power supply, the collector of transistor Q61 is also connected to the gate of MOSFET Q56, and the drain of MOSFET Q56 is connected to the power management chip and the main control chip.

[0006] Preferably, pin 5 of the comparator U71B is connected to a resistor R563, which is connected to the power input circuit. Pin 5 of the comparator U71B is also connected to a resistor R564 and a capacitor C507, both of which are grounded. A resistor R558 is connected in series between the comparator U71B and the transistor Q57. A resistor R562 is connected in series between the transistor Q57 and the system power supply. The collector of the transistor Q57 is also connected to a grounded capacitor C156. A resistor R559 is connected in series between the MOSFET Q59 and the power management chip.

[0007] Preferably, pin 3 of comparator U71A is connected to resistor R557, which is connected to the supercapacitor circuit. Pin 3 of comparator U71A is also connected to resistor R560 and capacitor C506, both of which are grounded. Pin 8 of comparator U71A is also connected to capacitor C44, which is grounded. A resistor R566 is connected in series between comparator U71A and transistor Q61. A resistor R556 is connected in series between transistor Q61 and the system power supply. The collector of transistor Q61 is also connected to a grounded capacitor C505. A resistor R561 is connected in series between MOSFET Q56 and the power management chip.

[0008] Preferably, the supercapacitor circuit includes a supercapacitor, the negative terminal of which is grounded, and the positive terminal of which is connected to pin 8 of U71B. The positive terminal of the supercapacitor is also connected to pin 8 of U71A and pin 3 of comparator U71A. The positive terminal of the supercapacitor is also connected to a first resistor group, a second resistor group, a third resistor group, a diode D36, and a diode D37 connected in parallel. The first resistor group, the second resistor group, the third resistor group, the diode D36, and the diode D37 are all connected to a voltage reduction circuit. The positive terminals of the diodes D36 and D37 are both connected to the supercapacitor, and the negative terminals of the diodes D36 and D37 are both connected to the voltage reduction circuit.

[0009] Preferably, the first resistor group includes resistors R567 and R565 connected in series, with resistor R567 connected to the supercapacitor and resistor R565 connected to the voltage reduction circuit; the second resistor group includes resistors R540 and R541 connected in series, with resistor R540 connected to the supercapacitor and resistor R541 connected to the voltage reduction circuit; and the third resistor group includes resistors R542 and R543 connected in series, with resistor R542 connected to the supercapacitor and resistor R543 connected to the voltage reduction circuit.

[0010] Preferably, the voltage reduction circuit includes a step-down chip U19. Pin BS of the step-down chip U19 is connected to a capacitor C153. Capacitor C153 is connected to an inductor L11. Pins LX1, LX2, and LX3 of the step-down chip U19 are all connected to the inductor L11. The inductor L11 is connected to capacitors C157, C151, and CE3, diodes D38, D39, and D40. Capacitors C157, C151, and CE3 are all grounded. The inductor L11... 11 is connected to the anodes of diodes D38, D39, and D40. The cathodes of diodes D38, D39, and D40 are all connected to the supercapacitor circuit. Pin FB of the step-down chip U19 is connected to resistor R354, capacitor C168, and resistor R384. Resistor R384 is grounded. Resistor R354 is connected to inductor L11. Capacitor C168 is connected to resistor R356, which is also connected to inductor L11.

[0011] Preferably, the power input circuit includes a dual-row connector. The negative terminal of the dual-row connector is connected to a reverse insertion protection circuit, which includes a MOSFET Q44 and a capacitor C136. The drain of the MOSFET Q44 is connected to the dual-row connector. The source of the MOSFET Q44 is connected to grounded inductors FB19 and FB20. The source of the MOSFET Q44 is also connected to a magnetic core common-mode inductor FB16. The gate of the MOSFET Q44 is connected to a resistor R275. Resistor R275 is connected to diode D8 and resistor R319. Diode D8 and resistor R319 are also connected to the source of the MOSFET Q44. Capacitor C136 is connected to resistor R320 and is also connected to the source of the MOSFET Q44. The positive terminal of the dual-row connector is connected to a resettable fuse PF1. The resettable fuse PF1 is connected to a resistor R271 and a capacitor C139. The resistor R271 is connected to the source of the MOSFET Q44. The resistor R271 is also connected to a capacitor C129, which is connected to a resistor R320. The capacitor C139 is also connected to a common-mode inductor FB16. The resettable fuse PF1 is also connected to inductors FB17 and FB18. The resettable fuse PF1 is also connected to the common-mode inductor FB16. Terminal 4 of the common-mode inductor FB16 is connected to the resettable fuse PF1. Terminal 3 of the common-mode inductor FB16 is connected to the source of the MOSFET Q44 and the capacitor C139. Terminal 2 of the common-mode inductor FB16 is grounded. Terminal 1 of the common-mode inductor FB16 is connected to a voltage reduction circuit.

[0012] Preferably, terminal 1 of the magnetic core common mode inductor FB16 is also connected to a grounded transient voltage suppressor TVS1.

[0013] The beneficial effects of this utility model are as follows: When there is a power outage or power failure, and the DC IN voltage is lower than 11V, the DC_DET_GPIO0_C6_D_3V3 signal output by the power detection circuit through comparator U71B will change from high level to low level. After the main control chip detects the change in the DC_DET_GPIO0_C6_D_3V3 signal level from high to low, the main control chip will save the data to complete the transaction or end the current process and enter the shutdown process. When the supercapacitor circuit provides sufficient voltage to complete the data saving or end the current process, and the supercapacitor circuit drops to the preset voltage, the comparator U71A outputs... The SCAP_DET_GPIO_A0_D_3V3 signal will change from high to low. After the main control chip detects the change in the SCAP_DET_GPIO_A0_D_3V3 signal level, it will immediately enter the shutdown process to prevent damage from over-discharge of the supercapacitor circuit or the system from entering an unpredictable state due to insufficient power supply. Through the above circuit, this application enables the device to continue to work for 5 to 20 seconds after a sudden power outage or power failure, giving the device time to react and perform relevant data storage and protection. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of the power supply detection circuit and the capacitor voltage detection circuit of this utility model embodiment;

[0015] Figure 2 This is a circuit diagram of the supercapacitor circuit according to an embodiment of this utility model;

[0016] Figure 3 This is a circuit diagram of the voltage reduction circuit according to an embodiment of this utility model;

[0017] Figure 4 This is a circuit diagram of the power input circuit of an embodiment of this utility model. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below. Obviously, the described embodiments are some embodiments of this utility model, but not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model. In addition, the directional terms mentioned in this utility model, such as "up," "down," "front," "back," "left," "right," "inner," and "outer," are only for reference to the directions in the accompanying drawings. The directional terms are used to better and more clearly explain and understand this utility model, and are not intended to indicate or imply the necessary orientation of this utility model. Therefore, they should not be construed as limitations on this utility model.

[0019] Examples of embodiments of this utility model Figures 1 to 4 As shown, a supercapacitor power-down protection circuit includes a power input circuit. The power input circuit is connected to a power detection circuit and a voltage reduction circuit. The power detection circuit includes a comparator U71B, a transistor Q57, and a MOSFET Q59. Pin 5 of the comparator U71B is connected to the power input circuit, pin 6 of the comparator U71B is connected to the system power supply, pin 7 of the comparator U71B is connected to the base of the transistor Q57, the collector of the transistor Q57 is connected to the system power supply, the collector of the transistor Q57 is also connected to the gate of the MOSFET Q59, and the drain of the MOSFET Q59 is connected to a power management chip and a main control chip. The voltage reduction circuit is connected to a supercapacitor circuit. The capacitor circuit is connected to pin 8 of comparator U71B. The supercapacitor circuit is also connected to a capacitor voltage detection circuit, which includes comparator U71A, transistor Q61, and MOSFET Q56. Pin 3 of comparator U71A is connected to the supercapacitor circuit, pin 2 of comparator U71A is also connected to the system power supply, pin 8 of comparator U71A is also connected to the supercapacitor circuit, pin 1 of comparator U71A is connected to the base of transistor Q61, the collector of transistor Q61 is connected to the system power supply, the collector of transistor Q61 is also connected to the gate of MOSFET Q56, and the drain of MOSFET Q56 is also connected to the power management chip and the main control chip.

[0020] When there is a power outage or power failure, and the DC IN voltage drops below 11V, the DC_DET_GPIO0_C6_D_3V3 signal output by the power detection circuit through comparator U71B will change from high to low. After the main control chip detects this change, it will save the data, complete the transaction, or terminate the current process and enter the shutdown procedure. Once the supercapacitor circuit provides sufficient voltage to save the data or terminate the current process, the supercapacitor circuit will drop to a preset voltage (8.2V). When the SCAP_DET_GPIO_A0_D_3V3 signal output by the U71A changes from high to low, the main control chip will immediately enter the shutdown process after detecting the change in the SCAP_DET_GPIO_A0_D_3V3 signal level. This prevents damage to the supercapacitor circuit due to over-discharge or the system from entering an unpredictable state due to insufficient power supply. Through the above circuit, this application enables the device to continue working for 5 to 20 seconds after a sudden power outage or power failure, giving the device time to react and perform relevant data storage and protection.

[0021] Further improvements, such as Figure 1 As shown, pin 5 of comparator U71B is connected to resistor R563, which is connected to the power input circuit. Pin 5 of comparator U71B is also connected to resistor R564 and capacitor C507, both of which are grounded. Resistor R558 is connected in series between comparator U71B and transistor Q57. Resistor R562 is connected in series between transistor Q57 and the system power supply. The collector of transistor Q57 is also connected to a grounded capacitor C156. Resistor R559 is connected in series between MOSFET Q59 and the power management chip. By adjusting the voltage division ratio of resistors R563 and R564, the voltage on pin 5 of comparator U71B is changed, thereby calibrating the 11V trigger point of comparator U71B.

[0022] Further improvements, such as Figure 1As shown, pin 3 of comparator U71A is connected to resistor R557, which is connected to a supercapacitor circuit. Pin 3 of comparator U71A is also connected to resistor R560 and capacitor C506, both of which are grounded. Pin 8 of comparator U71A is also connected to capacitor C44, which is grounded. Resistor R566 is connected in series between comparator U71A and transistor Q61. Resistor R556 is connected in series between transistor Q61 and the system power supply. The collector of transistor Q61 is also connected to a grounded capacitor C505. Resistor R561 is connected in series between MOSFET Q56 and the power management chip. By adjusting the voltage division ratio of resistor R556 or resistor R557, the 8.2V trigger point of comparator U71A can be calibrated.

[0023] Further improvements, such as Figure 2 As shown, the supercapacitor circuit includes a supercapacitor, the negative terminal of which is grounded, and the positive terminal of which is connected to pin 8 of U71B. The positive terminal of the supercapacitor is also connected to pin 8 of U71A and pin 3 of comparator U71A. The positive terminal of the supercapacitor is also connected to a first resistor group, a second resistor group, a third resistor group, a diode D36, and a diode D37 connected in parallel. The first resistor group, the second resistor group, the third resistor group, and diodes D36 and D37 are all connected to a voltage reduction circuit. The positive terminals of diodes D36 and D37 are both connected to the supercapacitor, and the negative terminals of diodes D36 and D37 are both connected to the voltage reduction circuit. The first resistor group, the second resistor group, and the third resistor group limit the current to approximately 0.5A.

[0024] Further improvements, such as Figure 2 As shown, the first resistor group includes resistors R567 and R565 connected in series. Resistor R567 is connected to the supercapacitor, and resistor R565 is connected to the step-down circuit. The second resistor group includes resistors R540 and R541 connected in series. Resistor R540 is connected to the supercapacitor, and resistor R541 is connected to the step-down circuit. The third resistor group includes resistors R542 and R543 connected in series. Resistor R542 is connected to the supercapacitor, and resistor R543 is connected to the step-down circuit.

[0025] Further improvements, such as Figure 3As shown, the voltage reduction circuit includes a step-down chip U19. A capacitor C153 is connected to pin BS of the step-down chip U19. Capacitor C153 is connected to inductor L11. Pins LX1, LX2, and LX3 of the step-down chip U19 are all connected to inductor L11. Inductor L11 is connected to capacitors C157, C151, and CE3, diodes D38, D39, and D40. Capacitors C157, C151, and CE3 are all grounded. Inductor L11 is connected to the anodes of diodes D38, D39, and D40. The cathodes of diodes D38, D39, and D40 are all connected to the supercapacitor circuit. Pin FB of the step-down chip U19 is connected to resistor R354, capacitor C168, and resistor R384. Resistor R384 is grounded, and resistor R354 is connected to inductor L11. Capacitor C168 is connected to resistor R356, which is also connected to inductor L11. This step-down circuit precisely reduces the 24V voltage to the required 12.5V for operation. Diodes D38, D39, and D40 prevent backflow of electricity from the supercapacitor circuit into the power supply.

[0026] Further improvements, such as Figure 4As shown, the power input circuit includes a dual-row connector. The negative terminal of the dual-row connector is connected to a reverse insertion protection circuit. The reverse insertion protection circuit includes a MOSFET Q44 and a capacitor C136. The drain of the MOSFET Q44 is connected to the dual-row connector. The source of the MOSFET Q44 is connected to grounded inductors FB19 and FB20. The source of the MOSFET Q44 is also connected to a magnetic core common-mode inductor FB16. The gate of the MOSFET Q44 is connected to a resistor. Resistor R275 is connected to diode D8 and resistor R319. Diode D8 and resistor R319 are also connected to the source of MOSFET Q44. Capacitor C136 is connected to resistor R320. Capacitor C136 is also connected to the source of MOSFET Q44. The positive terminal of the dual-row pin header is connected to resettable fuse PF1. Resettable fuse PF1 is connected to resistor R271 and capacitor C139. Resistor R271 is connected to the MOSFET... The source of Q44 is connected to the resistor. Resistor R271 is also connected to capacitor C129, which is connected to resistor R320. Capacitor C139 is also connected to the core common-mode inductor FB16. The resettable fuse PF1 is also connected to inductors FB17 and FB18, and is also connected to the core common-mode inductor FB16. Terminal 4 of the core common-mode inductor FB16 is connected to the resettable fuse PF1. Terminal 3 of the common-mode inductor FB16 is connected to the source of the MOSFET Q44 and capacitor C139. Terminal 2 of the common-mode inductor FB16 is grounded, and terminal 1 of the common-mode inductor FB16 is connected to the voltage reduction circuit. The self-resetting fuse PF1 protects against the impact of short circuits in the downstream equipment, while the reverse insertion protection circuit protects the downstream equipment from being burned out due to the user using the wrong power supply. The common-mode inductor FB16 can effectively prevent damage to the equipment due to power surges.

[0027] Further improvements, such as Figure 4 As shown, terminal 1 of the magnetic core common mode inductor FB16 is also connected to a grounded transient voltage suppressor TVS1, which protects the equipment from damage caused by static electricity.

[0028] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A supercapacitor power-off protection circuit, characterized in that, The system includes a power input circuit; the power input circuit is connected to a power detection circuit and a voltage reduction circuit; the power detection circuit includes a comparator U71B, a transistor Q57, and a MOSFET Q59; pin 5 of the comparator U71B is connected to the power input circuit; pin 6 of the comparator U71B is connected to the system power supply; pin 7 of the comparator U71B is connected to the base of the transistor Q57; the collector of the transistor Q57 is connected to the system power supply; the collector of the transistor Q57 is also connected to the gate of the MOSFET Q59; the drain of the MOSFET Q59 is connected to the power management chip and the main control chip; the voltage reduction circuit is connected to a supercapacitor circuit; the supercapacitor circuit is connected to the comparator... Pin 8 of U71B is connected; the supercapacitor circuit is also connected to a capacitor voltage detection circuit; the capacitor voltage detection circuit includes a comparator U71A, a transistor Q61, and a MOSFET Q56; pin 3 of the comparator U71A is connected to the supercapacitor circuit; pin 2 of the comparator U71A is also connected to the system power supply; pin 8 of the comparator U71A is also connected to the supercapacitor circuit; pin 1 of the comparator U71A is connected to the base of the transistor Q61; the collector of the transistor Q61 is connected to the system power supply; the collector of the transistor Q61 is also connected to the gate of the MOSFET Q56; the drain of the MOSFET Q56 is also connected to the power management chip and the main control chip.

2. The supercapacitor power-off protection circuit according to claim 1, characterized in that, Pin 5 of comparator U71B is connected to resistor R563; resistor R563 is connected to the power input circuit; pin 5 of comparator U71B is also connected to resistor R564 and capacitor C507; resistor R564 and capacitor C507 are both grounded; resistor R558 is connected in series between comparator U71B and transistor Q57; resistor R562 is connected in series between transistor Q57 and the system power supply; capacitor C156 is also connected to grounded at the collector of transistor Q57; resistor R559 is connected in series between MOSFET Q59 and the power management chip.

3. The supercapacitor power-off protection circuit according to claim 1, characterized in that, Pin 3 of comparator U71A is connected to resistor R557; resistor R557 is connected to the supercapacitor circuit; pin 3 of comparator U71A is also connected to resistor R560 and capacitor C506; both resistor R560 and capacitor C506 are grounded; pin 8 of comparator U71A is also connected to capacitor C44; capacitor C44 is grounded; resistor R566 is connected in series between comparator U71A and transistor Q61; resistor R556 is connected in series between transistor Q61 and the system power supply; the collector of transistor Q61 is also connected to a grounded capacitor C505; resistor R561 is connected in series between MOSFET Q56 and the power management chip.

4. The supercapacitor power-off protection circuit according to claim 1, characterized in that, The supercapacitor circuit includes a supercapacitor; the negative terminal of the supercapacitor is grounded; the positive terminal of the supercapacitor is connected to pin 8 of U71B; the positive terminal of the supercapacitor is also connected to pin 8 of U71A and pin 3 of comparator U71A; the positive terminal of the supercapacitor is also connected to a first resistor group, a second resistor group, a third resistor group, a diode D36, and a diode D37 connected in parallel; the first resistor group, the second resistor group, the third resistor group, the diode D36, and the diode D37 are all connected to a voltage reduction circuit; the positive terminals of diode D36 and diode D37 are both connected to the supercapacitor; the negative terminals of diode D36 and diode D37 are both connected to the voltage reduction circuit.

5. A supercapacitor power-off protection circuit according to claim 4, characterized in that, The first resistor group includes resistors R567 and R565 connected in series; resistor R567 is connected to a supercapacitor; resistor R565 is connected to a voltage-reducing circuit. The second resistor group includes resistors R540 and R541 connected in series; resistor R540 is connected to a supercapacitor; resistor R541 is connected to a voltage-reducing circuit. The third resistor group includes resistors R542 and R543 connected in series; resistor R542 is connected to a supercapacitor; resistor R543 is connected to a voltage-reducing circuit.

6. The supercapacitor power-off protection circuit according to claim 1, characterized in that, The voltage reduction circuit includes a step-down chip U19; the BS pin of the step-down chip U19 is connected to a capacitor C153; the capacitor C153 is connected to an inductor L11; the LX1, LX2, and LX3 pins of the step-down chip U19 are all connected to the inductor L11; the inductor L11 is connected to capacitors C157, C151, CE3, diodes D38, D39, and D40; capacitors C157, C151, and CE3 are all grounded; the inductor L11 and... The anodes of diodes D38, D39, and D40 are connected together; the cathodes of diodes D38, D39, and D40 are all connected to the supercapacitor circuit; pin FB of the step-down chip U19 is connected to resistor R354, capacitor C168, and resistor R384; resistor R384 is grounded; resistor R354 is connected to inductor L11; capacitor C168 is connected to resistor R356; resistor R356 is also connected to inductor L11.

7. A supercapacitor power-off protection circuit according to claim 1, characterized in that, The power input circuit includes a dual-row connector; the negative terminal of the dual-row connector is connected to a reverse insertion protection circuit; the reverse insertion protection circuit includes a MOSFET Q44 and a capacitor C136; the drain of the MOSFET Q44 is connected to the dual-row connector; the source of the MOSFET Q44 is connected to grounded inductors FB19 and FB20; the source of the MOSFET Q44 is also connected to a magnetic core common-mode inductor FB16; the gate of the MOSFET Q44 is connected to a resistor R275; the resistor R275 is connected to a diode D8 and a resistor R319; the diode D8 and the resistor R319 are also connected to the source of the MOSFET Q44; the capacitor C136 is connected to a resistor R320; the capacitor C136 is also connected to the source of the MOSFET Q44; the positive terminal of the dual-row connector is connected to a resettable fuse PF1; the resettable fuse PF1 is connected to the source of the MOSFET Q4 ... The resettable fuse PF1 is connected to a resistor R271 and a capacitor C139; the resistor R271 is connected to the source of the MOSFET Q44; the resistor R271 is also connected to a capacitor C129; the capacitor C129 is also connected to a resistor R320; the capacitor C139 is also connected to a core common-mode inductor FB16; the resettable fuse PF1 is also connected to inductors FB17 and FB18; the resettable fuse PF1 is also connected to the core common-mode inductor FB16; terminal 4 of the core common-mode inductor FB16 is connected to the resettable fuse PF1; terminal 3 of the core common-mode inductor FB16 is connected to the source of the MOSFET Q44 and the capacitor C139; terminal 2 of the core common-mode inductor FB16 is grounded; terminal 1 of the core common-mode inductor FB16 is connected to a voltage reduction circuit.

8. A supercapacitor power-off protection circuit according to claim 7, characterized in that, Terminal 1 of the magnetic core common mode inductor FB16 is also connected to a grounded transient voltage suppressor TVS1.

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