ESD protection circuit and electronic device

Abstract

An ESD protection circuit and electronic device are disclosed. The ESD protection circuit includes a first discharge circuit and a second discharge circuit connected in parallel between the positive and negative terminals of a power supply. The first discharge circuit includes a first MOSFET and a trigger circuit. The first MOSFET includes a first gate, a first source region, and a first drain region. The first drain region is electrically connected to the positive terminal of the power supply, and the first source region is electrically connected to the negative terminal of the power supply. The trigger circuit is electrically connected to the first gate to trigger the first MOSFET to conduct when an ESD event occurs. The conductive channel formed between the first source region and the first drain region serves as part of the first discharge circuit, enabling conduction between the positive and negative terminals of the power supply through the first discharge circuit. The second discharge circuit includes a second MOSFET, which includes a second gate, a second source region, a second drain region, and a body region. When an ESD event occurs, the second MOSFET is broken down, and the body region serves as part of the second discharge circuit, enabling conduction between the positive and negative terminals of the power supply through the second discharge circuit.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and more specifically to an ESD protection circuit and electronic device. Background Technology

[0002] In chips such as, but not limited to, power devices, ESD (Electro-Static Discharge) protection circuits are typically included. These circuits discharge instantaneous high voltage applied to chip pins through pathways that prevent breakdown of internal chip circuitry, thus avoiding damage to core components. However, current ESD protection circuits cannot simultaneously meet the requirements of both fast turn-on speed and strong discharge capability. Utility Model Content

[0003] The utility model description section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This utility model description section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0004] To address the existing problems, this utility model provides an ESD protection circuit, which includes:

[0005] The first discharge circuit and the second discharge circuit are connected in parallel between the positive and negative terminals of the power supply, wherein,

[0006] The first discharge circuit includes a first MOSFET and a trigger circuit. The first MOSFET includes a first gate, a first source region, and a first drain region. The first drain region is electrically connected to the positive terminal of the power supply, and the first source region is electrically connected to the negative terminal of the power supply. The trigger circuit is electrically connected to the first gate to trigger the first MOSFET to conduct when an ESD event occurs. Thus, the conductive channel formed between the first source region and the first drain region serves as part of the first discharge circuit, enabling the positive terminal of the power supply and the negative terminal of the power supply to conduct through the first discharge circuit.

[0007] The second discharge circuit includes a second MOSFET, which includes a second gate, a second source region, a second drain region, and a body region. The second drain region is electrically connected to the positive terminal of the power supply, and the second gate and the second source region are electrically connected and both are electrically connected to the negative terminal of the power supply. When an ESD event occurs, the second MOSFET is broken down, and the body region, as part of the second discharge circuit, allows the positive and negative terminals of the power supply to remain connected through the second discharge circuit.

[0008] In some embodiments of this application, the first discharge circuit further includes a first resistor electrically connected between the first source region and the negative terminal of the power supply.

[0009] In some embodiments of this application, the body region is electrically connected to the ground terminal, and when an ESD event occurs, the positive terminal of the power supply is also connected to the ground terminal through the body region.

[0010] In some embodiments of this application, the area of ​​the first MOS transistor is smaller than the area of ​​the second MOS transistor.

[0011] In some embodiments of this application, the ESD protection circuit further includes:

[0012] A semiconductor substrate, in which a ring-shaped isolation structure is formed, and a bulk region is disposed inside the isolation structure and is P-type doped;

[0013] The first source region, the first drain region, the second source region, and the second drain region are formed in the bulk region and are N-type doped.

[0014] In some embodiments of this application, a P-type doped ground doped region electrically connected to a ground terminal is also formed in the body region, and the doping concentration of the ground doped region is greater than that of the body region.

[0015] The second MOSFET is positioned between the first MOSFET and the ground doped region.

[0016] In some embodiments of this application, a second MOS transistor is disposed in the first device region and the second device region, wherein the first device region and the second device region are respectively located on both sides of the first MOS transistor;

[0017] The ground doped region includes: a first ground doped region located on the side of the first device region away from the first MOS transistor, and a second ground doped region located on the side of the second device region away from the first MOS transistor.

[0018] In some embodiments of this application, the first gate includes a plurality of first gate lines that are at least partially disposed on the body region and extend along a first direction, and the plurality of first gate lines are spaced apart along a second direction perpendicular to the first direction;

[0019] The second gate includes at least a portion of a plurality of second gate lines disposed on the body region and extending along a first direction. A portion of the plurality of second gate lines are spaced apart in the first device region along a second direction, and another portion is spaced apart in the second device region along the second direction.

[0020] In some embodiments of this application, the trigger circuit includes:

[0021] A capacitor, with its first terminal electrically connected to the positive terminal of a power supply and its second terminal electrically connected to a first gate; and...

[0022] The second resistor has its first end electrically connected to the second end of the capacitor and the first gate, and its second end electrically connected to the negative terminal of the power supply.

[0023] A second aspect of this utility model provides an electronic device, which includes any of the above-described ESD protection circuits.

[0024] According to the ESD protection circuit and electronic device provided by this utility model, a first discharge circuit and a second discharge circuit are connected in parallel between the positive and negative terminals of the power supply. The trigger circuit of the first discharge circuit is electrically connected to the first gate to trigger the first MOSFET to conduct when an ESD event occurs. Thus, the conductive channel formed between the first source region and the first drain region serves as part of the first discharge circuit, allowing the positive and negative terminals of the power supply to conduct through the first discharge circuit. Furthermore, when an ESD event occurs, the second MOSFET is broken down, and its body region serves as part of the second discharge circuit, allowing the positive and negative terminals of the power supply to conduct through the second discharge circuit as well. By utilizing the fast turn-on speed of the first discharge circuit and the strong discharge capability of the second discharge circuit, the ESD protection circuit shown in this application can simultaneously meet the requirements of both fast turn-on speed and strong discharge capability. Attached Figure Description

[0025] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0026] In the attached image:

[0027] Figure 1 A circuit topology diagram of an ESD protection circuit according to a specific embodiment of the present invention is shown.

[0028] Figure 2 The diagram shows the structure of an ESD protection circuit and a schematic diagram of the ESD current path according to a specific embodiment of the present invention.

[0029] Figure 3 The diagram shows a top view of the distribution of the first MOS transistor and the second MOS transistor according to a specific embodiment of the present invention.

[0030] Figure 4 This is a top view schematic diagram of the gate line lead-out according to a specific embodiment of the present invention;

[0031] Figure 5 A schematic diagram of the TLP curve of an existing RCMOS circuit is shown;

[0032] Figure 6 A schematic diagram of the TLP curve of an existing GGNMOS is shown;

[0033] Figure 7 The diagram shows a TLP curve of an ESD protection circuit according to a specific embodiment of the present invention.

[0034] Figure label:

[0035] 101 - Positive power supply terminal; 102 - Negative power supply terminal

[0036] 103-Grounding terminal 201-First discharge circuit

[0037] 202-Second discharge circuit 203-Trigger circuit

[0038] 301 - Body region; 302 - Semiconductor substrate

[0039] 303 - Isolation structure; 304 - First gate line

[0040] 305 - First Device Area; 306 - Second Device Area

[0041] 307 - Second gate line; 308 - First ground doped region

[0042] 309 - Second grounding doped region; 310 - First busbar

[0043] 311-Second Busbar Detailed Implementation

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the present invention.

[0045] It should be understood that this invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this invention to those skilled in the art. In the drawings, for clarity, the dimensions of layers and regions, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] In view of the technical problems existing in the background section, refer to Figure 1 and Figure 2 This utility model embodiment proposes an ESD protection circuit, which mainly includes:

[0050] Connected in parallel to the positive terminal of the power supply 101 ( Figure 1 In this context, VDD represents the positive terminal 101 and the negative terminal 102 of the power supply. Figure 1 In this context, VSS represents the first discharge circuit 201 between the negative terminal of the power supply (102) and the first discharge circuit 201 (e.g., ...). Figure 2 ① in the text indicates the first discharge circuit 201 and the second discharge circuit 202 (e.g., Figure 2 In the diagram, ② represents the second discharge circuit 202, where,

[0051] The first discharge circuit 201 includes a first MOSFET ( Figure 1 M1 in the diagram represents the first MOSFET) and trigger circuit 203203. The first MOSFET includes a first gate ( Figure 2 In this context, G1 represents the first gate and the first source region. Figure 2 S1 in the diagram represents the first source region and the first drain region. Figure 2 D1 in the diagram represents the first drain region. The first drain region is electrically connected to the positive terminal 101 of the power supply, and the first source region is electrically connected to the negative terminal 102 of the power supply. The trigger circuit 203 is electrically connected to the first gate to trigger the first MOS transistor to conduct when an ESD event occurs, thereby forming a conductive channel between the first source region and the first drain region. Figure 2 The area through which the Ichannel flows (representing the conductive channel) serves as part of the first discharge circuit 201, enabling the positive terminal 101 of the power supply and the negative terminal 102 of the power supply to be connected through the first discharge circuit 201.

[0052] The second discharge circuit 202 includes a second MOSFET ( Figure 1 M2 in the diagram represents the second MOSFET, which includes a second gate ( Figure 2 In this context, G2 represents the second gate and the second source region. Figure 2 S2 in the text represents the second source region and the second drain region. Figure 2 D2 in the text represents the second drain region) and body region 301 ( Figure 2 In this context, PSUB represents body region 301. The second drain region is electrically connected to the positive power supply 101, and the second gate and second source regions are electrically connected and both are electrically connected to the negative power supply 102. During an ESD event, the second MOSFET is damaged, and body region 301 becomes part of the second discharge circuit 202. Figure 2 The area through which Isub flows represents the current channel in body region 301, so that the positive terminal 101 and the negative terminal 102 of the power supply are also connected through the second discharge circuit 202.

[0053] The above embodiments have the following beneficial effects: By connecting a first discharge circuit 201 and a second discharge circuit 202 in parallel between the positive terminal 101 and the negative terminal 102 of the power supply, and the trigger circuit 203 of the first discharge circuit 201 is electrically connected to the first gate to trigger the first MOS transistor to conduct when an ESD event occurs, the conductive channel formed between the first source region and the first drain region becomes part of the first discharge circuit 201, allowing the positive terminal 101 and the negative terminal 102 of the power supply to conduct through the first discharge circuit 201; and when an ESD event occurs, the second MOS transistor is broken down, and the body region 301 becomes part of the second discharge circuit 202, allowing the positive terminal 101 and the negative terminal 102 of the power supply to also conduct through the second discharge circuit 202. Utilizing the characteristics of the first discharge circuit 201 having a fast turn-on speed and the second discharge circuit 202 having a strong discharge capability, the ESD protection circuit shown in this application achieves a balance between turn-on speed and discharge capability, thereby simultaneously meeting both requirements.

[0054] The specific principles are as follows: Common ESD protection circuits in related technologies include RCMOS circuits and GGNMOS circuits. In an RCMOS circuit, when an ESD event occurs between the power supply and ground, the capacitor connected to VDD (positive power supply 101) and the gate is charged, the gate voltage of the MOSFET rises and it turns on. The ESD current is discharged through the conductive channel in the MOSFET until the gate charge is discharged to VSS (negative power supply 102) through a resistor. The gate voltage then drops, and the MOSFET turns off. The RCMOS circuit has a lower Vt1 (turn-on voltage), giving it the advantage of fast turn-on speed, but its discharge path is a conductive channel, resulting in weaker discharge capability. In a GGNMOS circuit, the gate and source of the MOSFET are shorted and connected to VSS. When an ESD event occurs, the PN junction formed by the drain and the P-type SUB (substrate) is reverse-biased, and the ESD current is discharged through the SUB. Simultaneously, the PN junction formed by the source and the P-type SUB is forward-biased, also serving as an ESD current discharge path. GGNMOS circuits discharge ESD current through the P-type SUB, which has a strong discharge capability. However, the turn-on depends on the reverse breakdown of the PN junction, resulting in a high Vt1 and a slow turn-on speed.

[0055] The manner illustrated in the above embodiments of this application is referred to... Figure 1 and Figure 2A first discharge circuit 201 and a second discharge circuit 202 are connected in parallel between the positive terminal 101 and the negative terminal 102 of the power supply. The first discharge circuit 201 is electrically connected to the first gate of the first MOSFET via a trigger circuit 203. Whether the first discharge circuit 201 is turned on depends on whether the trigger circuit 203 triggers the first MOSFET to turn on. That is, the turn-on voltage of the first discharge circuit 201 is equal to or close to the turn-on voltage of the first MOSFET, which allows for a low turn-on voltage and thus gives the first discharge circuit 201 the advantage of fast turn-on speed. Although the conductive channel between the first source and the first drain is part of the first discharge circuit 201, allowing ESD current to flow through the conductive channel and thus limiting the discharge capability of the first discharge circuit 201, this requirement can be reinforced by the second discharge circuit 202, as described below.

[0056] In the second discharge circuit 202, the second gate and the second source region of the second MOSFET are electrically connected and both are electrically connected to the negative terminal of the power supply 102. When an ESD event occurs, the second MOSFET breaks down, and the body region 301, as part of the second discharge circuit 202, allows the positive terminal of the power supply 101 and the negative terminal of the power supply 102 to remain connected through the second discharge circuit 202. That is, at this time, the diode formed by the second drain and the body region 301 breaks down in reverse, providing a discharge path through the body region 301. Simultaneously, the voltage drop generated causes the PN junction formed by the body region 301 and the second source to conduct in the forward direction, serving as a discharge path for the ESD current. Thus, the body region 301, as part of the second discharge circuit 202, enables the connection between the positive terminal of the power supply 101 and the negative terminal of the power supply 102. Since the second discharge circuit 202 does not rely on the conductive channel formed between the second source and the second drain, the body region 301 can support large current discharge, giving the second discharge circuit 202 the advantage of strong discharge capability. Although the turn-on voltage of the second discharge circuit 202 is close to or equal to the breakdown voltage of the diode composed of the second drain and body region 301 when it is reverse-broken, and its turn-on voltage is relatively high, as mentioned above, the overall turn-on voltage of the ESD protection circuit of this application is the turn-on voltage of the first discharge circuit 201, so that the ESD protection circuit can still have the advantages of low turn-on voltage and fast turn-on speed.

[0057] In summary, the ESD protection circuit shown in this application combines two structures, combining the fast turn-on speed of RCMOS and the strong discharge capability of GGNMOS. While reducing the turn-on voltage Vt1 to improve the turn-on speed, it also improves the discharge capability of the ESD protection circuit.

[0058] The following tests were conducted using existing RCMOS circuits, GGNMOS circuits, and the ESD protection circuit shown in an embodiment of this application to obtain the corresponding TLP (Transmission Line Pulse) data. By comparing the TLP data of the three structures, it can be demonstrated that the ESD protection circuit shown in this application can achieve the expected effect.

[0059] refer to Figure 5 The TLP curve of the RCMOS circuit is shown. The turn-on voltage (Vt1) of the RCMOS circuit is about 7.2V, which is less than 8V. It can be seen that the RCMOS circuit has a fast turn-on speed, but the ESD current discharge capability is weak (the maximum discharge current is about 2.8A).

[0060] refer to Figure 6 The TLP curve of the GGNMOS circuit shown is approximately 12.5V. It does not have the ability to turn on quickly, but it has a strong ESD current discharge capability (the maximum discharge current is approximately 3.75A).

[0061] refer to Figure 7 The TLP curve of the ESD protection circuit of one embodiment of this application is shown. The turn-on voltage (Vt1) is about 7.2V, which is less than 8V; the maximum discharge current is about 5.1A.

[0062] As can be seen from the comparison, the ESD protection circuit shown in the embodiment of this application can reduce the turn-on voltage (Vt1) to below 8V while maintaining a high discharge capability, which basically achieves the effect of fast turn-on speed and high discharge capability.

[0063] Furthermore, since the first discharge circuit 201 shown in this embodiment mainly serves as the startup current, and the first MOSFET in the first discharge circuit 201 basically does not participate in the discharge of ESD current, the area of ​​the first MOSFET can be significantly reduced compared to the existing RCMOS circuit. The principle is as follows: reducing the area of ​​the MOSFET will reduce the load current of the MOSFET. To improve the discharge capability, the existing RCMOS circuit needs to occupy a relatively large MOSFET area. However, in this application, most of the discharge current is discharged through the second discharge circuit 202, and the discharge current of the first discharge circuit 201 is smaller. Therefore, it is not necessary to improve the load current capability of the first MOSFET, and thus it is not necessary to occupy a large MOSFET area. Moreover, under the same area, the discharge capability of the body region 301 of the second discharge circuit 202 is much greater than that of the existing RCMOS transistor. Therefore, the second MOSFET can achieve the discharge capability of the existing RCMOS transistor with a smaller area. Thus, the area occupied by the first MOSFET and the second MOSFET in this embodiment is smaller, achieving the purpose of area reduction. Tests revealed that, under the same discharge capability, the total area occupied by the first MOS transistor and the second MOS transistor in the ESD protection circuit shown in this application embodiment can be reduced by more than 50% compared with the existing RCMOS transistor circuit.

[0064] Below, for reference Figures 1 to 4 The ESD protection circuit of this utility model embodiment is described in detail.

[0065] Regarding the types of the first and second MOSFETs, NMOS transistors and PMOS transistors can be used, but are not limited to. In a preferred embodiment, an NMOS transistor is selected as both the first and second MOSFETs to improve discharge capability. The following example illustrates this using an NMOS transistor as both the first and second MOSFETs.

[0066] There are various ways to configure the trigger circuit 203. As long as it can detect whether an ESD event has occurred and trigger the first MOS transistor to conduct when an ESD event is detected, it falls within the protection scope of this application. The following is an exemplary description of how to configure the trigger circuit 203.

[0067] For example, refer to Figure 1 and Figure 2 The trigger circuit 203 may include: a capacitor (such as...) Figure 1 and Figure 2 In this context, C1 represents the capacitor and the second resistor (e.g., ...). Figure 1 and Figure 2In this diagram, R2 represents the second resistor. The first terminal of the capacitor is electrically connected to the positive terminal 101 of the power supply, and the second terminal of the capacitor is electrically connected to the first gate. The first terminal of the second resistor is electrically connected to the second terminal of the capacitor and the first gate, and the second terminal of the second resistor is electrically connected to the negative terminal 102 of the power supply. Figure 1 and Figure 2 As shown, when an ESD event occurs, capacitor C1 is charged. After reaching a certain level, capacitor C1 raises the potential of the first gate G1, thereby turning on the first MOSFET. This allows the positive and negative terminals of the power supply 101 and 102 to be connected through the first discharge circuit 201. The ESD current is discharged through the conductive channel via the first discharge circuit 201①. By using capacitor C1 and the second resistor R2, the structure of the trigger circuit 203 is simplified, and the sensitivity of the trigger circuit 203 in detecting ESD events is improved.

[0068] In some embodiments, reference Figure 1 and Figure 2 The first discharge circuit 201 may further include: a first resistor electrically connected between the first source region and the negative power supply 102. Figure 1 and Figure 2 In this context, R1 represents the first resistor. By setting the first resistor in the first discharge circuit 201, the first resistor mainly serves to limit the current. After the first discharge circuit 201 is turned on, under the action of the first resistor R1, the first discharge circuit 201 cannot support the discharge of a large current, allowing the ESD current to be discharged through the body region 301PSUB. Specifically, since the ESD current always needs to be discharged to the negative terminal of the power supply 102VSS, after the ESD current reaches a certain level, it can be discharged through the second discharge circuit 202②. In the second discharge circuit 202, refer to... Figure 2 The diode formed by the second drain region D2 and the body region 301PSUB undergoes reverse breakdown, providing a discharge path through the body region 301PSUB. Simultaneously, the resulting voltage drop causes the PN junction formed by the body region 301PSUB and the second source region S2 to conduct in the forward direction, serving as a discharge path for ESD current. Discharging ESD current through the second discharge circuit 202 enhances the discharge capability of the ESD protection circuit.

[0069] For example, refer to Figure 2 The body region 301 can also be electrically connected to the ground terminal 103. When an ESD event occurs, the positive terminal 101 of the power supply is also connected to the ground terminal 103 through the body region 301. This allows the ESD current to be discharged not only to the negative terminal 102 of the power supply through the broken-down second MOSFET, but also to the ground terminal 103 through the body region 301. Since the ground terminal 103 can provide a strong current discharge function, the discharge capability of the second discharge circuit 202 can be further improved.

[0070] For example, the area of ​​the first MOSFET can be smaller than the area of ​​the second MOSFET. It should be noted that the area of ​​the MOSFET refers to the area on the body region 301 occupied by the MOSFET. The area of ​​the first MOSFET can be referred to by the projected area of ​​the first source region and the first drain region on the surface parallel to the semiconductor substrate 302. Similarly, the area of ​​the second MOSFET can be referred to by the projected area of ​​the second source region and the second drain region on the surface parallel to the semiconductor substrate 302.

[0071] In the above embodiments, since the first discharge circuit 201 mainly serves as the start-up circuit of the ESD protection circuit, while the second discharge circuit 202 mainly bears most of the ESD current discharge, by reducing the area of ​​the first MOSFET and increasing the area of ​​the second MOSFET, making the area of ​​the second MOSFET larger than that of the first MOSFET, the discharge capability of the second discharge circuit 202 is further improved while the start-up speed is fast, and the total area of ​​the first MOSFET and the second MOSFET can also be reduced, which is beneficial to the miniaturization of the device.

[0072] In some embodiments, the first MOS transistor and the second MOS transistor can be disposed in the same active region (the region enclosed by the isolation structure 303), that is, the first MOS transistor and the second MOS transistor share the same body region 301.

[0073] For example, the ESD protection circuit further includes: a semiconductor substrate 302, in which a ring-shaped isolation structure 303 is formed; a body region 301 is disposed inside the isolation structure 303 and is P-type doped; a first source region, a first drain region, a second source region, and a second drain region are formed in the body region 301 and are N-type doped. By using the P-type doped body region 301 and the N-type doped source and drain regions to form the first MOSFET and the second MOSFET, the discharge capability of the ESD protection circuit can be improved. Simultaneously, forming the first MOSFET and the second MOSFET in the active region inside the same isolation structure 303 can improve the integration density of the ESD protection circuit.

[0074] Of course, it should be noted that in some other embodiments, the first MOS transistor and the second MOS transistor may be located in different active regions.

[0075] For example, refer to Figure 2 and Figure 3 In body region 301, a P-type doped ground doped region (e.g., for electrical connection to ground terminal 103) is also formed. Figure 2 and Figure 3 In this context, P+ represents the ground doped region. The doping concentration of the ground doped region is greater than that of the body region 301, thereby reducing the resistance between the body region 301 and the ground terminal 103.

[0076] For example, refer to Figure 2 and Figure 3 The second MOSFET is positioned between the first MOSFET and the ground doped region. Specifically, in the top view of the semiconductor substrate 302, the first MOSFET and the ground doped region are separated by the second MOSFET. Thus, after the first MOSFET is turned on, the ESD current in the body region 301 can flow sequentially from the direction of the first MOSFET through the direction of the second MOSFET to the ground terminal 103. This ensures that the turn-on sequence of the first MOSFET and the second MOSFET is consistent with the direction of ESD current flow, thereby improving the discharge rate.

[0077] There are several ways to place the second MOSFET between the first MOSFET and the ground doped region. Some of these methods are illustrated below.

[0078] For example, refer to Figure 2 and Figure 3 The second MOSFET is disposed in the first device region 305 and the second device region 306, wherein the first device region 305 and the second device region 306 are respectively located on both sides of the first MOSFET. The ground doped region includes: a first ground doped region 308 located on the side of the first device region 305 away from the first MOSFET, and a second ground doped region 309 located on the side of the second device region 306 away from the first MOSFET.

[0079] Specifically, in the above embodiments, reference is made to Figure 3 The second MOSFET is divided into two parts, one part of which is located in the first device region 305 and the other part is located in the second device region 306, separated by the first MOSFET. Similarly, a first ground doped region 308 and a second ground doped region 309 are respectively provided on both sides of the body region 301 in the second direction. The first MOSFET is located between the first ground doped region 308 and the second ground doped region 309, with the first device region 305 located between the first MOSFET and the first ground doped region 308, and the second device region 306 located between the first MOSFET and the second ground doped region 309. This allows the first MOSFET, which occupies a smaller area, to be located in the middle of the body region 301 in the second direction, while the second MOSFET, which mainly participates in ESD current discharge, is located on both sides of the first MOSFET. A ground doped region is provided on each side of the body region 301 in the second direction, so that the ESD current in the body region 301 flows from the middle region of the body region 301 through the second MOSFET to the ground doped regions on both sides, improving the discharge efficiency.

[0080] There are several ways to configure the first gate and the second gate. Some methods are illustrated below.

[0081] For example, refer to Figure 3The first gate includes a plurality of first gate lines 304 that are at least partially disposed on the body region 301 and extend along a first direction, and the plurality of first gate lines 304 are spaced apart along a second direction perpendicular to the first direction; the second gate includes a plurality of second gate lines 307 that are at least partially disposed on the body region 301 and extend along the first direction, a portion of the plurality of second gate lines 307 are spaced apart along the second direction in the first device region 305, and another portion is spaced apart along the second direction in the second device region 306.

[0082] In the above-described manner, during the fabrication process, multiple source and drain regions extending along the first direction can be arranged alternately and sequentially along the second direction in the body region 301, and gate lines extending along the first direction and arranged alternately along the second direction can be formed on the body region 301. (Refer to...) Figure 2 and Figure 3 Each gate line has a source region and a drain region constructed in the second direction. These gate lines are then divided into two parts, and the gate lines in each part are electrically connected to each other, thereby completing the fabrication of the first MOSFET and the second MOSFET, simplifying the fabrication efficiency of the first MOSFET and the second MOSFET.

[0083] For example, refer to Figure 4 The first gate may further include a first bus 310, which extends along a second direction and is located at one end of the plurality of first gate lines 304 in the first direction (e.g., Figure 4 (It can be located at the upper end), and the first bus 310 electrically connects all the first gate lines 304, so that multiple first gate lines 304 can be electrically led out to the first gate pad of the first gate through the first bus 310, thereby simplifying the lead-out of multiple first gate lines 304.

[0084] For example, refer to Figure 4 The second gate may further include a second bus 311, which extends along a second direction and is located at one end of the plurality of second gate lines 307 in the first direction (e.g., Figure 4 (It can be located at the lower end), and the second bus 311 electrically connects all the second gate lines 307, so that multiple second gate lines 307 can be electrically led out to the second gate pad of the second gate through the second bus 311, thereby simplifying the lead-out of multiple second gate lines 307.

[0085] In other embodiments, the first device region 305, the first ground doped region 308, and the first MOS transistor can be configured as described above. In this case, the first MOS transistor, the second MOS transistor, and the ground doped region each occupy one region, and the second MOS transistor is located between the first MOS transistor and the ground doped region. It is not necessary to set the second MOS transistor in two separate device regions, thereby simplifying the electrical lead-out of the second MOS transistor.

[0086] Example 2

[0087] In another embodiment of this utility model, an electronic device is also provided, which includes any of the above-described ESD protection circuits.

[0088] The electronic device in this embodiment can be any electronic product or device, such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, PFC device, transformer, charger, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the present invention has better performance due to the use of the aforementioned ESD protection circuit.

[0089] This utility model has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the utility model to the described embodiments. Furthermore, those skilled in the art will understand that this utility model is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this utility model, all of which fall within the scope of protection claimed by this utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. An ESD protection circuit, characterized by, include: The first discharge circuit and the second discharge circuit are connected in parallel between the positive and negative terminals of the power supply, wherein, The first discharge circuit includes a first MOSFET and a trigger circuit. The first MOSFET includes a first gate, a first source region, and a first drain region. The first drain region is electrically connected to the positive terminal of the power supply, and the first source region is electrically connected to the negative terminal of the power supply. The trigger circuit is electrically connected to the first gate to trigger the first MOS transistor to turn on when an ESD event occurs, so that the conductive channel formed between the first source region and the first drain region serves as part of the first discharge circuit, allowing the positive terminal of the power supply and the negative terminal of the power supply to be connected through the first discharge circuit. The second discharge circuit includes a second MOSFET, which includes a second gate, a second source region, a second drain region, and a body region. The second drain region is electrically connected to the positive terminal of the power supply, and the second gate and the second source region are electrically connected and both are electrically connected to the negative terminal of the power supply. When the ESD event occurs, the second MOSFET is broken down, and the body region, as part of the second discharge circuit, allows the positive terminal of the power supply and the negative terminal of the power supply to remain connected through the second discharge circuit.

2. The ESD protection circuit of claim 1, wherein, The first discharge circuit further includes a first resistor electrically connected between the first source region and the negative terminal of the power supply.

3. The ESD protection circuit of claim 1, wherein, The body region is electrically connected to the ground terminal, and when the ESD event occurs, the positive terminal of the power supply is also connected to the ground terminal through the body region.

4. The ESD protection circuit of claim 1, wherein, The area of ​​the first MOSFET is smaller than the area of ​​the second MOSFET.

5. The ESD protection circuit of claim 1, wherein, Also includes: A semiconductor substrate having an annular isolation structure formed therein, wherein the body region is disposed inside the isolation structure and is P-type doped; The first source region, the first drain region, the second source region, and the second drain region are formed in the body region and are N-type doped.

6. The ESD protection circuit of claim 5, wherein, The body region also contains a P-type doped ground doped region electrically connected to the ground terminal, and the doping concentration of the ground doped region is greater than that of the body region. The second MOS transistor is disposed between the first MOS transistor and the ground doped region.

7. The ESD protection circuit of claim 6, wherein, The second MOS transistor is disposed in the first device region and the second device region, wherein the first device region and the second device region are respectively located on both sides of the first MOS transistor; The ground doping region includes: a first ground doping region located on the side of the first device region away from the first MOS transistor, and a second ground doping region located on the side of the second device region away from the first MOS transistor.

8. The ESD protection circuit of claim 7, wherein, The first gate includes a plurality of first gate lines that are at least partially disposed on the body region and extend along a first direction, and the plurality of first gate lines are spaced apart along a second direction perpendicular to the first direction; The second gate includes at least a portion of a plurality of second gate lines disposed on the body region and extending along the first direction, a portion of the plurality of second gate lines being spaced apart along the second direction in the first device region, and another portion being spaced apart along the second direction in the second device region.

9. The ESD protection circuit of claim 1, wherein, The trigger circuit includes: a capacitor, a first end of the capacitor being electrically connected to the positive pole of the power supply, and a second end of the capacitor being electrically connected to the first gate; and a second resistor, a first end of the second resistor being electrically connected to the second end of the capacitor and the first gate, and a second end of the second resistor being electrically connected to the negative pole of the power supply.

10. An electronic device, comprising: The application further provides an ESD protection circuit comprising: The ESD protection circuit according to any one of claims 1-9.

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