Circuit for reducing inrush current

Abstract

The utility model discloses a circuit of reducing inrush current, and the circuit of reducing inrush current is connected with bridge rectifier circuit and flyback control circuit in switching power supply circuit, bridge rectifier circuit includes rectifier bridge and first capacitor, the positive pole of first capacitor is connected rectifier bridge's positive pole output end, the negative pole of first capacitor is connected rectifier bridge's negative pole output end, and the two alternating current input ports of rectifier bridge are connected with the fire line and zero line of commercial power respectively, the circuit of reducing inrush current includes switch and first resistance: switch and first resistance are set up in parallel between the negative pole of first capacitor and the negative pole output end of rectifier bridge, and the sixth pin of control chip in flyback control circuit is also connected with switch, and the fifth pin of control chip is connected with the positive pole output end of rectifier bridge. Both can reduce inrush current, and when the resistance of first resistance is too large, the impedance in the loop of rectifier bridge and first capacitor is too large, and the charging of first capacitor is influenced.

Description

Technical Field

[0001] This utility model relates to the field of circuit technology, and in particular to a circuit for reducing surge current. Background Technology

[0002] When a switching power supply is plugged into a socket or turned on, a large inrush current is generated the instant the circuit is connected. Although this inrush current has a short duration, its peak value is very high. In some high-power switching power supplies, UPS and other power conversion equipment, the instantaneous inrush current can reach more than 100 times its operating current, which can damage electronic components. Utility Model Content

[0003] The problem to be solved by this invention is to provide a circuit that reduces surge current.

[0004] This utility model provides a circuit for reducing surge current, which is applied in a switching power supply circuit. The circuit for reducing surge current is connected to the bridge rectifier circuit and the flyback control circuit in the switching power supply circuit. The bridge rectifier circuit includes a rectifier bridge BD1 and a first capacitor C1. The positive terminal of the first capacitor C1 is connected to the positive output terminal of the rectifier bridge BD1, and the negative terminal of the first capacitor C1 is connected to the negative output terminal of the rectifier bridge BD1. The two AC input ports of the rectifier bridge BD1 are respectively connected to the live wire and the neutral wire of the mains power.

[0005] The circuit for reducing surge current includes a switch Q1 and a first resistor R1: the switch Q1 and the first resistor R1 are connected in parallel between the negative terminal of the first capacitor C1 and the negative output terminal of the rectifier bridge BD1, and the switch Q1 is also connected to the sixth pin of the control chip U2 in the flyback control circuit so that the switch Q1 is controlled and driven by the control chip U2, and the fifth pin of the control chip U2 is connected to the positive output terminal of the rectifier bridge BD1.

[0006] In some embodiments, the number of switches Q1 is set to one or more.

[0007] In some embodiments, the switch Q1 includes one of a MOSFET, a thyristor, a transistor, and a relay.

[0008] In some embodiments, the switch Q1 is an N-channel MOSFET, the drain of the N-channel MOSFET is connected to the negative terminal of the first capacitor C1, the source of the N-channel MOSFET is connected to the negative output terminal of the rectifier bridge BD1, and the gate of the N-channel MOSFET is connected to the sixth pin of the control chip U2.

[0009] In some embodiments, the circuit for reducing surge current further includes a ninth capacitor C9 and a fifth resistor R5; the first end of the ninth capacitor C9 is simultaneously connected to the sixth pin of the control chip U2, the gate of the N-channel MOSFET, and the first end of the fifth resistor R5, and the second end of the ninth capacitor C9 is simultaneously connected to the negative output terminal of the rectifier bridge BD1, the source of the N-channel MOSFET, one end of the first resistor R1, and the second end of the fifth resistor R5.

[0010] In some embodiments, the circuit for reducing surge current further includes an NPN transistor Q2 and a PNP transistor Q4; the collector of the NPN transistor Q2 is connected to the positive voltage terminal VCC, the emitter of the NPN transistor Q2 is connected to both the gate of the N-channel MOSFET and the emitter of the PNP transistor Q4, the collector of the PNP transistor Q4 is grounded, and the bases of both the NPN transistor Q2 and the PNP transistor Q4 are connected to the sixth pin of the control chip U2.

[0011] In some embodiments, the circuit for reducing surge current further includes a first diode D1 and a fourteenth resistor R14; the first diode D1 and the fourteenth resistor R14 are connected in series between the sixth pin of the control chip U2 and the base of the PNP transistor Q4 and the base of the NPN transistor Q2.

[0012] In some embodiments, the circuit for reducing surge current further includes an eighth resistor R8, which is connected in series between the sixth pin of the control chip U2 and the gate of the N-channel MOSFET.

[0013] In some embodiments, the circuit for reducing surge current further includes a Zener diode ZD1; the positive terminal of the Zener diode ZD1 is connected to both the source of the N-channel MOSFET and the second terminal of the ninth capacitor C9, and the negative terminal of the Zener diode ZD1 is connected to both the gate of the N-channel MOSFET and the first terminal of the ninth capacitor C9.

[0014] In some embodiments, the resistance value of the first resistor R1 is Vac*1.414 / I; where I is the maximum surge current value generated in the switching power supply circuit when the first resistor R1 is not set, and Vac is the connected AC voltage.

[0015] The beneficial effects of this invention are as follows: AC mains power is rectified into DC power by a bridge rectifier circuit to supply power to the load devices in the switching power supply circuit. This results in a large inrush current being generated the instant the circuit is switched on. By placing a first resistor R1 between the negative terminal of the first capacitor C1 and the negative output terminal of the rectifier bridge BD1, according to Ohm's law I = U / R, the inrush current generated in the loop can be reduced, protecting the electronic components in the loop. Simultaneously, a switch Q1 connected in parallel with the first resistor R1 is placed between the negative terminal of the first capacitor C1 and the negative output terminal of the rectifier bridge BD1, and the switch Q1 is controlled and driven by the control chip U2 in the flyback control circuit. When the switching power supply circuit is working, the control chip U2 in the flyback control circuit outputs a PWM or PFM signal to drive the switch Q1 to turn on. In this way, while reducing the inrush current in the loop, the loop impedance between the rectifier bridge BD1 and the first capacitor C1 is minimized after the switching power supply circuit starts working. This not only reduces the inrush current, but also avoids the first resistor R1 being too large, which would cause the loop impedance between the rectifier bridge BD1 and the first capacitor C1 to be too large, thus affecting the charging of the first capacitor C1. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A partial structural diagram of the circuit for reducing surge current provided in this embodiment of the present invention applied in a switching power supply circuit;

[0018] Figure 2 The overall structure diagram of the circuit for reducing surge current provided in this embodiment of the present invention applied in a switching power supply circuit. Detailed Implementation

[0019] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0020] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and, or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and, or collections thereof.

[0021] It should also be noted that, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "joining," "fixing," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. When an component is referred to as being "on" or "below" another component, the component can be located "directly" or "indirectly" on the other component, or there may be one or more intermediary components. The terms "first," "second," "third," etc., are only for the convenience of describing this technical solution and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0022] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0023] It should also be further understood that the terms "and" and "or" as used in this specification and the appended claims refer to any combination of one or more of the associated listed items and all possible combinations, and include such combinations.

[0024] like Figure 1 and Figure 2 As shown, this utility model discloses a circuit for reducing surge current, which is applied in a switching power supply circuit. The circuit for reducing surge current is connected to the bridge rectifier circuit and the flyback control circuit in the switching power supply circuit. The bridge rectifier circuit includes a rectifier bridge BD1 and a first capacitor C1. The positive terminal of the first capacitor C1 is connected to the positive output terminal of the rectifier bridge BD1, and the negative terminal of the first capacitor C1 is connected to the negative output terminal of the rectifier bridge BD1. The two AC input ports of the rectifier bridge BD1 are respectively connected to the live wire and the neutral wire of the mains power.

[0025] The circuit for reducing surge current includes a switch Q1 and a first resistor R1: the switch Q1 and the first resistor R1 are connected in parallel between the negative terminal of the first capacitor C1 and the negative output terminal of the rectifier bridge BD1, and the switch Q1 is also connected to the sixth pin of the control chip U2 in the flyback control circuit so that the switch Q1 is controlled and driven by the control chip U2, and the fifth pin of the control chip U2 is connected to the positive output terminal of the rectifier bridge BD1.

[0026] Specifically, rectifier bridge BD1 is used for rectification. The negative terminal of the first capacitor C1 is also connected to ground. The first capacitor C1 is used for filtering and energy storage. The first end of the first resistor R1 is connected to the negative terminal of the first capacitor C1, and the second end of the first resistor R1 is connected to the negative output terminal of rectifier bridge BD1. The first terminal of switch Q1 is simultaneously connected to the first terminal of the first resistor R1, the negative terminal of the first capacitor C1, and ground. The second terminal of switch Q1 is simultaneously connected to the second terminal of the first resistor R1 and the negative output terminal of rectifier bridge BD1, so that switch Q1 and the first resistor R1 are connected in parallel between the negative terminal of the first capacitor C1 and the negative output terminal of rectifier bridge BD1. The AC mains power is rectified into DC power by the bridge rectifier circuit and then supplies power to the load device in the switching power supply circuit. That is, a large inrush current is generated at the moment the circuit is turned on. Because a first resistor R1 is placed between the negative terminal of the first capacitor C1 and the negative output terminal of the rectifier bridge BD1, according to Ohm's law I=U / R, the surge current generated in the loop can be reduced, protecting the electronic components in the loop. Simultaneously, a switch Q1 is placed in parallel with the first resistor R1 between the negative terminal of the first capacitor C1 and the negative output terminal of the rectifier bridge BD1, and the switch Q1 is controlled and driven by the control chip U2 in the flyback control circuit. When the switching power supply circuit is working, the control chip U2 in the flyback control circuit outputs a PWM or PFM signal to drive the switch Q1 to conduct. Thus, while reducing the surge current in the loop, the loop impedance between the rectifier bridge BD1 and the first capacitor C1 is minimized after the switching power supply circuit starts working. This reduces the surge current and avoids the first resistor R1 being too large, which would cause excessive impedance in the loop between the rectifier bridge BD1 and the first capacitor C1, affecting the charging of the first capacitor C1.

[0027] In a specific embodiment, the number of switches Q1 is set to one or more. The surge current reduction circuit can be applied to higher power switching power supply circuits by increasing the number of switches Q1. When multiple switches Q1 are used, they are connected in series.

[0028] In a specific embodiment, the switch Q1 includes one of a MOSFET, a thyristor, a transistor, and a relay, which can be selected according to actual needs.

[0029] In one specific embodiment, the switch Q1 is an N-channel MOSFET, the drain of the N-channel MOSFET is connected to the negative terminal of the first capacitor C1, the source of the N-channel MOSFET is connected to the negative output terminal of the rectifier bridge BD1, and the gate of the N-channel MOSFET is connected to the sixth pin of the control chip U2.

[0030] In this circuit, the drain of the N-channel MOSFET is the first terminal of the open-circuit transistor Q1, and the source of the N-channel MOSFET is the second terminal of the open-circuit transistor Q1. The sixth pin of the control chip U2 is its PWM signal output pin, and the fifth pin of the control chip U2 is its power supply pin. When the switching power supply is plugged into the socket or powered on, the loop between the rectifier bridge BD1 and the first capacitor C1 is closed. Because the resistance of the first resistor R1 is relatively large (where R1 = Vac * 1.414 / I), where I is the maximum inrush current generated in the switching power supply circuit without the first resistor R1, and Vac is the AC voltage connected to the mains, the first resistor R1 can reduce the inrush current in the loop between the rectifier bridge BD1 and the first capacitor C1, thus providing protection. The DC power rectified by the rectifier bridge BD1 is supplied to the control chip U2 through the fifth pin, enabling it to start working. The control chip U2 outputs a PWM signal through its sixth pin to drive the N-channel MOSFET to turn on, thereby reducing the impedance in the loop between the rectifier bridge BD1 and the first capacitor C1 and avoiding affecting the charging of the first capacitor C1 by the loop.

[0031] In a specific embodiment, the circuit for reducing surge current further includes a ninth capacitor C9 and a fifth resistor R5; the first end of the ninth capacitor C9 is simultaneously connected to the sixth pin of the control chip U2, the gate of the N-channel MOSFET, and the first end of the fifth resistor R5, and the second end of the ninth capacitor C9 is simultaneously connected to the negative output terminal of the rectifier bridge BD1, the source of the N-channel MOSFET, one end of the first resistor R1, and the second end of the fifth resistor R5.

[0032] The ninth capacitor C9 and the fifth resistor R5 are designed to ensure that the N-channel MOSFET, i.e., switch Q1, can work continuously after the switching power supply circuit is turned on, and to ensure that switch Q1 can be quickly turned off and not conduct after the switching power supply is turned off, i.e. after the switching power supply circuit is disconnected from the mains power, thus avoiding excessive surge current caused by switch Q1 still conducting when the mains power is connected again in a short time.

[0033] In a specific embodiment, the circuit for reducing surge current further includes an NPN transistor Q2 and a PNP transistor Q4; the collector of the NPN transistor Q2 is connected to the positive voltage terminal VCC, the emitter of the NPN transistor Q2 is connected to both the gate of the N-channel MOSFET and the emitter of the PNP transistor Q4, the collector of the PNP transistor Q4 is grounded, and the bases of both the NPN transistor Q2 and the PNP transistor Q4 are connected to the sixth pin of the control chip U2.

[0034] In this embodiment, NPN transistor Q2 and PNP transistor Q4 form a totem pole. The emitter of NPN transistor Q2 is also connected to the first terminal of the fifth resistor R5 and the first terminal of the ninth capacitor C9. The emitter of PNP transistor Q4 is also connected to the gate of the N-channel MOSFET, the first terminal of the fifth resistor R5, and the first terminal of the ninth capacitor C9. When the PWM signal output from the sixth pin of control chip U2 is high, NPN transistor Q2 is turned on and PNP transistor Q4 is turned off; when the PWM signal output from the sixth pin of control chip U2 is low, NPN transistor Q2 is turned off and PNP transistor Q4 is turned on. The totem pole formed by NPN transistor Q2 and PNP transistor Q4 provides a higher current output capability to drive switch Q1.

[0035] In a specific embodiment, the circuit for reducing surge current further includes a first diode D1 and a fourteenth resistor R14; the first diode D1 and the fourteenth resistor R14 are connected in series between the sixth pin of the control chip U2 and the base of the PNP transistor Q4 and the base of the NPN transistor Q2.

[0036] In this configuration, the anode of the first diode D1 is connected to the sixth pin of the control chip U2, and the anode of the first diode D1 is connected to the first terminal of the fourteenth resistor R14. The second terminal of the fourteenth resistor R14 is connected to the base of the NPN transistor Q2 and the base of the PNP transistor Q4. The fourteenth resistor R14 is used for current limiting and voltage regulation, and the first diode D1 is used for voltage regulation.

[0037] In a specific embodiment, the circuit for reducing surge current further includes an eighth resistor R8, which is connected in series between the sixth pin of the control chip U2 and the gate of the N-channel MOS transistor.

[0038] The first terminal of the eighth resistor R8 is connected to the base of the PNP transistor Q4, the base of the NPN transistor Q2, and the second terminal of the fourteenth resistor R14. The second terminal of the eighth resistor R8 is connected to the gate of the N-channel MOSFET Q1. The eighth resistor R8 is used to increase damping in the circuit and prevent ringing.

[0039] In other embodiments, the PNP transistor Q4 and NPN transistor Q2 may not be provided, that is, the first end of the eighth resistor R8 is only connected to the second end of the fourteenth resistor R14.

[0040] In a specific embodiment, the circuit for reducing surge current further includes a Zener diode ZD1, the anode of which is connected to both the source of the N-channel MOSFET and the second terminal of the ninth capacitor C9. The cathode of the Zener diode ZD1 is connected to both the gate of the N-channel MOSFET and the first terminal of the ninth capacitor C9.

[0041] The positive terminal of Zener diode ZD1 is connected to the second terminal of the first resistor R1 and the second terminal of the fifth resistor R5, while the negative terminal of Zener diode ZD1 is connected to the first terminal of the fifth resistor R5, the emitter of the NPN transistor Q2, and the second terminal of the eighth resistor R8. Zener diode ZD1 is used to prevent the voltage at the positive voltage terminal VCC from being too high and damaging the switch Q1, thereby improving the stability and safety of the circuit.

[0042] The above are merely specific embodiments of this utility model, but the protection scope of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A circuit for reducing inrush current, applied in a switching power supply circuit, characterized in that, The circuit for reducing surge current is connected to the bridge rectifier circuit and the flyback control circuit in the switching power supply circuit. The bridge rectifier circuit includes a rectifier bridge (BD1) and a first capacitor (C1). The positive terminal of the first capacitor (C1) is connected to the positive output terminal of the rectifier bridge (BD1), and the negative terminal of the first capacitor (C1) is connected to the negative output terminal of the rectifier bridge (BD1). The two AC input ports of the rectifier bridge (BD1) are respectively connected to the live wire and the neutral wire of the mains power. The circuit for reducing surge current includes a switch (Q1) and a first resistor (R1): the switch (Q1) and the first resistor (R1) are connected in parallel between the negative terminal of the first capacitor (C1) and the negative output terminal of the rectifier bridge (BD1), and the switch (Q1) is also connected to the sixth pin of the control chip (U2) in the flyback control circuit so that the switch (Q1) is controlled and driven by the control chip (U2), and the fifth pin of the control chip (U2) is connected to the positive output terminal of the rectifier bridge (BD1).

2. The circuit for reducing surge current according to claim 1, characterized in that, The number of switches (Q1) is set to one or more.

3. The circuit for reducing surge current according to claim 1, characterized in that, The switch (Q1) includes one of the following: MOSFET, thyristor, transistor, and relay.

4. The circuit for reducing surge current according to claim 1, characterized in that, The switch (Q1) is an N-channel MOS transistor. The drain of the N-channel MOS transistor is connected to the negative terminal of the first capacitor (C1), the source of the N-channel MOS transistor is connected to the negative output terminal of the rectifier bridge (BD1), and the gate of the N-channel MOS transistor is connected to the sixth pin of the control chip (U2).

5. The circuit for reducing surge current according to claim 4, characterized in that, The circuit for reducing surge current also includes a ninth capacitor (C9) and a fifth resistor (R5); the first end of the ninth capacitor (C9) is connected to the sixth pin of the control chip (U2), the gate of the N-channel MOSFET, and the first end of the fifth resistor (R5); the second end of the ninth capacitor (C9) is connected to the negative output terminal of the rectifier bridge (BD1), the source of the N-channel MOSFET, one end of the first resistor (R1), and the second end of the fifth resistor (R5).

6. The circuit for reducing surge current according to claim 5, characterized in that, The circuit for reducing surge current also includes an NPN transistor (Q2) and a PNP transistor (Q4); the collector of the NPN transistor (Q2) is connected to the positive voltage terminal (VCC), the emitter of the NPN transistor (Q2) is connected to both the gate of the N-channel MOSFET and the emitter of the PNP transistor (Q4), the collector of the PNP transistor (Q4) is grounded, and the bases of both the NPN transistor (Q2) and the PNP transistor (Q4) are connected to the sixth pin of the control chip (U2).

7. The circuit for reducing surge current according to claim 6, characterized in that, The circuit for reducing surge current also includes a first diode (D1) and a fourteenth resistor (R14); the first diode (D1) and the fourteenth resistor (R14) are connected in series between the sixth pin of the control chip (U2) and the base of the PNP transistor (Q4) and the base of the NPN transistor (Q2).

8. The circuit for reducing surge current according to claim 5, characterized in that, The circuit for reducing surge current also includes an eighth resistor (R8), which is connected in series between the sixth pin of the control chip (U2) and the gate of the N-channel MOSFET.

9. The circuit for reducing surge current according to claim 5, characterized in that, The circuit for reducing surge current also includes a Zener diode (ZD1); the positive terminal of the Zener diode (ZD1) is connected to both the source of the N-channel MOSFET and the second terminal of the ninth capacitor (C9), and the negative terminal of the Zener diode (ZD1) is connected to both the gate of the N-channel MOSFET and the first terminal of the ninth capacitor (C9).

10. The circuit for reducing surge current according to claim 1, characterized in that, The resistance value of the first resistor (R1) is Vac*1.414 / I; where I is the maximum surge current generated in the switching power supply circuit when the first resistor (R1) is not set, and Vac is the AC voltage connected.

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