A vibration suppression system for motor servo control
By using a combination of accelerometer, spectrum analysis chip and FPGA chip in the motor servo system to generate anti-phase compensation signal, the problems of mechanical vibration and signal distortion are solved, achieving high-precision and low-noise vibration suppression effect, and improving system integration and power consumption performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NORTHERN INST OF AUTOMATIC CONTROL TECH
- Filing Date
- 2025-07-24
- Publication Date
- 2026-06-05
Smart Images
Figure CN224329401U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of motor control technology, and in particular to a vibration suppression system for motor servo control. Background Technology
[0002] In the fields of industrial automation and precision control, motor servo systems are widely used in high-precision equipment such as machine tools and robots. However, mechanical vibrations caused by factors such as insufficient rigidity of the mechanical transmission chain, load disturbances, or electromagnetic excitation during motor operation can lead to problems such as decreased machining accuracy and shortened equipment lifespan. Traditional vibration suppression solutions often employ active control strategies based on software algorithms, such as notch filters or adaptive control algorithms. However, these methods suffer from drawbacks such as poor real-time performance, reliance on precise mathematical models, and dynamic response lag.
[0003] In existing technologies, when vibration signals are collected by deploying an accelerometer on the motor output shaft, insufficient rigidity of the sensor mounting structure or poor contact with the coupling often results in a large amount of noise interference in the vibration signal, affecting the accuracy of subsequent processing. Furthermore, if the electrical connection between the signal processing module and the compensation module lacks anti-interference design, it is easily contaminated by high-frequency switching noise from the servo driver, leading to distortion of the compensation signal. For example, the combination of a digital phase-locked loop and a waveform generator, commonly seen in published literature, can generate an inverse compensation signal, but because no isolation or shielding measures are set in the signal transmission path, the compensation signal is susceptible to common-mode interference, making accurate cancellation difficult.
[0004] On the other hand, in the existing hardware architecture of vibration suppression systems, the signal processing unit and the compensation control unit are mostly implemented using discrete components, resulting in low circuit integration, high power consumption, and difficulty in adapting to the dynamic adjustment requirements under different load conditions. Utility Model Content
[0005] This application proposes a vibration suppression system for motor servo control, which is used to solve the vibration problem that occurs during motor servo control.
[0006] This application proposes a vibration suppression system for motor servo control, applied to a servo motor. The servo motor includes a motor output shaft and a servo driver. The system includes a vibration detection module, a signal processing terminal, and a compensation and suppression module. The output terminal of the vibration detection module is electrically connected to the input terminal of the signal processing terminal, the output terminal of the signal processing terminal is electrically connected to the input terminal of the compensation and suppression module, and the output terminal of the compensation and suppression module is electrically connected to the servo driver. The vibration detection module is fixedly installed on the motor output shaft.
[0007] The vibration detection module is equipped with an acceleration sensor, which is used to detect vibration signals.
[0008] The compensation and suppression module includes an FPGA chip, a digital phase-locked loop (PLL), and a waveform generator. The input of the FPGA chip is electrically connected to the SPI port of the signal processing unit, and the output of the FPGA chip is electrically connected to the waveform generator. The input of the PLL is electrically connected to the output of the servo driver, and the output of the PLL is electrically connected to the input of the waveform generator. The waveform generator is electrically connected to the current loop reference interface of the servo driver.
[0009] This application acquires vibration signals through the acceleration sensor of the vibration detection module, determines the harmonic components caused by the vibration signals through spectrum analysis of the signal processing terminal, and then analyzes the real-time phase of the motor rotor through the FPGA chip of the compensation and suppression module and the digital phase-locked loop / waveform generator. Based on the phase signal output by the phase-locked loop, a compensation voltage waveform that is out of phase with the vibration signal is generated and superimposed on the original control signal to eliminate mechanical vibration and achieve real-time vibration suppression.
[0010] In conjunction with the first aspect, the acceleration sensor is fixed to the outside of the coupling between the motor output shaft and the load end of the servo motor by an elastic clamp; wherein the elastic clamp has an internal insulating pad.
[0011] This application achieves stable installation and electrical isolation of the accelerometer by using elastic clamps and insulating pads, thus solving the problems of signal distortion caused by insufficient sensor installation rigidity and electromagnetic interference introduced by metal contact.
[0012] In conjunction with the first aspect, the insulating pad is made of multi-layer composite ceramic material.
[0013] The elastic clamp of this application has a curved surface structure and an array of elastic protrusions, which can self-adapt to clamping. The multi-layer composite ceramic gasket improves the insulation performance, avoids the installation stress concentration caused by the irregular shape design of the coupling, and prevents insulation failure under high temperature environment.
[0014] In conjunction with the first aspect, the signal processing terminal is equipped with a spectrum analysis chip; wherein, the SPI control terminal of the spectrum analysis chip is connected to the output terminal of the accelerometer through a first analog-to-digital converter.
[0015] This application uses a dedicated spectrum analysis chip and an analog-to-digital converter to achieve rapid frequency domain analysis of vibration signals.
[0016] In conjunction with the first aspect, the front end of the spectrum analysis chip is equipped with an analog bandpass filter connected in parallel. The cutoff frequency range of the analog bandpass filter covers the fundamental frequency and its second harmonic frequency corresponding to the rated speed of the motor.
[0017] This application sets an analog bandpass filter at the front end of the spectrum analysis chip to limit the processing frequency band to the motor fundamental frequency and its second harmonic range, thereby avoiding noise interference across the entire frequency band, improving the accuracy of spectrum analysis, and preventing inaccurate vibration feature extraction.
[0018] In conjunction with the first aspect, the output terminal of the accelerometer is connected to the first analog-to-digital converter via differential signal lines; wherein, the differential signal lines are twisted-pair shielded cables.
[0019] The accelerometer-to-analog-to-digital converter in this application uses a twisted-pair shielded differential signal line, which prevents electromagnetic induction noise from polluting the analog signal during long-distance transmission.
[0020] In conjunction with the first aspect, the FPGA chip includes a first bank1 and a second bank2, wherein an isolation voltage is provided between the first bank1 and the second bank2, the first bank1 is configured with a first IO pin group, and the second bank2 is configured with a second IO pin group;
[0021] The first IO pin group is connected to the phase feedback input of the digital phase-locked loop via a 16-bit parallel data bus, wherein the bit feedback input is electrically connected to the data bit and clock bit of the 16-bit parallel data bus.
[0022] The second I / O pin group is connected to the parameter configuration terminal of the waveform generator via an 8-bit synchronous serial bus, which is a signal line based on the SPI protocol.
[0023] The FPGA chip of this application features IO pin grouping and a parallel / serial bus architecture that solves timing conflicts and signal crosstalk caused by traditional single-bus hybrid transmission. It can also generate compensation signals through a built-in compensation calculation mechanism.
[0024] In conjunction with the first aspect, the power supply circuit of the FPGA chip includes an independent isolated power supply module. The secondary winding of the isolated power supply module is led out using twisted-pair shielded wire, and a transient suppression diode is connected in parallel at the power input terminal.
[0025] The FPGA chip in this application uses an independent isolated power supply module and transient suppression diodes to prevent FPGA logic errors caused by switching power supply ripple coupling.
[0026] In conjunction with the first aspect, the output terminal of the waveform generator is electrically connected to the current loop reference interface of the servo driver via a coaxial signal line;
[0027] The inner core of the coaxial signal line transmits the compensation voltage signal, the outer shielding layer is connected to the system ground, and the input end of the coaxial signal line is electrically connected to the output end of the waveform generator through a signal buffer.
[0028] The waveform generator output of this application transmits the compensation signal through a coaxial signal line. The outer shielding layer is grounded, and the compensation signal is modulated by the switching noise of the servo driver during transmission.
[0029] In conjunction with the first aspect, the signal buffer is implemented using a rail-to-rail operational amplifier, and an adjustable resistor network is connected in series in the feedback loop of the signal buffer. The adjustment terminal of the adjustable resistor network is electrically connected to the gain control pin of the spectrum analysis chip.
[0030] The signal buffer of this application integrates an adjustable resistor network, which is linked with the gain control of the spectrum analysis chip to prevent the compensation signal from being overloaded or insufficient due to the inability of the fixed gain to adapt to the dynamic changes in vibration amplitude.
[0031] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.
[0032] The technical solution of this utility model will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0033] The accompanying drawings are provided to further understand the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation thereof.
[0034] In the attached diagram:
[0035] Figure 1 This is a diagram showing the composition of the vibration suppression system for motor servo control in this embodiment of the present invention;
[0036] Figure 2 This is a diagram showing the fixed assembly of the accelerometer in an embodiment of this utility model;
[0037] Figure 3 This is a schematic diagram illustrating the vibration suppression process of the motor servo control vibration suppression system in this embodiment of the present invention. Detailed Implementation
[0038] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.
[0039] In the existing servo motor 4, during operation, such as in the case of tightening screws, the motor output shaft 41 is connected to the tightener through a gear reducer. As a result, there is a meshing gap in the gear reducer. During the switching between forward and reverse rotation of the servo motor 4, there will be a free stroke. At the same time, due to the gap problem, vibration will be generated. If the vibration can be suppressed, the forward and reverse rotation process will be more stable, and the tightening process will be more stable.
[0040] Example 1:
[0041] See Figure 1 and Figure 3 This application proposes a vibration suppression system for motor servo control, applied to a servo motor 4. The servo motor 4 includes a motor output shaft 41 and a servo driver 42. The system includes a vibration detection module 1, a signal processing terminal 2, and a compensation and suppression module 3. The output terminal of the vibration detection module 1 is electrically connected to the input terminal of the signal processing terminal 2, the output terminal of the signal processing terminal 2 is electrically connected to the input terminal of the compensation and suppression module 3, and the output terminal of the compensation and suppression module 3 is electrically connected to the servo driver 42. The vibration detection module 1 is fixedly installed on the motor output shaft 41.
[0042] The vibration detection module 1 is equipped with an acceleration sensor 10, which is used to detect vibration signals.
[0043] The compensation and suppression module 3 includes an FPGA chip 31, a digital phase-locked loop 32, and a waveform generator 33. The input terminal of the FPGA chip 31 is electrically connected to the SPI port of the signal processing terminal 2, and the output terminal of the FPGA chip 31 is electrically connected to the waveform generator 33. The input terminal of the digital phase-locked loop 32 is electrically connected to the output terminal of the servo driver 42, and the output terminal of the digital phase-locked loop 32 is electrically connected to the input terminal of the waveform generator 33. The waveform generator 33 is electrically connected to the current loop reference interface of the servo driver 42.
[0044] The vibration detection module 1 collects the vibration signal of the motor output shaft in real time through the accelerometer 10. The accelerometer 10 is rigidly fixed to the end of the motor output shaft 41 by an M3 screw, and mainly detects the axial vibration acceleration signal.
[0045] The vibration signal is received by the first analog-to-digital converter 22 of the signal processing terminal 2, and then the frequency domain analysis of the vibration signal is performed by the spectrum analysis chip 21 to extract the fundamental frequency and harmonic components. The analysis results are transmitted to the compensation and suppression module 3 through the SPI interface. In the actual implementation process, the SPI interface will output the vibration signal after the vibration detection module 1 is converted, and the vibration frequency and amplitude characteristics are determined according to the fundamental frequency and harmonic components.
[0046] The compensation and suppression module 3 primarily utilizes an FPGA chip 31, preferably a low-power chip from the Xilinx Artix-7 series, and integrates a digital phase-locked loop 32 and a waveform generator 33. After receiving the spectrum analysis results, the FPGA chip 31 uses the digital phase-locked loop 32, based on a 16-bit parallel bus 312, to acquire the real-time phase information of the motor rotor, serving as a reference for the vibration frequency. The waveform generator 33 generates a compensation voltage waveform out of phase with the vibration signal, based on the phase signal output by the phase-locked loop and the compensation current signal generated by the FPGA chip 31, which is in the same frequency but out of phase with the vibration signal. This compensation voltage is transmitted via a coaxial signal line, after DA conversion, to the current loop input interface of the servo driver, where it is superimposed on the original control signal, thereby canceling out the mechanical vibration.
[0047] Example 2:
[0048] See Figure 2 The acceleration sensor 10 of this application is fixed to the outside of the coupling 43 between the motor output shaft and the load end by an elastic clamp 12; wherein the elastic clamp 12 has an internal insulating pad.
[0049] See Figure 1 and Figure 2 The acceleration sensor 10 of this application is fixed to the connection between the motor output shaft and the coupling by an elastic clamp 12. In a specific implementation, the elastic clamp 12 is a split stainless steel structure, with two clamping arms locked by spring bolts. The inner side of the clamping arms is in contact with the outer surface of the coupling. Other clamps with the same technical effect can also be used.
[0050] An insulating gasket is embedded inside the clamp. The insulating gasket is made of epoxy resin-based composite material with a thickness of 1.5 mm and covers the contact surface between the clamp and the coupling. During installation, the insulating gasket is first pasted onto the outer wall of the coupling 43, and then the elastic clamp is placed on the outside of the gasket and the bolts are tightened so that the sensing surface of the acceleration sensor 10 is axially perpendicular to the motor shaft.
[0051] Example 3:
[0052] In this application, the insulating gasket is made of multi-layer composite ceramic material. In practical implementation, the clamping surface of the elastic clamp 12 can also be set as a curved surface structure that matches the outer contour of the coupling 43, and an array of elastic protrusions can be arranged circumferentially on the curved surface structure. If the clamping surface of the elastic clamp 12 is machined into a concave curved surface that matches the outer contour of the coupling, the radius of curvature of the curved surface will be 0.5mm larger than the outer diameter of the coupling 43, forming a clearance fit. The elastic protrusions are evenly distributed on the curved surface, each protrusion using a hemispherical silicone structure with a diameter of 2mm, a height of 1mm, and a spacing of 5mm between adjacent protrusions. During installation, the elastic protrusions deform under pressure, generating a uniformly distributed clamping force, avoiding excessive local stress that could cause coupling deformation.
[0053] The insulating gasket 13 is a multi-layer composite structure, primarily consisting of three layers: an outer layer of alumina ceramic (0.2 mm thick), a middle layer of mica (0.5 mm thick), and a bottom layer of silicon nitride ceramic (0.3 mm thick). These three layers are sintered together at high temperature, allowing it to withstand temperatures up to 300°C. Therefore, the edge of the insulating gasket extends 2 mm beyond the clamp contact surface, forming a creepage barrier to prevent surface discharge.
[0054] Example 4:
[0055] See Figure 1 and Figure 3 The signal processing terminal 2 of this application is equipped with a spectrum analysis chip 21; wherein, the SPI control terminal of the spectrum analysis chip 21 is connected to the output terminal of the accelerometer 10 through the first analog-to-digital converter 22.
[0056] The spectrum analysis chip 21 of the signal processing terminal 2 is an ADIS16229, which has a built-in 1024-point FFT hardware accelerator. The analog signal output by the accelerometer 10 is sampled by the first analog-to-digital converter 22, converted into a 16-bit digital signal, and then transmitted to the spectrum analysis chip 21 through the SPI interface at a clock frequency of 10MHz. The first analog-to-digital converter 22 preferably uses the ADIS16229.
[0057] In practical implementation, the ADIS16229 performs a spectrum calculation every 50μs, extracts the three frequency components with the largest amplitude within the 0-5kHz frequency band, and stores the results in an internal register. The FPGA chip 31 reads the register data via the SPI bus and determines whether the vibration main frequency exceeds the allowable range based on a preset threshold.
[0058] Example 5:
[0059] See Figure 3 The spectrum analysis chip 21 is equipped with an analog bandpass filter 23 connected in parallel at the front end. The cutoff frequency range of the analog bandpass filter 23 includes the fundamental frequency and its second harmonic frequency corresponding to the rated speed of the motor. The fundamental frequency and the second harmonic of the motor can be targetedly acquired through the two-stage cascading of the analog bandpass filter 23 and the spectrum analysis chip 21.
[0060] This application connects an analog bandpass filter 23 in parallel at the input of the spectrum analysis chip 21. Its design parameters are determined based on the rated speed of the motor. Taking a rated speed of 3000 rpm and a corresponding fundamental frequency of 50 Hz as an example, the analog bandpass filter 23 adopts a second-order voltage-controlled voltage source (VCVS) structure, consisting of an operational amplifier, resistors, and capacitors. In actual implementation, the specific parameters can be configured as follows:
[0061] Low-frequency cutoff: 45Hz (fundamental frequency -10%);
[0062] High-frequency cutoff: 110Hz (second harmonic +10%);
[0063] Resistance R1 = R2 = 10kΩ;
[0064] Capacitor C1 = C2 = 33nF;
[0065] The analog bandpass filter input uses an RC network for signal preconditioning to suppress high-frequency glitches. In actual testing, this ensures that the spectrum analysis chip 21 only processes signals within the effective frequency band.
[0066] Example 6:
[0067] See Figure 3 The output terminal of the accelerometer 10 is connected to the first analog-to-digital converter 22 via a differential signal line 11. This differential signal line 11 is a twisted-pair shielded cable used to suppress noise during vibration signal detection. When transmitted via the twisted-pair cable, the interference source is common-mode noise induced on both wires with equal amplitude and phase. The differential signal line 11, through differential input, can cancel out the common-mode noise, leaving only the useful differential-mode vibration signal. This provides both isolation and active suppression.
[0068] The analog output terminal of the accelerometer 10 is connected to the first analog-to-digital converter 22 via a differential signal line 11. The characteristic impedance of the twisted-pair shielded cable is 120Ω, and its twist pitch is 10mm. It can be grounded to a single point on the metal casing of the signal processing terminal 2 via a 360° loop connection. However, in actual implementation, the length of the twisted-pair shielded cable should not exceed 1.5m. If it exceeds this length, an instrumentation amplifier needs to be added at the front end of the first analog-to-digital converter 22, with a gain set to 2 times to compensate for attenuation.
[0069] Example 7:
[0070] See Figure 3 The FPGA chip 31 includes a first bank 1 and a second bank 2, wherein an isolation voltage is provided between the first bank 1 and the second bank 2, the first bank 1 is configured with a first IO pin group 311, and the second bank 2 is configured with a second IO pin group 312.
[0071] The first IO pin group 311 is connected to the phase feedback input terminal of the digital phase-locked loop 32 through the 16-bit parallel data bus 313, wherein the phase feedback input terminal is electrically connected to the data bit and clock bit of the 16-bit parallel data bus 313.
[0072] The second IO pin group 312 is connected to the parameter configuration terminal of the waveform generator 33 via an 8-bit synchronous serial bus 314, which is a signal line based on the SPI protocol.
[0073] When the FPGA chip 31 receives a vibration signal, the digital logic core of the first bank 1 and the analog interface peripheral pins of the second bank 2 are powered by an isolated power supply to block ground loop noise. The 16-bit parallel data bus 313 of the first IO pin group 311 can update the data based on the phase feedback data, so that the phase error of the servo motor 4 within a 100μs period can be compensated in real time. The digital phase-locked loop 32 adjusts the output phase in real time through the feedback data, thereby adjusting the overall error.
[0074] The 8-bit synchronous serial bus 314 of the second IO pin group 312 generates a suppression command by configuring the parameters of the waveform generator 33. The suppression command includes dynamic adjustment data of the frequency, amplitude and phase of the vibration suppression waveform.
[0075] The deployment of the first bank1 and the second bank2 in this application physically isolates the high-speed digital logic processing inside the FPGA chip 31 from the low-speed analog data reception, thereby preventing noise cross-coding and improving the transmission speed of suppression instructions.
[0076] Example 8:
[0077] See Figure 3 Traditional vibration suppression systems suffer from ripple noise and transient overvoltages introduced into the FPGA power supply circuit during power fluctuations, potentially leading to logic errors. To address this, the FPGA chip 31's power supply circuit utilizes an independent isolated power supply module. The secondary winding of this module is led out using twisted-pair shielded wire, and a transient suppression diode is connected in parallel at the power input. In practical implementation, the independent isolated power supply module employs a high-frequency transformer, or the power supply module consists of an AC / DC isolated power supply and a DC / DC converter. The twisted-pair shielded wire ensures that the secondary output current flows in opposite directions within the twisted pair, and the electromotive forces induced by the external alternating magnetic field in the two wires are equal in magnitude and opposite in direction. This cancels out differential-mode interference, achieving end-to-end protection from the grid input to the FPGA chip, and simultaneously resolving issues of power supply noise, logic errors, and insufficient accuracy.
[0078] When using a high-frequency voltage transformer, the high-frequency transformer achieves electrical isolation between input and output, blocks common-mode noise and ground loop interference on the grid side, and prevents noise between different voltage domains.
[0079] If a combination of AC / DC isolated power supply and DC / DC converter is adopted, the AC / DC module converts 220VAC to 5VDC, which is then transmitted to the DC / DC module via twisted-pair shielded cable. The secondary side outputs 1.8V and 3.3V to each bank of the FPGA chip 31. Furthermore, a transient suppression diode is connected in parallel at the power input terminal, and a clamping voltage of 5.8V is set, with a response time of 1ps, absorbing 8 / 20μs waveforms and 600W surge energy, thereby preventing interference.
[0080] The addition of transient voltage suppression diodes is primarily based on actual measurement comparisons. Without transient voltage suppression diodes, the peak surge voltage at the power supply terminal reaches 12V; after adding them, it is limited to within 5.5V. The ripple factor of the isolation power supply module is reduced from 3% to 0.5%, and the false trigger rate of the FPGA internal logic is reduced from 10%. -4 Reduced to 10 -7 .
[0081] Example 9:
[0082] See Figure 3 The output of waveform generator 33 is electrically connected to the current loop reference interface of servo driver via a coaxial signal line; wherein, the inner core of the coaxial signal line transmits the compensation voltage signal, the outer shielding layer is connected to the system ground, and the input of the coaxial signal line is electrically connected to the output of waveform generator 33 via a signal buffer.
[0083] The output of the waveform generator 33 in this application is connected to the current loop interface of the servo driver via a coaxial cable. The inner core of the coaxial cable transmits the compensation voltage signal, and the outer shielding layer is directly connected to the signal processing terminal 2 and the grounding terminal of the driver at both ends via metal clamps, with a grounding loop resistance of <0.05Ω. A signal buffer is added to the input terminal to ensure that the compensation signal is not distorted and to eliminate signal reflection caused by impedance discontinuity.
[0084] Example 10:
[0085] See Figure 3 The signal buffer in this application is implemented using a rail-to-rail operational amplifier. An adjustable resistor network is connected in series in the feedback loop of the signal buffer, and the adjustment terminal of the adjustable resistor network is electrically connected to the gain control pin of the spectrum analysis chip 21.
[0086] In this application, a digital potentiometer is connected in series in the feedback loop of the signal buffer. The resistance value of the digital potentiometer is controlled by the gain control pin of the spectrum analysis chip 21 via I... 2 The C interface dynamically adjusts the signal. When the vibration amplitude exceeds the threshold (pre-set manually), the spectrum analysis chip 21 sends a signal to the FPGA chip 31. The FPGA chip 31 then gradually adjusts the feedback resistor from 1kΩ to 5kΩ, corresponding to an increase in the buffer gain from 1x to 5x, making multi-band vibration compensation more accurate.
[0087] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.
Claims
1. A vibration suppression system for servo control of a motor, applied to a servo motor (4), the servo motor (4) including a motor output shaft (41) and a servo driver (42), characterized in that, The system includes a vibration detection module (1), a signal processing terminal (2), and a compensation and suppression module (3). The output terminal of the vibration detection module (1) is electrically connected to the input terminal of the signal processing terminal (2), the output terminal of the signal processing terminal (2) is electrically connected to the input terminal of the compensation and suppression module (3), and the output terminal of the compensation and suppression module (3) is electrically connected to the servo driver (42). The vibration detection module (1) is fixedly installed on the motor output shaft (41). The vibration detection module (1) is equipped with an acceleration sensor (10), which is used to detect vibration signals; The compensation and suppression module (3) includes an FPGA chip (31), a digital phase-locked loop (32), and a waveform generator (33); wherein, the input terminal of the FPGA chip (31) is electrically connected to the SPI port of the signal processing terminal (2), the output terminal of the FPGA chip (31) is electrically connected to the waveform generator (33), the input terminal of the digital phase-locked loop (32) is electrically connected to the output terminal of the servo driver (42), and the output terminal of the digital phase-locked loop (32) is electrically connected to the input terminal of the waveform generator (33); the waveform generator (33) is electrically connected to the current loop reference interface of the servo driver (42).
2. The vibration suppression system for motor servo control as described in claim 1, characterized in that, The acceleration sensor (10) is fixed to the outside of the coupling (43) between the motor output shaft (41) and the load end of the servo motor (4) by an elastic clamp (12); wherein the elastic clamp (12) has an insulating pad inside.
3. The vibration suppression system for motor servo control as described in claim 2, characterized in that, The insulating pad is made of multi-layer composite ceramic material.
4. The vibration suppression system for motor servo control as described in claim 1, characterized in that, The signal processing terminal (2) is equipped with a spectrum analysis chip (21); wherein, the SPI control terminal of the spectrum analysis chip (21) is connected to the output terminal of the acceleration sensor (10) through the first analog-to-digital converter (22).
5. A vibration suppression system for motor servo control as described in claim 4, characterized in that, The spectrum analysis chip (21) is equipped with an analog bandpass filter (23) connected in parallel at the front end. The cutoff frequency range of the analog bandpass filter (23) includes the fundamental frequency and its second harmonic frequency corresponding to the rated speed of the motor.
6. The vibration suppression system for motor servo control as described in claim 1, characterized in that, The output terminal of the accelerometer (10) is connected to the first analog-to-digital converter (22) via a differential signal line (11); wherein the differential signal line (11) is a twisted-pair shielded wire.
7. The vibration suppression system for motor servo control as described in claim 1, characterized in that, The FPGA chip (31) includes a first bank1 and a second bank2, wherein an isolation voltage is provided between the first bank1 and the second bank2, the first bank1 is configured with a first IO pin group (311), and the second bank2 is configured with a second IO pin group (312). The first IO pin group (311) is connected to the phase feedback input of the digital phase-locked loop (32) through a 16-bit parallel data bus (313), wherein the phase feedback input is electrically connected to the data bit and clock bit of the 16-bit parallel data bus (313); The second IO pin group (312) is connected to the parameter configuration terminal of the waveform generator (33) via an 8-bit synchronous serial bus (314), which is a signal line based on the SPI protocol.
8. A vibration suppression system for motor servo control as described in claim 7, characterized in that, The power supply circuit of the FPGA chip (31) includes an independent isolated power supply module. The secondary winding of the isolated power supply module is led out with twisted shielded wire and a transient suppression diode is connected in parallel at the power input terminal.
9. A vibration suppression system for motor servo control as described in claim 1, characterized in that, The output of the waveform generator (33) is electrically connected to the current loop reference interface of the servo driver via a coaxial signal line. The inner core of the coaxial signal line transmits the compensation voltage signal, the outer shielding layer is connected to the system ground, and the input end of the coaxial signal line is electrically connected to the output end of the waveform generator (33) through the signal buffer.
10. A vibration suppression system for motor servo control as described in claim 9, characterized in that, The signal buffer is a rail-to-rail operational amplifier. An adjustable resistor network is connected in series in the feedback loop of the signal buffer. The adjustment terminal of the adjustable resistor network is electrically connected to the gain control pin of the spectrum analysis chip (21).