A system on chip
By introducing a performance monitoring unit into the system-on-a-chip, memory operation instructions are recorded and analyzed in real time, solving the problem of low efficiency in memory controller anomaly detection and achieving efficient memory access anomaly detection and resolution.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- PHYTIUM TECH CO LTD
- Filing Date
- 2025-07-02
- Publication Date
- 2026-06-09
AI Technical Summary
In a system-on-a-chip, the memory controller may experience abnormal situations such as instruction loss or instruction scheduling disorder, leading to abnormal memory operations. Existing technologies are unable to efficiently detect and resolve these problems.
A performance monitoring unit is introduced into the system-on-a-chip to record memory operation instructions through the port physical layer interface, enabling real-time monitoring and analysis, and providing instruction monitoring data for evaluating memory controller performance.
It improves the efficiency of detecting and resolving memory access anomalies, enabling timely detection and analysis of memory controller performance anomalies, and ensuring memory read/write efficiency and performance.
Smart Images
Figure CN224341880U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more particularly to a system-on-a-chip. Background Technology
[0002] In a system-on-a-chip (SoC), the memory controller is responsible for managing memory read and write operations, scheduling command streams, and ensuring efficient data transmission. As SoCs continue to grow in scale and the diversity of system tasks increases, the diversity and complexity of memory access requests also increase, leading to a corresponding increase in the workload of the memory controller.
[0003] In some cases, the memory controller may experience abnormal situations such as instruction loss or instruction scheduling errors, leading to corresponding memory operation anomalies. These memory operation anomalies often result in system malfunctions, and users can only discover the problem by using tools to test the entire system, which is a relatively inefficient method for troubleshooting. Utility Model Content
[0004] Based on the above-mentioned technical problems, this application provides a system-on-a-chip that can improve the efficiency of detecting and resolving memory access anomalies.
[0005] The first aspect of this application provides a system-on-a-chip, the system-on-a-chip including a memory subsystem; the memory subsystem including a memory controller and a performance monitoring unit; wherein the memory controller is connected to the performance monitoring unit through a port physical layer interface;
[0006] The performance monitoring unit is used to record the memory operation instructions output by the memory controller through the port physical layer interface to obtain instruction monitoring data; the instruction monitoring data is used to analyze the performance of the memory controller.
[0007] The system-on-a-chip (SoC) provided in this application includes a performance monitoring unit in the memory subsystem. The physical layer interface of the memory controller's port is connected to this performance monitoring unit. Based on this architecture, the performance monitoring unit can record the memory operation instructions output by the memory controller through the physical layer interface, obtaining instruction monitoring data. This instruction monitoring data can be used to analyze the performance of the memory controller. The aforementioned SoC implements real-time recording of memory operation instructions output by the memory controller. Based on the recorded instruction monitoring data, the performance of the memory controller can be analyzed in real time, or, in the event of a memory access anomaly, the instruction monitoring data can be used to efficiently verify whether the memory controller is malfunctioning, thereby improving the efficiency of detecting and resolving memory access anomalies.
[0008] In some implementations, the on-chip system further includes memory, and the memory subsystem further includes a port physical layer; one end of the port physical layer is connected to the port physical layer interface of the memory controller, and the other end of the port physical layer is connected to the memory. Based on this implementation, the access of the performance monitoring unit will not affect the operation of the original on-chip system architecture. The performance monitoring unit only records the memory operation instructions output by the memory controller through the port physical layer interface, and will not affect the sending of memory operation instructions output by the memory controller through the port physical layer interface to the port physical layer, thereby monitoring the memory controller's instructions without the system's awareness.
[0009] In some implementations, the system-on-a-chip further includes a processor connected to the memory controller via a data bus. Based on this architecture, the processor's memory access process can be monitored and recorded through a performance monitoring unit, facilitating the analysis of the processor's memory access performance and timely troubleshooting in case of anomalies.
[0010] In some implementations, the performance monitoring unit includes: an instruction parsing module for parsing memory operation instructions output by the memory controller to obtain instruction information; and a counting unit for counting and statistically analyzing the instruction information output by the instruction parsing module. Based on this implementation, efficient parsing and statistical analysis of memory operation instructions are achieved through the cooperation of the instruction parsing module and the counting unit.
[0011] In some implementations, the performance monitoring unit further includes a cache for storing instruction information output by the instruction parsing module. Based on this implementation, by setting up the cache, a buffer function is provided for data transmission between the instruction parsing module and the counting unit, enabling the instruction parsing module and the counting unit to perform instruction parsing and instruction information statistics smoothly.
[0012] In some implementations, the cache includes a first cache and a second cache. The first cache receives and stores instruction information output by the instruction parsing module. After the instruction information output by the instruction parsing module is stored in the first cache and a set time has elapsed, the instruction information stored in the first cache is transferred to the second cache. Based on this implementation, the performance monitoring unit in the on-chip system achieves buffering of instruction information through a two-level cache, and also achieves separate storage of different instructions through the two-level cache, thereby avoiding confusion between different instructions in the cache.
[0013] In some implementations, the performance monitoring unit further includes an event counting enable module. This module identifies event information based on instruction information sent from the first cache and the second cache, and sends a corresponding counting enable signal to the counting unit based on the received instruction information and / or the identified event information. Based on this implementation, accurate and efficient identification of memory access events is achieved through the event counting enable module.
[0014] In some implementations, the counting unit includes an instruction counter, an event counter, and an event duration counter; wherein the instruction counter is used to count instructions; the event counter is used to count events identified based on instruction information; and the event duration counter is used to record the duration of the events. Based on this implementation, by using different counters to count instructions, events, and event durations separately, the efficiency and accuracy of instruction counting can be improved.
[0015] In some implementations, the counting unit further includes registers corresponding to various instructions and events, used to store counting and statistical results, and / or to control the enabling and clearing of the counter. This storage method makes the counting and statistical results of instructions and events clear and concise, thereby facilitating the acquisition of statistical results for any instruction or event.
[0016] In some implementations, the performance monitoring unit further includes a performance analysis module, used to analyze the performance of the memory controller based on the counting and statistical results generated in the counting unit, and obtain performance analysis results. Based on this implementation, the system-on-a-chip can directly obtain the performance analysis results of the memory controller through the performance monitoring unit, thereby enabling timely detection of performance anomalies and memory access anomalies during memory controller operation, which helps ensure memory read / write efficiency and performance. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0018] Figures 1-3 These are schematic diagrams of the structures of several on-chip systems provided in the embodiments of this application.
[0019] Figures 4-6 These are schematic diagrams of the structures of several performance monitoring units provided in the embodiments of this application. Detailed Implementation
[0020] In a system-on-a-chip, the memory controller is responsible for managing memory read and write operations, scheduling command streams, and ensuring efficient data transmission.
[0021] Figure 1 A schematic diagram of a system-on-a-chip is shown.
[0022] See Figure 1 As shown, in a system-on-a-chip, the processor (CPU) is connected to the memory controller via a data bus. The memory controller is connected to the port physical layer (PHY) via DFI (DDR PHY Interface), and the port physical layer is then connected to the DDR memory.
[0023] In this on-chip system, when the processor needs to read or write data from memory, it sends a memory read / write request to the memory controller. After receiving the memory read / write request, the memory controller parses the memory read / write request, generates the corresponding memory operation instructions, and then sends the memory operation instructions to the memory through the port physical layer to realize the memory read / write operation, and then feeds back the read / write operation results to the processor.
[0024] During the above process, the memory controller sorts the memory read and write requests issued by the processor. The sorting rules are related to the scheduling policy. Then, under the conditions of following the memory read and write rules and memory read and write timing, the memory operation instructions that the memory can recognize are sent to the port physical layer through the DFI interface.
[0025] The memory read / write rules refer to the requirement that before performing read / write operations on memory, the corresponding memory row must be activated (by sending the Activate command), and after the operation is completed, the corresponding memory row must be precharged (by sending the Precharge command). The memory read / write timing refers to the requirement that memory must adhere to a certain time interval between receiving different memory operation instructions to ensure data correctness. Additionally, memory rows must be periodically refreshed (by sending the Refresh command) to maintain the integrity of the stored data.
[0026] As the scale of on-chip systems continues to expand and the diversity of system tasks increases, the diversity and complexity of memory access requests also increase, leading to a corresponding increase in the workload of the memory controller. For example, with the increasing number of processors and processor cores in on-chip systems, a large number of processors or processor cores need to perform memory read and write operations through the memory controller. Consequently, the number and types of tasks executed by a large number of processors and processor cores also increase, resulting in a corresponding increase in the workload of the memory controller.
[0027] In some cases, the memory controller may experience abnormal situations such as instruction loss or instruction scheduling errors, which can lead to corresponding memory operation anomalies. For example, due to the diversity, complexity, and high concurrency of memory access requests, the memory controller sometimes struggles to accurately schedule different memory access requests, resulting in memory access delays and conflicts, and reducing memory access efficiency.
[0028] Typically, memory controller malfunctions don't go unnoticed by users until the system malfunctions due to abnormal memory operations. By the time users discover a clear problem and attempt to test or investigate, system performance is severely compromised.
[0029] To address the aforementioned technical problems, this application provides a novel system-on-a-chip (SoC) capable of recording memory operation instructions output by the memory controller in real time. This enables real-time monitoring and recording of the memory controller, and the obtained instruction monitoring data can be used to analyze the performance of the memory controller or to promptly identify problems when the memory controller malfunctions.
[0030] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0031] This application first provides a system-on-a-chip (SoC), see [link to previous document]. Figure 2 As shown, the system-on-a-chip includes a memory subsystem 100, which includes a memory controller 101 and a performance monitoring unit 102.
[0032] The memory controller 101 is connected to the performance monitoring unit 102 via the Port Physical Layer Interface (DFI). This allows the performance monitoring unit 102 to receive memory operation instructions output by the memory controller via the Port Physical Layer Interface, and to record the memory operation instructions output by the memory controller 101 to obtain instruction monitoring data.
[0033] The aforementioned memory operation instructions are memory operation instructions that can be recognized and executed by the memory controller 101 after receiving a memory access request sent by the processor or processor core and parsing the memory access request.
[0034] The aforementioned instruction monitoring data includes information about each memory operation instruction output by the memory controller 101 through the port physical layer interface, including the instruction type, instruction content, etc.
[0035] The performance monitoring unit 102 is equipped with a memory or register for storing information related to memory operation instructions output by the memory controller 101 through the port physical layer interface.
[0036] In some embodiments, memory operation instructions output by the memory controller 101 through the port physical layer interface are sequentially stored in the performance monitoring unit 102 according to the order in which they are output. Alternatively, in other embodiments, the performance monitoring unit 102 is configured with corresponding storage space for each memory operation instruction or each type of memory operation instruction, for storing the corresponding memory operation instruction.
[0037] The system-on-a-chip (SoC) provided in this application includes a performance monitoring unit in the memory subsystem. The physical layer interface of the memory controller's port is connected to this performance monitoring unit. Based on this architecture, the performance monitoring unit can record the memory operation instructions output by the memory controller through the physical layer interface, obtaining instruction monitoring data. This instruction monitoring data can be used to analyze the performance of the memory controller. The aforementioned SoC implements real-time recording of memory operation instructions output by the memory controller. Based on the recorded instruction monitoring data, the performance of the memory controller can be analyzed in real time, or, in the event of a memory access anomaly, the instruction monitoring data can be used to efficiently verify whether the memory controller is malfunctioning, thereby improving the efficiency of detecting and resolving memory access anomalies.
[0038] The system-on-a-chip provided in another embodiment also includes memory 200, and the memory subsystem 100 also includes a port physical layer 103.
[0039] See Figure 3 As shown, in the on-chip system provided in this embodiment, the memory controller 101 is connected to one end of the port physical layer 103 through the port physical layer interface, and the other end of the port physical layer 103 is connected to the input / output port of the memory 200.
[0040] The main function of the port physical layer 103 is to align data and match data rates, and to interact with memory with commands and data at a higher frequency clock. It also takes into account clock management, data path training and calibration functions.
[0041] The aforementioned memory 200 can be any type of memory, such as DDR SDRAM, including LPDDR5, LPDDR4, DDR5, DDR4, etc. Furthermore, memory 200 can include multiple memory blocks.
[0042] The types of the memory controller 101 and port physical layer 103 mentioned above are matched with the type of memory 200 to enable smooth interaction between the memory controller 101, port physical layer 103 and memory 200.
[0043] In this embodiment, the physical layer interface of the memory controller 101 is connected to both the performance monitoring unit 102 and the physical layer 103, thereby enabling memory operation instructions output by the memory controller 101 through the physical layer interface to be simultaneously sent to both the performance monitoring unit 102 and the physical layer 103. Based on this connection, the access of the performance monitoring unit 102 will not affect the operation of the original on-chip system architecture. The performance monitoring unit 102 only records the memory operation instructions output by the memory controller 101 through the physical layer interface and will not affect the transmission of these instructions to the physical layer 103.
[0044] In another embodiment, see continue to see Figure 3 As shown, the system-on-a-chip also includes a processor 300, which is connected to the memory controller 101 via a data bus.
[0045] The aforementioned data bus can be any type of bus used to implement internal data communication within the system-on-chip, such as a bus of the Advanced Microcontroller Bus Architecture (AMBA) type.
[0046] The processor 300 described above can be a single processor or multiple processors, including a central processing unit, a graphics processing unit, a neural network processor, a video processor, etc. The processor 300 may include one or more processor cores, each of which can send memory access requests to the memory controller 101 via the data bus between the processor 300 and the memory controller 101.
[0047] Based on this architecture, the memory access process of the processor 300 can be monitored and recorded through the performance monitoring unit 102, which is beneficial for analyzing the memory access performance of the processor 300 and for timely analysis of the problem when an anomaly occurs.
[0048] In another embodiment, the specific structure of the performance monitoring unit 102 in the system-on-chip is disclosed.
[0049] See Figure 4 As shown, the performance monitoring unit 102 disclosed in this embodiment includes:
[0050] Instruction parsing module 1021 and counting unit 1022.
[0051] The input terminal of the instruction parsing module 1021 is connected to the physical layer interface of the memory controller 101, and is used to receive memory operation instructions output by the memory controller 101 through the physical layer interface.
[0052] After receiving the memory operation instructions output by the memory controller 101 through the port physical layer interface, the instruction parsing module 1021 parses the memory operation instructions to obtain instruction information.
[0053] The memory controller 101 outputs memory operation instructions primarily through its physical layer interface, including the dfi_ca and dfi_cs signals. The dfi_ca signal is the instruction code sent to memory; it also carries address information when sending row open / close and read / write commands, corresponding to the row address, bank address, and column address of the memory. The dfi_cs signal is the rank address information sent to memory, emitted simultaneously with the dfi_ca signal.
[0054] The instruction parsing module 1021 can determine the type of memory operation instruction sent by the memory controller 101, as well as instruction content and other instruction information, by parsing the aforementioned dfi_ca and dfi_cs signals.
[0055] The memory operation instructions sent by the memory controller 101 can be any one of the following: row open instruction (Activate), precharge instruction (Precharge), read instruction (Read), write instruction (Write), and refresh instruction (Refresh).
[0056] The output of the instruction parsing module 1021 is connected to the input of the counting unit 1022, so that after the instruction parsing module 1021 parses the memory operation instructions output by the memory controller to obtain the instruction information, it sends the instruction information to the counting unit 1022.
[0057] The counting unit 1022 counts and performs statistics on the instruction information output by the instruction parsing module 1021.
[0058] Specifically, the counting unit 1022 counts and statistically analyzes each instruction output by the instruction parsing module 1021 to obtain instruction monitoring data. For example, it counts the row open (Activate), precharge (Precharge), read (Read), write (Write), and refresh (Refresh) instructions output by the instruction parsing module 1021, and statistically analyzes the row address, rank address, and bank address corresponding to each instruction. Through the instruction monitoring data obtained by the counting and statistical analysis of the counting unit 1022, the number and sending order of row open (Activate), precharge (Precharge), read (Read), write (Write), and refresh (Refresh) instructions issued by the memory controller 101 within a certain time period can be determined. Furthermore, the frequency of access to each memory row, rank, and bank can also be statistically analyzed.
[0059] In another embodiment of the system-on-a-chip, the performance monitoring unit 102 further includes a cache.
[0060] The cache is set on the path between the instruction parsing module 1021 and the counting unit 1022, and is used to receive and store the instruction information output by the instruction parsing module 1021, and to send the stored instruction information to the counting unit 1022.
[0061] The cache setting provides a buffer function for data transmission between the instruction parsing module 1021 and the counting unit 1022, so that the instruction parsing module 1021 and the counting unit 1022 can smoothly perform instruction parsing and instruction information statistics.
[0062] In another embodiment of the on-chip system, see [link to another embodiment]. Figure 5 As shown, the cache in the performance monitoring unit 102 includes a first cache 1023 and a second cache 1024. The first cache 1023 and the second cache 1024 can be caches of the same type and / or the same size, or they can be caches of different types and / or different sizes.
[0063] The input terminal of the first cache 1023 is connected to the output terminal of the instruction parsing module 1021, and the output terminal of the first cache 1023 is connected to the input terminal of the counting unit 1022 and the input terminal of the second cache 1024, respectively.
[0064] The output of the second buffer 1024 is connected to the input of the counting unit 1022.
[0065] Based on the above structure, the first cache 1023 receives instruction information output by the instruction parsing module 1021. After the instruction information output by the instruction parsing module 1021 has been stored in the first cache 1023 for a set period of time, the first cache 1023 sends the stored instruction information to the second cache 1024. At this time, the first cache 1023 can receive the next instruction information output by the instruction parsing module 1021.
[0066] The performance monitoring unit 102 in the on-chip system implements instruction information buffering through a two-level cache, and also separates the storage of different instructions to avoid confusion between them. Furthermore, by storing two adjacent instructions separately in the two-level cache, instructions from different time periods can be stored separately. This allows for recording the time interval between two adjacent instructions. When two adjacent instructions constitute an event, the time interval between them represents the duration of that event, thus providing a basis for the counting unit 1022 to collect various event information.
[0067] In another embodiment, when cache 1013 sends the next received instruction information to counting unit 1022, second cache 1024 sends the previously received instruction information stored in it to counting unit 1022. For example, first cache 1023 sends the previously received instruction information to second cache 1024, and then when first cache 1023 receives instruction information this time, first cache 1023 and second cache 1024 simultaneously send the currently received instruction information and the previously received instruction information to counting unit 1022, so that counting unit 1022 can receive information from two adjacent instructions at the same time, so as to quickly count and analyze the switching and changes of adjacent instructions.
[0068] For example, the first cache 1023 receives and stores the instruction information output by the instruction parsing module 1021. After one clock cycle, the first cache 1023 sends the stored instruction information to the second cache 1024, and then the first cache 1023 can receive the next instruction information. When the first cache 1023 receives the next instruction information, the first cache 1023 and the second cache 1024 synchronously send the cached instruction information to the counting unit 1022.
[0069] In another embodiment of the on-chip system, see [link to relevant documentation]. Figure 6 As shown, the performance monitoring unit 102 also includes an event counting enable module 1025.
[0070] See Figure 6As shown, the input terminal of the event counting enable module 1025 is connected to the output terminal of the first buffer 1023 and the output terminal of the second buffer 1024, respectively, and the output terminal of the event counting enable module 1025 is connected to the input terminal of the counting unit 1022.
[0071] The event counting enable module 1025 is used to identify event information based on the instruction information sent by the first cache 1023 and the second cache 1024, and to send a corresponding counting enable signal to the counting unit 1022 based on the received instruction information and / or the identified event information. The counting enable signal is used to trigger the counting unit 1022 to count or count the corresponding instruction or event.
[0072] In this embodiment, events to be counted are preset, and the event counting enable module 1025 identifies the events according to the instruction information sent by the first cache 1023 and the second cache 1024, and sends a counting enable signal to the counting unit 1022 to trigger the counting unit 1022 to count or count the corresponding events based on the time of identification.
[0073] The events to be counted in this embodiment include, but are not limited to, the following events:
[0074] 1. Events where the number of consecutive write commands is between 1 and N-1, N to 2N-1, ..., where N is a positive integer. For example, events where the number of consecutive write commands is between 1 and 9, 10 and 19, 20 and 29, ..., 80 and 89, or more than 90.
[0075] 2. Events where the number of consecutive read commands is between 1 and N-1, N to 2N-1, ..., where N is a positive integer. For example, events where the number of consecutive read commands is between 1 and 9, 10 and 19, 20 and 29, ..., 80 and 89, or more than 90.
[0076] 3. Events where the two consecutive read commands switch to read commands and are for different ranks; events where the two consecutive read commands switch to read commands and are for the same rank but different banks; events where the two consecutive read commands switch to read commands and are for the same rank and the same bank but different row addresses; events where the two consecutive read commands switch to read commands and are for the same rank, the same bank and the same row address.
[0077] 4. Events where the two consecutive read instructions are switched to write instructions and are for different ranks; events where the two consecutive read instructions are switched to write instructions and are for the same rank but different banks; events where the two consecutive read instructions are switched to write instructions and are for the same rank and the same bank but different row addresses; events where the two consecutive read instructions are switched to write instructions and are for the same rank, the same bank and the same row address.
[0078] 5. Events where the two consecutive instructions are write instructions switching to write instructions and are for different ranks; events where the two consecutive instructions are write instructions switching to write instructions and are for the same rank but different banks; events where the two consecutive instructions are write instructions switching to write instructions and are for the same rank and the same bank but different row addresses; events where the two consecutive instructions are write instructions switching to write instructions and are for the same rank, the same bank and the same row address.
[0079] 6. Events where the two consecutive instructions are write instructions switched to read instructions and are for different ranks; events where the two consecutive instructions are write instructions switched to read instructions and are for the same rank but different banks; events where the two consecutive instructions are write instructions switched to read instructions and are for the same rank and the same bank but different row addresses; events where the two consecutive instructions are write instructions switched to read instructions and are for the same rank, the same bank and the same row address.
[0080] 7. Events where the instruction before and after is a read instruction and then switches to a refresh instruction; events where the instruction before and after is a write instruction and then switches to a refresh instruction.
[0081] For the events described in 3, 4, 5, and 6 above, the time interval between the two instructions is also counted.
[0082] The event counting enable module 1025 identifies whether the events described in 3, 4, 5, 6, and 7 above have occurred based on the instruction information sent by the first cache 1023 and the second cache 1024, and identifies whether the events described in 1 and 2 above have occurred by statistically analyzing and classifying the received instruction information. If an event has occurred, it sends a counting enable signal corresponding to the event to the counting unit 1022.
[0083] After receiving the counting enable signal corresponding to a specific event sent by the event counting enable module 1025, the counting unit 1022 counts and performs statistics on the event.
[0084] In another embodiment of the system-on-a-chip, the counting unit 1022 is internally provided with an instruction counter, an event counter and an event duration counter.
[0085] The instruction counter is used to count instructions. For example, when the instruction parsing module 1021 sends an instruction information counting unit 1022, or when the event counting enable module 1025 sends an instruction counting enable signal to the counting unit 1022, the instruction counter increments the count of the instruction by 1 to count the instruction.
[0086] The event counter is used to count the events identified by the instruction information output by the instruction parsing module 1021. For example, when an event among the events to be counted is identified by the instruction information output by the instruction parsing module 1021, or when the event counting enable module 1025 sends a counting enable signal for an event to the counting unit 1022, the event counter increments the count of that event by 1 to count the event.
[0087] The event duration counter is used to record the duration of an event. For example, for events 3, 4, 5, and 6 mentioned above, the duration of the event is determined by counting the time interval between two instructions before and after the event. For instance, a separate timer can be set in the counting unit 1022 to record the duration of the event.
[0088] In this embodiment, by using different counters to count instructions, events, and event durations, the efficiency and accuracy of instruction counting can be improved.
[0089] In another embodiment, the counting unit 1022 further includes corresponding registers for each instruction and each event to store the counting and statistical results of the corresponding instruction or event. This storage method makes the counting and statistical results of instructions and events clear and easy to understand, thus facilitating the acquisition of statistical results for any instruction or event. Furthermore, the register is also used to control the enabling and clearing of the counter. For example, the register can be configured to enable or clear the counter corresponding to the register. For instance, by configuring the register used to store the counting and statistical results of read instructions, the counter used to count read instructions can be enabled or cleared.
[0090] In another embodiment, the performance monitoring unit 102 is further provided with a performance analysis module, which is connected to the counting unit 1022 and is used to read the counting and statistical results stored in the counting unit 1022, perform data parsing, analyze the performance of the memory controller 101, and obtain performance analysis results.
[0091] Specifically, the instruction parsing module 1021 and the counting unit 1022 comprehensively record information such as the number of various instructions, the distribution of consecutive read and write instructions, the number of instruction conversion events, and the number of clock cycles consumed, providing data support for memory controller performance analysis. The performance analysis module, by analyzing the count and statistical results stored in the technical unit 1022, can accurately evaluate the actual performance of the memory controller scheduling algorithm and gain a deeper understanding of the advantages and disadvantages in the scheduling process. For example, by analyzing the distribution of consecutive read and write instructions, the processing efficiency of the memory controller for sequential read and write operations under a specific workload can be determined; based on the number and time of read-to-write instruction conversion events, the performance loss of the memory controller during read-write operation switching can be evaluated.
[0092] Alternatively, based on the number of transition events from read to read, read to write, write to read, and write to write, as well as the clock cycle consumption corresponding to each event, the average time interval between read and write instructions can be calculated. By comparing this parameter with the timing parameters specified in the memory read / write protocol, it can be determined whether the timing parameters configured by the memory controller are reasonable.
[0093] By analyzing the number of consecutive read and write instruction events in different ranges, as well as the proportion of read-to-write and write-to-read switching events to the total number of instruction switching events, we can more intuitively determine whether the memory controller's control of read-to-write switching is reasonable.
[0094] The on-chip system provided in this embodiment can directly obtain the performance analysis results of the memory controller through the performance monitoring unit, thereby enabling timely detection of performance anomalies and memory access anomalies during the operation of the memory controller, which helps to ensure memory read and write efficiency and performance.
[0095] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The modules and sub-modules in the devices and terminals of the various embodiments of this application can be merged, divided, and deleted according to actual needs, and the features described in each embodiment can be replaced or combined.
[0096] In the embodiments provided in this application, it should be understood that the disclosed terminals and devices can be implemented in other ways. For example, the division of modules or sub-modules is merely a logical functional division; in actual implementation, there may be other division methods. For instance, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be indirect couplings or communication connections through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.
[0097] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.
[0098] In addition, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module.
[0099] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.
[0100] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A system-on-a-chip, characterized in that, The system-on-a-chip includes a memory subsystem; the memory subsystem includes a memory controller and a performance monitoring unit; wherein the memory controller is connected to the performance monitoring unit through a port physical layer interface; The performance monitoring unit is used to record the memory operation instructions output by the memory controller through the port physical layer interface to obtain instruction monitoring data; the instruction monitoring data is used to analyze the performance of the memory controller.
2. The system-on-a-chip according to claim 1, characterized in that, The system-on-chip also includes memory, and the memory subsystem further includes a port physical layer; One end of the port physical layer is connected to the port physical layer interface of the memory controller, and the other end of the port physical layer is connected to the memory.
3. The system-on-a-chip according to claim 1, characterized in that, The system-on-a-chip also includes a processor, which is connected to the memory controller via a data bus.
4. The system-on-a-chip according to any one of claims 1 to 3, characterized in that, The performance monitoring unit includes: The instruction parsing module is used to parse the memory operation instructions output by the memory controller to obtain instruction information; The counting unit is used to count and statistically analyze the instruction information output by the instruction parsing module.
5. The system-on-a-chip according to claim 4, characterized in that, The performance monitoring unit also includes a cache for storing instruction information output by the instruction parsing module.
6. The system-on-a-chip according to claim 5, characterized in that, The cache includes a first cache and a second cache; The first cache is used to receive and store instruction information output by the instruction parsing module; The instruction information output by the instruction parsing module is stored in the first cache, and after a set time period, the instruction information stored in the first cache is transferred to the second cache.
7. The system-on-a-chip according to claim 6, characterized in that, The performance monitoring unit also includes an event counting enable module; The event counting enable module is used to identify event information based on the instruction information sent by the first cache and the second cache, and to send a corresponding counting enable signal to the counting unit based on the received instruction information and / or the identified event information.
8. The system-on-a-chip according to claim 4, characterized in that, The counting unit includes an instruction counter, an event counter, and an event duration counter; The instruction counter is used to count instructions. The event counter is used to count the events identified based on the instruction information; The event duration counter is used to record the duration of the event.
9. The system-on-a-chip according to claim 8, characterized in that, The counting unit also includes registers corresponding to various instructions and events, used to store counting and statistical results, and / or to control the enabling and clearing of the counter.
10. The system-on-a-chip according to claim 4, characterized in that, The performance monitoring unit further includes: The performance analysis module is used to analyze the performance of the memory controller based on the count and statistical results generated in the counting unit, and obtain the performance analysis results.