Circuit board and electronic device

Abstract

The application provides a circuit board and an electronic device, comprising a plurality of copper matrix layers stacked along a first direction, among the plurality of copper matrix layers, the copper matrix layers located at the outermost sides in the first direction are respectively a first matrix layer and a second matrix layer, the thickness of the first matrix layer is equal to the thickness of the second matrix layer, and the first matrix layer comprises a plurality of sub-matrix layers stacked along the first direction. The total thickness of the first matrix layer is equal to the thickness of the second matrix layer, so that the circuit board has a symmetrical structure and thickness in the first direction, and is not easy to warp during pressing. Meanwhile, due to the thinness of the single sub-matrix layer, more intensive wiring can be realized. Different current sizes of elements are arranged on copper matrix layers with different thicknesses, so that the current carrying capacity is guaranteed, wiring can be more reasonable, and the problem that the large current carrying capacity and intensive wiring on the circuit board cannot be compatible is solved.

Description

Technical Field

[0001] This utility model relates to the field of battery technology, specifically to a circuit board and electronic device. Background Technology

[0002] As electronic devices become increasingly feature-rich, the capacity of existing batteries is growing larger and larger. Consequently, the power and current carrying capacity of the circuit boards also need to be increased. To achieve greater current carrying capacity, the copper thickness of the circuit boards needs to be increased to reduce impedance.

[0003] In existing technologies, to ensure the mechanical and electrical properties of circuit boards and prevent warping, multilayer circuit boards are mainly symmetrically laminated. Due to the limitations of symmetrical lamination, layers with different current-carrying capacities have the same copper thickness. Excessive copper thickness makes etching difficult, requiring larger etching spacing, which limits the line width and spacing of signal lines, resulting in less flexible routing and the inability to achieve dense routing. Utility Model Content

[0004] This utility model provides a circuit board and electronic device to solve the problems of insufficient wiring flexibility and inability to achieve dense wiring in related technologies.

[0005] To solve the above-mentioned technical problems, this utility model is implemented as follows:

[0006] In a first aspect, the present invention provides a circuit board including a plurality of copper substrate layers stacked along a first direction. Among the plurality of copper substrate layers, the outermost copper substrate layer in the first direction is a first substrate layer and a second substrate layer, the thickness of the first substrate layer is equal to the thickness of the second substrate layer, and at least one of the first substrate layer and the second substrate layer includes a plurality of first sub-substrate layers stacked along the first direction.

[0007] Optionally, the circuit board further includes a plurality of first dielectric layers and second dielectric layers;

[0008] One of the first dielectric layers is disposed between two adjacent copper substrate layers;

[0009] A second dielectric layer is disposed between two adjacent first sub-substrate layers.

[0010] Optionally, among the plurality of copper substrate layers, the copper substrate layer located between the first substrate layer and the second substrate layer is a third substrate layer, and at least one of the third substrate layers includes a plurality of second sub-substrates stacked along the first direction.

[0011] Optionally, at least one of the third substrate layers is a core board layer, wherein the core board layer is a first copper foil layer, an insulating substrate layer, and a second copper foil layer stacked sequentially along the first direction.

[0012] Optionally, the first substrate layer includes a plurality of first sub-substrates, the thickness of the first sub-substrates is less than the thickness of the second substrate layer, and the rated current on the second substrate layer is greater than the rated current on the first sub-substrates.

[0013] Optionally, among the plurality of first sub-substrate layers, an electronic component is disposed on the surface of the outermost first sub-substrate layer in the first direction that is opposite to the second substrate layer, and an electronic component is disposed on the surface of the second substrate layer that is opposite to the first substrate layer.

[0014] Optionally, the minimum etch spacing of the second substrate layer is greater than the minimum etch spacing of each of the first sub-substrates in the first substrate layer, and the wiring density on the second substrate layer is less than the wiring density on each of the first sub-substrates in the first substrate layer.

[0015] Optionally, the circuit board is provided with a via extending along the first direction, the via penetrating at least one of the copper substrate layers, the wall of the via being plated with a metal layer, and at least one of the copper substrate layers being electrically connected to the metal layer.

[0016] Optionally, the via includes at least one of a through hole, a blind hole, and a buried hole.

[0017] Secondly, this utility model provides an electronic device, including any of the circuit boards described in the first aspect.

[0018] This invention provides a circuit board and an electronic device. The outermost layers of the circuit board are a first substrate layer and a second substrate layer. One layer is composed of multiple thinner sub-substrate layers laminated together, while the other layer is a thicker copper substrate layer. The total thickness of the first substrate layer is equal to the thickness of the second substrate layer, ensuring that the circuit board has a symmetrical structure and thickness in the first direction, making it less prone to warping during lamination. Simultaneously, because each individual sub-substrate layer is thinner, the etching time is shorter, and the minimum etching pitch is smaller, allowing for denser routing. Correspondingly, the internal resistance is relatively higher, making it suitable for densely arranging low-current signal lines. The thicker copper substrate layer in the second substrate layer has lower internal resistance and a larger etching pitch, making it suitable for arranging high-current components. By placing components with different current values ​​on copper substrate layers of different thicknesses, current-carrying capacity is ensured while allowing for more rational routing, solving the problem of incompatibility between high current-carrying capacity and dense routing on a circuit board. Attached Figure Description

[0019] Figure 1 This diagram illustrates a three-layer circuit board provided in an embodiment of the present invention.

[0020] Figure 2This diagram illustrates a five-layer circuit board provided in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram showing the core board layer provided in an embodiment of the present invention.

[0022] Figure label:

[0023] 100: Circuit board; 10: Copper substrate layer; 11: First substrate layer; 111: First sub-substrate layer; 112: Second dielectric layer; 12: Second substrate layer; 13: Third substrate layer; 20: First dielectric layer; 30: Core board layer; 31: First copper foil layer; 32: Insulating substrate layer; 33: Second copper foil layer; 40: Through hole. Detailed Implementation

[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0025] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0026] This utility model embodiment provides a circuit board 100, including a plurality of copper substrate layers 10 stacked along a first direction. Among the plurality of copper substrate layers 10, the outermost copper substrate layers 10 in the first direction are a first substrate layer 11 and a second substrate layer 12, respectively. The thickness of the first substrate layer 11 is equal to the thickness of the second substrate layer 12. At least one of the first substrate layer 11 and the second substrate layer 12 includes a plurality of first sub-substrate layers 111 stacked along the first direction.

[0027] This utility model designs an asymmetric circuit board 100-layer stacked structure, such as Figure 1As shown, in this embodiment, the top layer of the circuit board 100 is defined as the first substrate layer 11, and the bottom layer is defined as the second substrate layer 12. The first substrate layer 11 is divided into two layers, L1 and L2, and the second substrate layer 12 is L3. The circuit board 100 consists of three layers in total, and the thickness of the first substrate layer 11 is equal to the thickness of the second substrate layer 12. This makes the first substrate layer 11 and the second substrate layer 12 have symmetrical thickness and structure in the first direction. During high-temperature heat treatment, the thermal expansion effects of the first substrate layer 11 and the second substrate layer 12 cancel each other out, reducing the possibility of warping, making the etching conditions more consistent, ensuring the accuracy and consistency of the circuit, and giving the circuit board 100 better mechanical and electrical stability.

[0028] In practical applications, the copper substrate layer 10 uses copper foil of varying thicknesses, primarily 1 / 3 ounce, 0.5 ounce, 1 ounce, 2 ounce, and 3 ounce. Different thicknesses of copper foil can be selected based on the current-carrying and mechanical performance requirements of the circuit board 100. In some specialized circuit board 100 designs, non-standard thickness copper foil may be customized to meet specific electrical, mechanical, or heat dissipation requirements. In some high-precision instruments, thinner copper foil may be used to reduce electromagnetic interference; while in aerospace, military, and other fields with extremely high reliability requirements, thicker copper foil may be used to improve the overload resistance of the circuit board 100.

[0029] The thickness of the copper foil directly affects the current-carrying capacity and wiring density of the circuit board 100. During the fabrication of the circuit board 100, unwanted copper foil is removed by etching, leaving conductive lines. The spacing between these lines is called the etching pitch. The thicker the copper foil, the more copper needs to be removed during etching, and the etching time will increase accordingly, thus increasing the possibility of side etching. To ensure that there is no short circuit between the lines, a larger etching pitch is required. The larger the etching pitch, the greater the distance between the conductive lines. Therefore, thicker copper foil usually has a lower wiring density.

[0030] The thickness of copper foil affects current carrying capacity because, given a fixed material and length, a larger cross-sectional area results in lower resistance. The cross-sectional area of ​​the conductive lines on circuit board 100 is equal to the thickness of the copper foil multiplied by its width. Therefore, with a fixed width, increasing the copper foil thickness increases its cross-sectional area, reduces resistance, and decreases heat generation, thus enabling it to carry a larger current without overheating and improving current carrying capacity. Therefore, when the current carrying capacity of circuit board 100 is high, the copper foil thickness is often appropriately increased to ensure normal circuit operation.

[0031] This embodiment and its appendix Figure 1A simple splitting scheme is provided, wherein the first substrate layer 11 is composed of two first sub-substrate layers 111 of the same thickness, namely L1 and L2, and the second substrate layer 12 is L3. The thickness of the first substrate layer 11 is equal to the thickness of the second substrate layer 12, and they are laminated to form a three-layer circuit board 100.

[0032] Furthermore, such as Figure 2 As shown, multiple copper substrate layers 10 can be symmetrically arranged between the first substrate layer 11 and the second substrate layer 12, designed with 5, 7, or other layers, to form a stacked design with any number of board layers. Due to the limitations of symmetrical lamination, existing multilayer circuit boards 100 are usually designed with an even number of layers such as 4, 6, or 8. In this embodiment, by dividing the symmetrical copper substrate layer 10 of equal thickness into multiple first sub-substrate layers 111, an odd number of layers can be arranged, providing a more flexible and complex multilayer circuit board 100 design scheme.

[0033] For ease of explanation and understanding, in this embodiment, the top layer of the circuit board 100 is defined as the first substrate layer 11, and the bottom layer is defined as the second substrate layer 12. Figure 1 and attached Figure 2 The embodiments described herein are all based on this, with the first substrate layer 11 split into two layers. In specific applications, depending on actual needs, the positions of the first substrate layer 11 and the second substrate layer 12 can be reversed, and the first substrate layer 11 can also be split into several thinner first sub-substrate layers 111. Alternatively, multiple thin copper layers can be laminated on the second substrate layer 12. Under the premise that the total thickness of the first substrate layer 11 is the same as the thickness of the second substrate layer 12, each first sub-substrate layer 111 can have different thicknesses, allowing for flexible wiring. All of these can be implemented with reference to the structure provided in this embodiment.

[0034] In some alternative embodiments, the circuit board 100 further includes a plurality of first dielectric layers 20 and second dielectric layers 112; a first dielectric layer 20 is disposed between two adjacent copper substrate layers 10; and a second dielectric layer 112 is disposed between two adjacent first sub-substrate layers 111.

[0035] The circuit board 100 includes multiple first dielectric layers 20 and second dielectric layers 112. A first dielectric layer 20 is disposed between two adjacent copper substrate layers 10, its function being to isolate the adjacent copper substrate layers 10, prevent short circuits, and also provide insulation and support. A second dielectric layer 112 is disposed between two adjacent first sub-substrate layers 111, similarly serving an insulating and isolating function, ensuring electrical independence between each sub-substrate layer, and improving the stability and reliability of the circuit board 100. It is understandable that in situations such as... Figure 1In the embodiment shown, the thickness of the second substrate layer 12 is actually equal to the thickness of L1 and L2 and the thickness of the second dielectric layer 112 pressed between them.

[0036] The first dielectric layer 20 and the second dielectric layer 112 are prepreg (PP sheets) used to provide appropriate insulation between the copper substrate layers 10. It is a dielectric material composed of semi-solid resin and glass fiber, forming a so-called wetting layer. In the circuit board 100, it mainly serves to fill and bond, filling the gaps etched between conductive lines and bonding adjacent copper substrate layers 10 together. Layers of different thicknesses are laminated together by PP layers, forming a mirror-symmetric structure with alternating lamination of the copper substrate layers 10 and PP layers. To ensure structural symmetry, each PP layer is typically of equal thickness.

[0037] The first dielectric layer 20 and the second dielectric layer 112 serve as isolation, allowing each copper substrate layer 10 in the multilayer circuit board 100 to be independently wired and used for different purposes. For example... Figure 1 The three-layer circuit board 100 shown has L1 for soldering electronic components and routing, and L2 for auxiliary routing on L1. The more electronic components there are, the more routing is needed. Transferring large-area routing of electronic components to other stacked layers reduces the area of ​​the circuit board 100. Different types of signals, such as digital signals, analog signals, and high-frequency signals, can be arranged on different layers, reducing interference between signals and improving the stability and accuracy of signal transmission. In addition to the signal layers for routing, some layers are dedicated to power distribution, such as power and ground layers. The power layer provides a stable power supply to the entire circuit board 100 and can be segmented to independently power multiple different signal layers. The ground layer provides a low-impedance return path for current. This multi-layer structure allows for better management of power supply and current flow, reducing the impact of power supply noise on signals and providing greater flexibility in electronic component placement.

[0038] In some alternative embodiments, among the plurality of copper substrate layers 10, the copper substrate layer 10 located between the first substrate layer 11 and the second substrate layer 12 is a third substrate layer 13, and at least one third substrate layer 13 includes a plurality of second sub-substrates stacked along a first direction.

[0039] On the inner layer of the circuit board 100, the same asymmetric stacked structure can be used, with a thick copper layer symmetrically arranged with multiple thin copper layers of the same total thickness, in order to achieve a more flexible and diverse layout.

[0040] In addition, in some optional embodiments, at least one third substrate layer 13 is a core board layer 30, which is a first copper foil layer 31-insulating substrate layer 32-second copper foil layer 33 stacked sequentially along the first direction.

[0041] In the multilayer circuit board 100, the circuit board 100 is mainly formed by laminating multiple core layers 30 (CORE), such as Figure 3 As shown, a CORE is a basic unit, also known as a copper-clad laminate, with copper foil on both surfaces as conductive layers. An insulating substrate layer 32, primarily composed of reinforcing glass fiber impregnated with solid resin, is filled between the two copper foil layers. Multiple COREs are laminated together using PP lamination.

[0042] In addition, in some optional embodiments, the first substrate layer 11 includes a plurality of first sub-substrate layers 111, the thickness of the first sub-substrate layers 111 is less than the thickness of the second substrate layer 12, and the rated current on the second substrate layer 12 is greater than the rated current on the first sub-substrate layers 111.

[0043] This design allows for the rational allocation of the thickness and load-bearing capacity of the substrate layer based on the current requirements of different areas. For example, for areas that require high current carrying capacity, such as power modules, a thicker second substrate layer 12 with a higher rated current can be used; while for signal transmission areas with relatively low current carrying capacity requirements, a thinner first sub-substrate layer 111 can be used, thereby optimizing material usage and cost while ensuring the performance of the circuit board 100.

[0044] In addition, in some optional embodiments, among the plurality of first sub-substrate layers 111, an electronic component is disposed on the surface of the outermost first sub-substrate layer 111 in the first direction away from the second substrate layer 12, and an electronic component is disposed on the surface of the second substrate layer 12 away from the first substrate layer 11.

[0045] The top and bottom layers of the circuit board 100, as well as the outermost layer of the first substrate layer 11 and the second substrate layer 12, are usually component layers used to arrange electronic components. In addition to realizing electrical connections, they also undertake the task of connecting with external interfaces. The top and bottom layers are covered with soldering points for electronic components such as connectors, switches, and indicator lights. Through precise layout and soldering processes, smooth interaction between electronic devices and the external environment is ensured.

[0046] It should be noted that, in this embodiment, the thicker layer of the top and bottom layers is mainly used to arrange high-current electronic components such as MOSFETs and integrated circuits (ICs), while the thinner layer is used to arrange electronic components with smaller current such as resistors and capacitors, so as to match the current carrying capacity of copper substrate layers 10 of different thicknesses.

[0047] In some embodiments, electronic components, primarily surface-mount components with a relatively small thickness, can also be disposed on inner layers. Within the limited space of the circuit board 100, by increasing the number of layers, different types of components can be distributed on different layers, thereby achieving a more compact layout.

[0048] Additionally, in some optional embodiments, the minimum etch pitch of the second substrate layer 12 is greater than the minimum etch pitch of each of the first sub-substrate layers 111 in the first substrate layer 11, and the wiring density on the second substrate layer 12 is less than the wiring density on each of the first sub-substrate layers 111 in the first substrate layer 11.

[0049] For example, in this embodiment, the first substrate layer 11 includes two thin copper layers, L1 and L2, and the second substrate layer 12 is a thick copper layer. Since copper thickness is related to etching time, it is understood that the thinner L1 and L2 have smaller etching pitches. When the copper thickness is 1 / 3 ounce and the conductive line width is 12 mil, the etching pitch is less than 0.1 mm, allowing for dense wiring. The thicker L3 has a larger etching pitch, which limits the line width and spacing of the signal lines, but it has lower internal resistance, better heat dissipation, and can carry larger currents. By splitting the first substrate layer 11, which is originally the same thickness as the second substrate layer 12, into multiple thinner first sub-substrates 111, the low-current signal lines can be concentrated on the thin copper layers, while the second substrate layer 12, which carries large currents, retains a larger thickness. Compared with the prior art, where the board layers are of uniform thickness and all wiring is done on thick copper layers, this increases the wiring density of signal lines and saves wiring space. This utility model embodiment uses an asymmetrical stacked design to press thin copper and thick copper into the same circuit board 100, achieving the effect of separating the thin copper for signal lines from the thick copper for high current, thus solving the problem of the circuit board 100 carrying high current and dense wiring.

[0050] In addition, in some optional embodiments, the circuit board 100 is provided with a via 40 extending along a first direction. The via 40 penetrates at least one copper substrate layer 10. The wall of the via 40 is plated with a metal layer. At least one copper substrate layer 10 is electrically connected to the metal layer.

[0051] Optionally, the via 40 includes at least one of a through hole, a blind hole, and a buried hole.

[0052] To achieve electrical connections between different conductive layers, the multilayer circuit board 100 is provided with vias 40. A via 40 is a small hole that penetrates all layers of the circuit board 100, and its interior is usually metallized to allow current to flow between the lines of different layers. Depending on their function, vias 40 can be classified as through-holes, blind vias, and buried vias. Through-holes penetrate the entire circuit board 100, from the top layer to the bottom layer; blind vias extend only from the surface of the circuit board 100 to a specific inner layer; buried vias are completely hidden inside the circuit board 100, connecting intermediate conductive layers. Some high-density integrated circuits can be connected to different signal and power layers through vias 40, allowing the circuit board 100 to accommodate more components within a limited space, thus improving the integration density of the circuit board 100.

[0053] In conjunction with the above embodiments, the manufacturing method of circuit board 100 specifically includes:

[0054] 1. Design the L1 and L2 structures in the signal line layout area to be two thin copper layers with the same thickness.

[0055] 2. L1 and L2 are first pressed together using PP sheets to form the first substrate layer 11, making its thickness consistent with the copper thickness of the thick copper area of ​​the second substrate layer 12. This ensures symmetrical pressing requirements during the second pressing process.

[0056] 3. Perform pre-lamination treatment after completing the CORE layer circuitry.

[0057] 4. Press the first substrate layer 11 and the second substrate layer 12 onto the CORE layer simultaneously.

[0058] 5. Continue with the production of subsequent etching inks and other processes.

[0059] This invention provides a circuit board 100 and an electronic device. The outermost layers of the circuit board 100 are a first substrate layer 11 and a second substrate layer 12. One layer is formed by laminating multiple thinner sub-substrate layers, and the other layer is a thicker copper substrate layer 10. The total thickness of the first substrate layer 11 is equal to the thickness of the second substrate layer 12, ensuring that the circuit board 100 has a symmetrical structure and thickness in the first direction, making it less prone to warping during lamination. Simultaneously, because each individual sub-substrate layer is thinner, the etching time is shorter, and the minimum etching pitch is smaller, allowing for denser routing. Correspondingly, the internal resistance is relatively larger, suitable for densely arranging signal lines with lower current carrying capacity. The copper substrate layer 10 in the second substrate layer is thicker, has lower internal resistance, and a larger etching pitch, suitable for arranging components with higher current carrying capacity. By arranging components with different current values ​​on copper substrate layers 10 of different thicknesses, current carrying capacity is ensured while allowing for more rational routing, solving the problem of incompatibility between high current carrying capacity and dense routing on the circuit board 100.

[0060] This utility model also provides an electronic device, including any of the circuit boards 100 provided in the above embodiments.

[0061] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0062] Although alternative embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the alternative embodiments as well as all changes and modifications falling within the scope of the present invention.

[0063] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity from another, and do not necessarily require or imply any such actual relationship or order between these entities. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or terminal device that includes that element.

[0064] The technical solution provided by this utility model has been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the principle and implementation of this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A circuit board (100), characterized by The system includes multiple copper substrate layers (10) stacked along a first direction. Among the multiple copper substrate layers (10), the outermost copper substrate layer (10) in the first direction is a first substrate layer (11) and a second substrate layer (12). The thickness of the first substrate layer (11) is equal to the thickness of the second substrate layer (12). At least one of the first substrate layer (11) and the second substrate layer (12) includes multiple first sub-substrate layers (111) stacked along the first direction.

2. A circuit board (100) according to claim 1, characterized in that The circuit board (100) also includes a plurality of first dielectric layers (20) and second dielectric layers (112); One of the first dielectric layers (20) is disposed between two adjacent copper substrate layers (10); A second dielectric layer (112) is disposed between two adjacent first sub-substrate layers (111).

3. A circuit board (100) according to claim 1, characterized in that Of the plurality of copper substrate layers (10), the copper substrate layer (10) located between the first substrate layer (11) and the second substrate layer (12) is a third substrate layer (13), and at least one of the third substrate layers (13) includes a plurality of second sub-sub-substrates stacked along the first direction.

4. A circuit board (100) according to claim 3, characterized in that At least one of the third substrate layers (13) is a core board layer (30), which is a first copper foil layer (31) - an insulating substrate layer (32) - a second copper foil layer (33) stacked sequentially along the first direction.

5. A circuit board (100) according to claim 1, characterized in that The first substrate layer (11) includes a plurality of first sub-substrates (111), the thickness of the first sub-substrates (111) is less than the thickness of the second substrate layer (12), and the rated current on the second substrate layer (12) is greater than the rated current on the first sub-substrates (111).

6. A circuit board (100) according to claim 5, characterized in that Among the plurality of first sub-substrate layers (111), the outermost first sub-substrate layer (111) in the first direction has an electronic component disposed on its surface opposite to the second substrate layer (12), and the second substrate layer (12) has an electronic component disposed on its surface opposite to the first substrate layer (11).

7. A circuit board (100) according to claim 6, characterized in that The minimum etch spacing of the second substrate layer (12) is greater than the minimum etch spacing of each of the first sub-substrate layers (111) in the first substrate layer (11), and the wiring density on the second substrate layer (12) is less than the wiring density on each of the first sub-substrate layers (111) in the first substrate layer (11).

8. A circuit board (100) according to any one of claims 1-7, characterized in that The circuit board (100) is provided with a through hole (40) extending along the first direction. The through hole (40) penetrates at least one of the copper substrate layers (10). The hole wall of the through hole (40) is plated with a metal layer. At least one of the copper substrate layers (10) is electrically connected to the metal layer.

9. A circuit board (100) according to claim 8, characterized in that The via (40) includes at least one of a through hole, a blind hole, and a buried hole.

10. An electronic device, comprising: Includes the circuit board (100) as described in any one of claims 1-9.

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