Display panel

Abstract

This application provides a display panel including a first conductive layer, at least one first insulating layer, a first active layer, and a second conductive layer. The first conductive layer includes a first conductive portion, the first active layer includes a first active portion, and the second conductive layer includes a first electrode and a second conductive portion. The display panel has a first hole and a second hole. By making the first hole penetrate the first active portion and the first insulating layer, and making the second hole penetrate the first insulating layer, the first electrode can be connected to the first active portion through the first hole, and the second conductive portion can be connected to the first conductive portion through the second hole. In this way, the first hole and the second hole can be formed simultaneously using the same photomask, without the need to use different photomasks to form the first hole and the second hole separately. Therefore, the number of photomasks can be reduced, and the manufacturing process can be simplified, thereby improving the production efficiency of the display panel and reducing the production cost.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] Thin-film transistors (TFTs) are key open-electrode components in liquid crystal displays (LCDs) and active matrix driven electric light-emitting displays (ATLCs), and their performance is closely related to the development direction of display panels.

[0003] Low-temperature polycrystalline oxide (LTPO) technology is an emerging display panel technology in recent years. This technology utilizes both low-temperature polycrystalline silicon (LTSi) thin-film transistors (TFTs) and metal-oxide-semiconductor (MODS) thin-film transistors (MODS) as transistors in the display panel. Because LTSi TFTs have high mobility and MODS TFTs have lower leakage current, combining the advantages of these two transistors is beneficial for the development of high-resolution, low-power, and high-image-quality display products. Currently, LTPO technology involves more patterning steps and requires multiple photomasks, resulting in a more complex manufacturing process and higher costs.

[0004] Therefore, it is necessary to provide a display panel to improve this deficiency. Utility Model Content

[0005] Embodiments of this application provide a display panel that can reduce the number of photomasks and lower production costs.

[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising:

[0007] The first conductive layer includes a first conductive portion;

[0008] At least one first insulating layer is disposed on the first conductive layer;

[0009] A first active layer is disposed on the first insulating layer, the first active layer including a first active portion; and

[0010] A second conductive layer is disposed on the first active layer, and the second conductive layer includes a first electrode and a second conductive portion.

[0011] The display panel is provided with a first hole and a second hole. The first hole penetrates the first active part and the first insulating layer in the thickness direction of the display panel. The first electrode is connected to the side wall of the first active part surrounding the first hole through the first hole. The second hole penetrates the first insulating layer in the thickness direction. The second conductive part is connected to the first conductive part through the second hole.

[0012] Optionally, the first active portion includes a channel portion and doped portions disposed on both sides of the channel portion;

[0013] The first hole penetrates the doped portion.

[0014] Optionally, the doped portion includes a heavily doped portion and a lightly doped portion located between the heavily doped portion and the channel portion, and the first hole penetrates the heavily doped portion.

[0015] Optionally, the display panel further includes a second active layer, wherein the material of the first active layer includes a silicon semiconductor material, and the material of the second active layer includes an oxide semiconductor material;

[0016] The second active layer is disposed on the first conductive layer, and the first active layer is disposed on the second active layer.

[0017] Optionally, the display panel includes two layers of the first insulating layer, the two layers of the first insulating layer comprising:

[0018] A first gate insulating layer is disposed on the first conductive layer, and a second active layer is disposed on the first gate insulating layer; and

[0019] A second gate insulating layer is disposed on the second active layer, and the first active layer is disposed on the second gate insulating layer;

[0020] The second active layer includes a second active portion, the second conductive layer includes a second electrode, the display panel is provided with a third hole, the third hole penetrates at least through the second gate insulating layer in the thickness direction to expose a portion of the second active portion, and the second electrode is connected to the second active portion through the third hole.

[0021] Optionally, the third hole penetrates the second gate insulating layer, the second active portion, and the first gate insulating layer in the thickness direction, and the second electrode is connected to the sidewall of the second active portion surrounding the third hole through the third hole.

[0022] Optionally, the display panel further includes a third conductive layer, which is disposed on the second active layer, and the second conductive layer is disposed on the third conductive layer;

[0023] The third conductive layer includes a first gate and a second gate, wherein the first gate overlaps with the first active portion in the thickness direction, and the second gate overlaps with the second active portion in the thickness direction.

[0024] Optionally, the first conductive layer further includes a third gate, which overlaps with the second active portion in the thickness direction, and the third gate is electrically connected to the first conductive portion.

[0025] Optionally, the display panel further includes:

[0026] A first passivation layer is disposed on the second conductive layer; and

[0027] A first electrode layer is disposed on the first passivation layer;

[0028] The first electrode layer includes a pixel electrode, the display panel has a fourth hole, the fourth hole penetrates the first passivation layer and the second gate insulating layer in the thickness direction to expose a portion of the second active part, and the pixel electrode is connected to the second active part through the fourth hole.

[0029] Optionally, the display panel has a display area and a non-display area disposed around the display area, and the display panel includes a driving transistor located in the display area and a switching transistor located in the non-display area;

[0030] The switching transistor includes the first active portion, and the driving transistor includes the second active portion.

[0031] In the display panel of this application embodiment, by making a first hole penetrate the first active portion and the first insulating layer located below the first active portion, the first electrode can be connected to the first active portion exposed on the sidewall of the first hole through the first hole, and a second hole can be made to penetrate the first insulating layer, so that the second conductive portion can be connected to the first conductive portion through the second hole. In this way, the first hole and the second hole can be etched simultaneously using the same photomask, without the need to use different photomasks to etch the first hole and the second hole separately. Therefore, the number of photomasks can be reduced and the manufacturing process can be simplified, thereby improving the production efficiency of the display panel and reducing the production cost.

[0032] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0035] Figure 1 A top view of a display panel provided for an embodiment of this application;

[0036] Figure 2 A schematic diagram of the film layer structure of a first type of display panel provided for embodiments of this application;

[0037] Figures 3a to 3k A schematic diagram illustrating a method for manufacturing a first display panel according to an embodiment of this application;

[0038] Figure 4 A schematic diagram of the film layer structure of a second type of display panel provided for an embodiment of this application;

[0039] Figure 5 A schematic diagram of a display device provided for an embodiment of this application. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0041] Embodiments of this application provide a display panel, which includes a first conductive layer, at least one first insulating layer, a first active layer, and a second conductive layer. The first conductive layer includes a first conductive portion. The first insulating layer is disposed on the first conductive layer. The first active layer is disposed on the first insulating layer and includes a first active portion. The second conductive layer is disposed on the first active layer and includes a first electrode and a second conductive portion. The display panel has a first hole and a second hole. The first hole penetrates the first active portion and the first insulating layer in the thickness direction of the display panel. The first electrode is connected to the sidewall of the first active portion surrounding the first hole through the first hole. The second hole penetrates the first insulating layer in the thickness direction, and the second conductive portion is connected to the first conductive portion through the second hole.

[0042] In the embodiments of this application, by making the first hole penetrate the first active portion and the first insulating layer located below the first active portion, the first electrode can be connected to the sidewall of the active portion surrounding the first hole through the first hole, and the second hole can penetrate the first insulating layer, so that the second conductive portion can be connected to the first conductive portion through the second hole. In this way, the first hole and the second hole can be etched simultaneously using the same photomask, without the need to use different photomasks to etch the first hole and the second hole separately. Therefore, the number of photomasks can be reduced and the manufacturing process can be simplified, thereby improving the production efficiency of the display panel and reducing the production cost.

[0043] Please see Figure 1 , Figure 1This is a top view of a display panel provided in an embodiment of this application. The display panel 100 includes a display area AA and a non-display area NA. The non-display area NA is disposed around the periphery of the display area AA. The display area AA is an area for displaying images. The display area AA may have multiple sub-pixels and pixel driving circuits for driving the sub-pixels to emit light. The non-display area NA is an area for placing driving circuits and signal traces related to the display function. The driving circuits related to the display function may include, but are not limited to, gate driving circuits.

[0044] Please see Figure 2 , Figure 2 This is a schematic diagram of the film layer structure of a first display panel provided in an embodiment of this application. The display panel 100 includes a first conductive layer 1, at least one first insulating layer 2, a first active layer 3, and a second conductive layer 4. The first conductive layer 1 includes a first conductive portion 11. The first insulating layer 2 is disposed on the first conductive layer 1. The first active layer 3 is disposed on the first insulating layer 2 and includes a first active portion 31. The second conductive layer 4 is disposed on the first active layer 3 and includes a first electrode 41 and a second conductive portion 42.

[0045] like Figure 2 As shown, the display panel has a first hole H1 and a second hole H2. The first hole H1 penetrates the first active part 31 and the first insulating layer 2 in the thickness direction of the display panel. The sidewall of the first hole H1 exposes the first active part 31. The first electrode 41 is partially formed on the sidewall of the first hole H1 and directly contacts the first active part 31 exposed on the sidewall of the first hole H1, thereby realizing the electrical connection between the first electrode 41 and the first active part 31.

[0046] like Figure 2 As shown, the second hole H2 penetrates the first insulating layer 2 in the thickness direction. The second hole H2 exposes the side surface of the first conductive part 11 near the first active layer 3. The second conductive part 42 directly contacts the side surface of the first conductive part 11 near the first active layer 3 through the second hole H2, thereby realizing the electrical connection between the second conductive part 42 and the first conductive part 11.

[0047] In the embodiments of this application, during the process of etching the first insulating layer 2 to form the second hole H2, the first active portion 31 on the first insulating layer 2 can be etched simultaneously. Because the second hole H2 is deeper, after etching through the first active portion 31, the etching does not stop but continues to etch the first insulating layer 2 below the first active portion 31 until the first conductive portion 11 is reached. At this point, the etching solution can no longer etch the first conductive portion 11, and the etching process stops. This results in the first hole H1 not only penetrating the first active portion 31 but also penetrating the first insulating layer 2, just like the second hole H2. In this way, the first hole and the second hole can be formed simultaneously using the same photomask, eliminating the need for separate photomasks. Therefore, the number of photomasks can be reduced, and the manufacturing process can be simplified, thereby improving the production efficiency of the display panel and reducing production costs.

[0048] In some embodiments, such as Figure 2 As shown, the first active portion 31 includes a channel portion 311 and doped portions 312 disposed on both sides of the channel portion 311. The material of the channel portion 311 can be an undoped intrinsic semiconductor material, while the doped portion 312 is an ion-doped intrinsic semiconductor material. A first hole H1 penetrates the doped portion 312 in the thickness direction. The first electrode 41 is connected to the doped portion 312 exposed on the sidewall of the first hole H1 through the first hole H1. The doped portion 312 can reduce the contact barrier between the first electrode 41 and the channel portion 311.

[0049] In some embodiments, such as Figure 2 As shown, the display panel 100 includes a switching transistor T2, which includes a first active portion 31. The second conductive layer 4 may include a plurality of first electrodes 41, one of which serves as the source of the switching transistor T2, and the other first electrode 41 serves as the drain of the switching transistor T2. The display panel may be provided with a plurality of first holes H1, one of which penetrates a doped portion 312 on one side of the channel portion 311, and the other first hole H1 penetrates a doped portion 312 on the other side of the channel portion 311. The source and drain of the switching transistor T2 are respectively connected to the corresponding doped portion 312 through the corresponding first hole H1.

[0050] In some embodiments, such as Figure 2 As shown, the doped portion 312 includes a heavily doped portion 3121 and a lightly doped portion 3122. The lightly doped portion 3122 is located between the heavily doped portion 3121 and the channel portion 311, and the first hole H1 penetrates the heavily doped portion 3121.

[0051] In some embodiments, such as Figure 2As shown, the first hole H1 penetrates the middle region of the heavily doped portion 3121, and the inner wall of the periphery of the first hole H1 exposes the heavily doped portion 3121, so that the first electrode 41 and the heavily doped portion 3121 form a ring-shaped contact. This can increase the contact area between the first electrode 41 and the heavily doped portion 3121, thereby reducing the contact resistance between the first electrode 41 and the heavily doped portion 3121.

[0052] In some embodiments, such as Figure 2 As shown, the display panel 100 also includes a second active layer 5. The material of the first active layer 3 includes a silicon semiconductor material, which can be amorphous silicon or polycrystalline silicon. The material of the second active layer 5 includes an oxide semiconductor material, which can be any one of metal oxide semiconductor materials such as indium gallium zinc oxide, zinc tin oxide, and indium zinc oxide.

[0053] In some embodiments, such as Figure 2 As shown, the display panel 100 also includes a driving transistor T1, which includes a second active part 51, and a switching transistor T2, which includes a first active part 31. That is, the driving transistor is an oxide thin film transistor, the driving transistor T1 is located in the display area AA, and the switching transistor T2 is a low temperature polycrystalline silicon thin film transistor, the switching transistor T2 is located in the non-display area.

[0054] In some embodiments, such as Figure 2 As shown, the second active layer 5 is disposed on the first conductive layer 1, and the first active layer 3 is disposed on the second active layer 5.

[0055] In some embodiments, such as Figure 2 As shown, the display panel 100 includes two first insulating layers 2, each including a first gate insulating layer 21 and a second gate insulating layer 22. The display panel also includes a substrate 10, with a first conductive layer 1 disposed on the substrate 10, a first gate insulating layer 21 disposed on the first conductive layer 1, a second active layer 5 disposed on the first gate insulating layer 21, a second gate insulating layer 22 disposed on the second active layer 5, and a first active layer 3 disposed on the second gate insulating layer 22.

[0056] In the embodiments of this application, by disposing the first active layer 3 on the second active layer 5, the first gate insulating layer 21 at the bottom of the second active layer 5 can be used as a buffer layer for the first active layer 3. This eliminates the need for the original buffer layer located below the low-temperature polycrystalline silicon thin-film transistor and the buffer layer manufacturing process, thereby simplifying the film structure and process of the display panel, improving the production efficiency of the display panel, and reducing the production cost.

[0057] In some embodiments, the second active layer 5 includes a second active portion 51, the second conductive layer 4 includes a second electrode 43, the display panel is provided with a third hole H3, the third hole H3 penetrates at least through the second gate insulating layer 22 in the thickness direction to expose a portion of the second active portion 51, and the second electrode 43 is connected to the second active portion 51 through the third hole H3.

[0058] In some embodiments, such as Figure 2 As shown, the driving transistor T1 includes a second active portion 51 and a second electrode 43. The second electrode 43 serves as the drain of the driving transistor T1 and is connected to the data signal line. A third hole H3 penetrates the second gate insulating layer 22 in the thickness direction to expose the surface of the second active portion 51 away from the first conductive layer 1. The second electrode 43 contacts the surface of the second active portion 51 away from the first conductive layer 1 through the third hole H3, thereby achieving an electrical connection between the second electrode 43 and the second active portion 51.

[0059] In some embodiments, such as Figure 2 As shown, the display panel 100 further includes a third conductive layer 6, which is disposed on the second active layer 5. A second conductive layer 4 is disposed on the third conductive layer 6. The third conductive layer 6 includes a first gate 61 and a second gate 62. The first gate 61 overlaps with the first active portion 31 in the thickness direction and serves as the top gate of the switching transistor T2. The second gate 62 overlaps with the second active portion 51 in the thickness direction and serves as the top gate of the driving transistor T1.

[0060] In the embodiments of this application, by setting the first gate 61 of the switching transistor T2 and the second gate 62 of the driving transistor T1 in the same layer, the film layer structure and manufacturing process of the display panel can be further simplified, thereby improving the production efficiency of the display panel and reducing the production cost.

[0061] In some embodiments, such as Figure 2 As shown, the first conductive layer 1 also includes a third gate 12, which overlaps with the second active portion 51 in the thickness direction. The third gate 12 can serve as the bottom gate of the driving transistor T1. The third gate 12 is electrically connected to the first conductive portion 11 and the second gate 42. The first conductive portion 11 can serve as part of a scan line, and the second conductive portion 42 can serve as another part of a scan line. Through the second conductive portion 42 and the first conductive portion 11, the scan signal output by the gate driving circuit can be transmitted to the second gate 62 and the third gate 12 of the corresponding driving transistor T1 to control the conduction and shutdown of the driving transistor T1.

[0062] In some embodiments, such as Figure 2As shown, the display panel 100 also includes a third gate insulating layer 23 and an interlayer dielectric layer 24. The third gate insulating layer 23 is disposed on the first active layer 3 and the second gate insulating layer 22. The third conductive layer 6 is disposed on the third gate insulating layer 23. The interlayer dielectric layer 24 is disposed on the third conductive layer 6 and the third gate insulating layer 23. The second conductive layer 4 is disposed on the interlayer dielectric layer 24.

[0063] In some embodiments, such as Figure 2 The first hole H1 sequentially penetrates the interlayer dielectric layer 24, the third gate insulating layer 23, the first active portion 31, the second gate insulating layer 22, and the first gate insulating layer 21 in the thickness direction. The second hole H2 sequentially penetrates the interlayer dielectric layer 24, the third gate insulating layer 23, the second gate insulating layer 22, and the first gate insulating layer 21 in the thickness direction. The third hole H3 sequentially penetrates the interlayer dielectric layer 24, the third gate insulating layer 23, and the second gate insulating layer 22 in the thickness direction.

[0064] In some embodiments, such as Figure 2 As shown, the display panel also includes a first passivation layer 25 and a first electrode layer 7. The first passivation layer 25 is disposed on the second conductive layer 4, and the first electrode layer 7 is disposed on the first passivation layer 25. The first electrode layer 7 includes a pixel electrode 71. The display panel has a fourth hole H4, which penetrates the first passivation layer 25, the interlayer dielectric layer 24, the third gate insulating layer 23, and the second gate insulating layer 22 in the thickness direction to expose a portion of the second active portion 51. The pixel electrode 71 is connected to the second active portion 51 through the fourth hole H4.

[0065] In the embodiments of this application, the material of the first electrode layer 7 is a transparent conductive material, which may include, but is not limited to, polyimide. The pixel electrode 71 can replace the original metal drain of the driving transistor T1 and be directly connected to the second active part 51 through the fourth hole H4, which can further improve the aperture ratio of the display panel, thereby improving the transmittance of the display panel.

[0066] In some embodiments, such as Figure 2 As shown, the first passivation layer 25 can be a single-layer structure formed of any one of the inorganic insulating materials selected from silicon nitride, silicon oxide, and silicon oxynitride, or it can be a multilayer structure formed by stacking at least two of the above materials. Using the first passivation layer 25 to replace the planar layer originally located below the first electrode layer 7 is beneficial to improving the aperture ratio of the display panel.

[0067] In some embodiments, the thickness of the first passivation layer 25 is greater than or equal to 4000 angstroms. For example, the thickness of the first passivation layer 25 can be 4000 angstroms, 4300 angstroms, 4500 angstroms, 4700 angstroms, or 5000 angstroms. This not only allows the first passivation layer 25 to have good insulation properties to isolate the first electrode layer 7 from the second conductive layer 4, but also allows the first passivation layer 25 to have good flatness, thereby improving the flatness of the first electrode layer 7 formed above the first passivation layer 25, and thus improving the uniformity of the display brightness of the display panel.

[0068] In some embodiments, such as Figure 2 The display panel 100 further includes a second passivation layer 26 and a second electrode layer 8. The second passivation layer 26 is disposed on the first electrode layer 7 and the first passivation layer 25, and the second electrode layer 8 is disposed on the second passivation layer 26. The second electrode layer 8 includes a common electrode 81 and a third conductive portion 82. The second conductive layer 8 includes a fourth conductive portion 44, which is a common voltage signal line used to transmit a common voltage signal. The display panel has a fifth hole H5, which penetrates the second passivation layer 26 and the first passivation layer 25 in the thickness direction to expose part of the fourth conductive portion 44. The third conductive portion 82 is connected to the fourth conductive portion 44 through the fifth hole H5 and is electrically connected to the common electrode 81 to transmit the common voltage to the common electrode 81.

[0069] In some embodiments, the second passivation layer 26 can be a single-layer structure formed of any one of the inorganic insulating materials selected from silicon nitride, silicon oxide, and silicon oxynitride, or it can be a stacked structure formed by stacking at least two of the aforementioned materials. Replacing the planar layer originally located below the first electrode layer 7 with the first passivation layer 25 is beneficial for improving the aperture ratio of the display panel.

[0070] In some embodiments, the thickness of the second passivation layer 26 is greater than or equal to 600 angstroms and less than or equal to 3000 angstroms. For example, the thickness of the first passivation layer 25 can be 4000 angstroms, 4300 angstroms, 4500 angstroms, 4700 angstroms, or 5000 angstroms. This not only allows the second passivation layer 26 to have good insulation properties to isolate the second electrode layer 8 from the first electrode layer 7, but also allows the second passivation layer 26 to have good flatness, thereby improving the flatness of the second electrode layer 8 formed above the second passivation layer 26, and thus improving the uniformity of the display brightness of the display panel.

[0071] Combination Figures 3a to 3k As shown, Figures 3a to 3k A schematic diagram illustrating a first method for manufacturing a display panel according to an embodiment of this application. The method for manufacturing the display panel includes the following steps:

[0072] Step S1, as follows Figure 3aAs shown, a metal material is deposited on the substrate 10, and the metal material is etched to form a first conductive layer 1. The first conductive layer 1 includes a patterned first conductive portion 11 and a third gate 12.

[0073] Step S2, as follows Figure 3b As shown, a first gate insulating layer 21 is formed on the substrate 10 and the first conductive layer 1, and an oxide semiconductor material is formed on the first gate insulating layer 21. The oxide semiconductor material is etched to form a second active layer 5. The second active layer 5 includes a patterned second active portion 51.

[0074] Step S3, as follows Figure 3c As shown, a second gate insulating layer 22 is formed on the second active layer 5, and a layer of polysilicon semiconductor material is formed on the second gate insulating layer 22. The polysilicon semiconductor material is etched to form a first active layer 3. The first active layer 3 includes a patterned first active portion 31.

[0075] Step S4, as follows Figure 3d As shown, a third gate insulating layer 23 is formed on the first active layer 3, a metal material is deposited on the third gate insulating layer 23, and the metal material is etched to form a third conductive layer 6. The third conductive layer 6 includes a patterned first gate 61 and a second gate 62.

[0076] Step S5, as follows Figure 3e As shown, an interlayer dielectric layer 24 is formed on the third conductive layer 6. The interlayer dielectric layer 24 is etched to form a first hole H1 and a second hole H2. The first hole H1 passes through the interlayer dielectric layer 24, the third gate insulating layer 23, the first active part 31, the second gate insulating layer 22 and the first gate insulating layer 21 in the thickness direction. The second hole H2 passes through the interlayer dielectric layer 24, the third gate insulating layer 23, the second gate insulating layer 22 and the first gate insulating layer 21 in the thickness direction.

[0077] Step S6, as follows Figure 3f As shown, the interlayer dielectric layer 24 is etched to form a third hole H3, which sequentially penetrates the interlayer dielectric layer 24, the third gate insulating layer 23, and the second gate insulating layer 22 in the thickness direction.

[0078] Step S6, as follows Figure 3g As shown, a metal material is deposited on the interlayer dielectric layer 24, and the metal material is etched to form a second conductive layer 4. The second conductive layer 4 includes a patterned first electrode 41, a second conductive portion 42, a second electrode 43, and a fourth conductive portion 44.

[0079] Step S7, as follows Figure 3hAs shown, a first passivation layer 25 is formed on the second conductive layer 4. The first passivation layer 25 is etched to form a fourth hole H4. The fourth hole H4 penetrates the first passivation layer 25, the interlayer dielectric layer 24, the third gate insulating layer 23 and the second gate insulating layer 22 in the thickness direction.

[0080] Step S8, as follows Figure 3i As shown, a transparent conductive material is deposited on the first passivation layer 25, and the transparent conductive material is etched to form a first electrode layer 7. The first electrode layer 7 includes a plurality of patterned pixel electrodes 71.

[0081] Step S9, as follows Figure 3j As shown, a second passivation layer 26 is formed on the first electrode layer 7. The second passivation layer 26 is etched to form a fifth hole H5. The fifth hole H5 penetrates the second passivation layer 26 and the first passivation layer 25 in the thickness direction to expose part of the fourth conductive part 44.

[0082] Step S10, as follows Figure 3k As shown, a transparent conductive material is deposited on the second passivation layer 26, and the transparent conductive material is etched to form a second electrode layer 8. The second electrode layer 8 includes a patterned common electrode 81 and a third conductive part 82. The third conductive part 82 is connected to the fourth conductive part 44 through the fifth hole H5, and the third conductive part 82 is electrically connected to the common electrode 81.

[0083] In some embodiments, such as Figure 4 As shown, Figure 4 A schematic diagram of the film layer structure of a second type of display panel provided for an embodiment of this application. Figure 4 The structure of the second type of display panel shown is similar to... Figure 2 The structures of the display panels shown are roughly the same, except that the third hole H3 penetrates the second gate insulating layer 22, the second active part 51 and the first gate insulating layer 21 in the thickness direction, and the second electrode 43 is connected to the side wall of the second active part 51 surrounding the third hole H3 through the third hole H3.

[0084] like Figure 4 As shown, the third hole H3 penetrates the middle region of the second active part 51. The sidewall of the second active part 51 is arranged around the third hole H3. The second electrode 43 is partially formed on the sidewall of the second active part 51 surrounding the third hole H3 to form annular contact with the second active part 51. This can increase the contact area between the second electrode 43 and the second active part 51, thereby reducing the contact resistance between the second electrode 43 and the second active part 51.

[0085] exist Figure 4In the embodiment shown, during the process of etching the first insulating layer 2 to form the second hole H2, the first active portion 31 on the second gate insulating layer 22 and the second active portion 51 on the first gate insulating layer 21 can be etched simultaneously. Due to the greater depth of the second hole H2, the etching does not stop after the etching penetrates the first active portion 31 or the second active portion 51. Instead, it continues to etch the second gate insulating layer 22 and the first gate insulating layer 21 below the first active portion 31 and the first gate insulating layer 21 below the second active portion 51 until the first conductive portion 11 is etched. The etching solution can no longer etch the first conductive portion 11, and the etching process stops. This results in the first hole H1 penetrating not only the first active portion 31, but also penetrating the second gate insulating layer 22 and the first gate insulating layer 21, just like the second hole H2. The third hole H3 not only penetrates the second active portion 51, but also penetrates the first gate insulating layer 21, just like the second hole H2. This allows the same photomask to be used to simultaneously etch the first hole H1, the second hole H2, and the third hole H3, eliminating the need to use different photomasks to etch the first, second, and third holes separately. This reduces the number of photomasks and simplifies the manufacturing process, thereby improving the production efficiency of display panels and reducing production costs.

[0086] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of a display device provided in an embodiment of this application. The display device 1000 includes a display panel 100 and a housing 200, with the display panel 100 disposed on the housing 200. The display panel 100 can be any of the display panels provided in the above embodiments. The display device provided in the embodiments of this application can achieve the same technical effects as the display panels provided in any of the above embodiments, and will not be described in detail here.

[0087] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel, which includes a first conductive layer, at least one first insulating layer, a first active layer, and a second conductive layer. The first conductive layer includes a first conductive portion, the first active layer includes a first active portion, and the second conductive layer includes a first electrode and a second conductive portion. The display panel is provided with a first hole and a second hole. By making the first hole penetrate the first active portion and the first insulating layer, and making the second hole penetrate the first insulating layer, the first electrode can be connected to the first active portion through the first hole, and the second conductive portion can be connected to the first conductive portion through the second hole. In this way, the first hole and the second hole can be formed simultaneously by etching with the same photomask, without the need to use different photomasks to etch the first hole and the second hole separately. Therefore, the number of photomasks can be reduced and the manufacturing process can be simplified, thereby improving the production efficiency of the display panel and reducing the production cost.

[0088] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0089] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0090] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0091] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: The first conductive layer includes a first conductive portion; At least one first insulating layer is disposed on the first conductive layer; A first active layer is disposed on the first insulating layer, the first active layer including a first active portion; and A second conductive layer is disposed on the first active layer, and the second conductive layer includes a first electrode and a second conductive portion. The display panel is provided with a first hole and a second hole. The first hole penetrates the first active part and the first insulating layer in the thickness direction of the display panel. The first electrode is connected to the side wall of the first active part surrounding the first hole through the first hole. The second hole penetrates the first insulating layer in the thickness direction. The second conductive part is connected to the first conductive part through the second hole.

2. The display panel as described in claim 1, characterized in that, The first active portion includes a channel portion and doped portions disposed on both sides of the channel portion; The first hole penetrates the doped portion.

3. The display panel as described in claim 2, characterized in that, The doped portion includes a heavily doped portion and a lightly doped portion located between the heavily doped portion and the channel portion, and the first hole penetrates the heavily doped portion.

4. The display panel as described in claim 1, characterized in that, The display panel further includes a second active layer, wherein the material of the first active layer includes a silicon semiconductor material, and the material of the second active layer includes an oxide semiconductor material; The second active layer is disposed on the first conductive layer, and the first active layer is disposed on the second active layer.

5. The display panel as described in claim 4, characterized in that, The display panel includes two layers of the first insulating layer, and the two layers of the first insulating layer include: A first gate insulating layer is disposed on the first conductive layer, and a second active layer is disposed on the first gate insulating layer; and A second gate insulating layer is disposed on the second active layer, and the first active layer is disposed on the second gate insulating layer; The second active layer includes a second active portion, the second conductive layer includes a second electrode, the display panel is provided with a third hole, the third hole penetrates at least through the second gate insulating layer in the thickness direction to expose a portion of the second active portion, and the second electrode is connected to the second active portion through the third hole.

6. The display panel as described in claim 5, characterized in that, The third hole penetrates the second gate insulating layer, the second active portion, and the first gate insulating layer in the thickness direction, and the second electrode is connected to the sidewall of the second active portion surrounding the third hole through the third hole.

7. The display panel as described in claim 5, characterized in that, The display panel further includes a third conductive layer, which is disposed on the second active layer, and the second conductive layer is disposed on the third conductive layer; The third conductive layer includes a first gate and a second gate, wherein the first gate overlaps with the first active portion in the thickness direction, and the second gate overlaps with the second active portion in the thickness direction.

8. The display panel as described in claim 5, characterized in that, The first conductive layer further includes a third gate, which overlaps with the second active portion in the thickness direction, and the third gate is electrically connected to the first conductive portion.

9. The display panel as described in claim 5, characterized in that, The display panel also includes: A first passivation layer is disposed on the second conductive layer; and A first electrode layer is disposed on the first passivation layer; The first electrode layer includes a pixel electrode, the display panel has a fourth hole, the fourth hole penetrates the first passivation layer and the second gate insulating layer in the thickness direction to expose a portion of the second active part, and the pixel electrode is connected to the second active part through the fourth hole.

10. The display panel as claimed in claim 5, characterized in that, The display panel has a display area and a non-display area disposed around the display area, and the display panel includes a driving transistor located in the display area and a switching transistor located in the non-display area; The switching transistor includes the first active portion, and the driving transistor includes the second active portion.

Images