Packaging structure and electronic device

Abstract

The present disclosure relates to the technical field of semiconductor, and particularly relates to a packaging structure and an electronic device. The packaging structure comprises at least two layers of chips and a silicon bridge structure, the at least two layers of chips are arranged in a stacked mode with a spacing, the at least two layers of chips comprise a first layer of chips and a second layer of chips adjacent to each other, the first layer of chips comprises a plurality of first chips arranged with a spacing, the second layer of chips comprises a plurality of second chips arranged with a spacing, and the silicon bridge structure is arranged between the first layer of chips and the second layer of chips, and the silicon bridge structure is electrically connected with the plurality of first chips and the plurality of second chips to electrically connect the first chips and the second chips. The packaging structure of the embodiment of the present disclosure can improve the data transmission efficiency between the chips.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to a packaging structure and an electronic device. Background Technology

[0002] Three-dimensional integrated circuits (3D integrated circuits) are integrated circuits with multi-layer device structures, also known as stereoscopic integrated circuits. They have advantages such as high packaging density and high operating speed, which can meet the ever-increasing computing power demands. In related technologies, the chips in the multi-layer stacked chips of 3D integrated circuits are connected by traces on the substrate. The trace paths are relatively long, which affects the data transmission efficiency between chips. Utility Model Content

[0003] This disclosure aims to at least partially address one of the technical problems in the related art. To this end, embodiments of this disclosure propose a packaging structure that can improve the efficiency of data transmission between chips.

[0004] This disclosure also proposes an electronic device.

[0005] The packaging structure of this disclosure includes: at least two chip layers stacked at intervals, the at least two chip layers including a first chip layer and a second chip layer adjacent to each other, the first chip layer including a plurality of first chips arranged at intervals, and the second chip layer including a plurality of second chips arranged at intervals; a silicon bridge structure disposed between the first chip layer and the second chip layer, the silicon bridge structure being electrically connected to the plurality of first chips and to the plurality of second chips to electrically connect the first chip and the second chip.

[0006] The packaging structure of this disclosure embodiment provides a silicon bridge structure between adjacent first-layer chips and second-layer chips. The silicon bridge structure is electrically connected to multiple spaced-apart first chips and multiple spaced-apart second chips, thereby realizing the electrical connection between multiple first chips and multiple second chips. This achieves interconnection between the first chips and the second chips, as well as interconnection between multiple first chips and multiple second chips, improving the data transmission efficiency between chips and thus improving the performance of the packaging structure.

[0007] In some embodiments, there are two of each of the first and second chips, with one first chip stacked with one second chip, and another first chip stacked with another second chip.

[0008] In some embodiments, there are four first chips arranged in a rectangular array, and four second chips arranged in a rectangular array. The first chips and the second chips correspond one-to-one and are stacked together.

[0009] In some embodiments, the silicon bridge structure includes a silicon bridge body and bumps, the bumps being disposed on the silicon bridge body and electrically connected to the first chip and the second chip.

[0010] In some embodiments, the silicon bridge body has a first surface and a second surface, and the bumps include a first bump and a second bump electrically connected to each other, the first bump being disposed on the first surface and the second bump being disposed on the second surface, the first bump being electrically connected to the first chip and the second bump being electrically connected to the second chip.

[0011] In some embodiments, both the first bump and the second bump are multiple.

[0012] In some embodiments, the silicon bridge structure further includes connecting lines disposed within the silicon bridge body, the connecting lines connecting the first bumps to each other and / or connecting the second bumps to each other and / or connecting the first bumps and the second bumps to each other.

[0013] In some embodiments, the passive surface of the first chip faces the active surface of the second chip.

[0014] In some embodiments, the packaging structure further includes a first electrical connector connected between the first chip and the second chip stacked on top of each other.

[0015] In some embodiments, the packaging structure further includes a substrate, wherein the at least two chip layers are disposed on the substrate and electrically connected to the substrate.

[0016] In some embodiments, the packaging structure further includes a second electrical connector disposed between the substrate and the active surface of a layer of chip adjacent to the substrate, for electrically connecting the substrate and the layer of chip.

[0017] The electronic device of this disclosure includes: a printed circuit board; a packaging structure, the packaging structure including the packaging structure described in any of the above embodiments, and the printed circuit board being connected to the packaging structure.

[0018] The electronic device of this disclosure improves the performance of the electronic device by including the packaging structure of the above embodiments. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the packaging structure according to an embodiment of the present disclosure.

[0020] Figure 2 This is a schematic diagram of a silicon bridge structure according to an embodiment of the present disclosure.

[0021] Figure label:

[0022] First layer chip 1, first chip 11, active surface 111 of the first chip, passive surface 112 of the first chip

[0023] Second-layer chip 2, second chip 21, active surface 211 of the second chip,

[0024] Silicon bridge structure 3, silicon bridge body 31, first surface 311, second surface 312.

[0025] Bump 32, first bump 321, second bump 322.

[0026] Connector 33,

[0027] First electrical connector 4, substrate 5, second electrical connector 6. Detailed Implementation

[0028] Embodiments of this disclosure are described in detail below, with examples of these embodiments illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting it.

[0029] The following is in conjunction with the appendix Figures 1-2 The packaging structure of the embodiments of this disclosure will be described in detail.

[0030] The packaging structure of this embodiment includes at least two chip layers and a silicon bridge structure 3. The at least two chip layers are stacked at intervals, including a first chip layer 1 and a second chip layer 2 adjacent to each other. The first chip layer 1 includes a plurality of first chips 11 arranged at intervals, and the second chip layer 2 includes a plurality of second chips 21 arranged at intervals. The silicon bridge structure 3 is disposed between the first chip layer 1 and the second chip 2, and is electrically connected to both the plurality of first chips 11 and the plurality of second chips 21, thereby electrically connecting the first chip 11 and the second chip 21.

[0031] The packaging structure of this disclosure embodiment, by setting a silicon bridge structure 3 between adjacent first-layer chips 1 and second-layer chips 2, and using the silicon bridge structure 3 to electrically connect with multiple spaced-apart first chips 11 and multiple spaced-apart second chips 21, realizes the electrical connection between multiple first chips 11 and multiple second chips 21, thereby realizing the interconnection between first chips 11 and second chips 21, as well as the interconnection between multiple first chips 11 and multiple second chips 21, improving the data transmission efficiency between chips, and thus improving the performance of the packaging structure.

[0032] Specifically, such as Figure 1As shown, for ease of description, the stacking direction of the first layer chip 1 and the second layer chip 2 is the same as the vertical direction. The first layer chip 1 and the second layer chip 2 are stacked in the vertical direction. The first layer chip 1 includes a plurality of first chips 11 arranged at intervals in the left-right direction and / or front-back direction. The second layer chip 2 includes a plurality of second chips 21 arranged at intervals in the left-right direction and / or front-back direction. That is, the plurality of first chips 11 are arranged at intervals, and the plurality of second chips 21 are arranged at intervals.

[0033] The silicon bridge structure 3 is disposed between the first layer chip 1 and the second layer chip 2. The lower end of the silicon bridge structure 3 is electrically connected to multiple first chips 11, and the upper end of the silicon bridge structure 3 is electrically connected to multiple second chips 21, thereby realizing three-dimensional interconnection between multiple first chips 11 and multiple second chips 21. In other words, in this embodiment, the silicon bridge structure 3 realizes the electrical connection between multiple first chips 11, the electrical connection between multiple second chips 21, and the electrical connection between first chips 11 and second chips 21.

[0034] Compared to the method in related technologies where each stacked chip is connected to the other chips via traces on the substrate 5, this embodiment sets up a silicon bridge structure 3 between adjacent first-layer chips 1 and second-layer chips 2. The silicon bridge structure 3 directly connects multiple first chips 11 and multiple second chips 21, which greatly shortens the interconnection path and thus shortens the data transmission path, enabling more efficient information access and transmission between chips.

[0035] For example, the first chip 11 and the second chip 21 can be a memory chip DRAM (Dynamic Random Access Memory), a central processing unit chip CPU (Central Processing Unit), a graphics processing chip GPU (Graphics Processing Unit), or other functional chips.

[0036] In some embodiments, there are two first chips 11 and two second chips 21, with one first chip 11 stacked with one second chip 21, and another first chip 11 stacked with another second chip 21.

[0037] In this embodiment, by setting two first chips 11 and two second chips 21, and using a silicon bridge structure 3 to electrically connect the two first chips 11 and the two second chips 21, three-dimensional interconnection between the four chips is realized, enabling more efficient information access and transmission between the chips, thereby improving data transmission efficiency.

[0038] Specifically, such as Figure 1As shown, two first chips 11 are arranged at intervals in the left-right direction, and two second chips 21 are arranged at intervals in the left-right direction and are configured in a one-to-one correspondence with the two first chips 11. That is, the second chip 21 on the left is stacked with the first chip 11 on the left, and the second chip 21 on the right is stacked with the first chip 11 on the right. A silicon bridge structure 3 is disposed between the first layer chip 1 and the second layer chip 2. The upper end of the silicon bridge structure 3 is electrically connected to the two second chips 21, and the lower end of the silicon bridge structure 3 is electrically connected to the two first chips 11, realizing three-dimensional interconnection between the stacked chips.

[0039] In some embodiments, there are four first chips 11 arranged in a rectangular array, and four second chips 21 arranged in a rectangular array. The first chips 11 and the second chips 21 correspond one-to-one and are stacked together.

[0040] In this embodiment, by setting four first chips 11 and four second chips 21, and using a silicon bridge structure 3 to electrically connect the four first chips 11 and the four second chips 21, three-dimensional interconnection between eight chips is achieved, enabling more efficient information access and transmission between chips, thereby improving data transmission efficiency.

[0041] Specifically, the four first chips 11 are divided into two groups, and the two groups of first chips 11 are arranged at intervals in the front-to-back direction. Each group of first chips 11 includes two first chips 11 arranged at intervals in the left-to-right direction. The four second chips 21 are divided into two groups, and the two groups of second chips 21 are arranged at intervals in the front-to-back direction. Each group of second chips 21 includes two second chips 21 arranged at intervals in the left-to-right direction.

[0042] Four first chips 11 are stacked in a one-to-one correspondence with four second chips 21. Specifically, the second chip 21 located at the front left end is stacked with the first chip 11 located at the front left end, the second chip 21 located at the front right end is stacked with the first chip 11 located at the front right end, the second chip 21 located at the rear left end is stacked with the first chip 11 located at the rear left end, and the second chip 21 located at the rear right end is stacked with the first chip 11 located at the rear right end. A silicon bridge structure 3 is disposed between the first layer chip 1 and the second layer chip 2. The upper end of the silicon bridge structure 3 is electrically connected to the four second chips 21, and the lower end of the silicon bridge structure 3 is electrically connected to the four first chips 11.

[0043] In some embodiments, such as Figure 2As shown, the silicon bridge structure 3 includes a silicon bridge body 31 and bumps 32. The bumps 32 are disposed on the silicon bridge body 31 and are electrically connected to the first chip 11 and the second chip 21. By disposing of the bumps 32 on the silicon bridge body 31 and directly connecting them to the first chip 11 and the second chip 21, the interconnection path between the chips can be shortened, thereby reducing parasitic resistance in the interconnection path, improving signal transmission efficiency, and ultimately improving the overall performance of the package structure.

[0044] Optionally, the bump 32 is a metal bump, for example, a copper bump or a solder ball. For example, the silicon bridge body 31 is made of silicon material.

[0045] In some embodiments, the silicon bridge body 31 has a first surface 311 and a second surface 312, and the bump 32 includes a first bump 321 and a second bump 322 that are electrically connected to each other. The first bump 321 is disposed on the first surface 311, and the second bump 322 is disposed on the second surface 312. The first bump 321 is electrically connected to the first chip 11, and the second bump 322 is electrically connected to the second chip 21.

[0046] In this embodiment, by setting a first bump 321 and a second bump 322 that are electrically connected to each other on the silicon bridge body 31, the first bump 321 is directly electrically connected to the first chip 11, and the second bump 322 is directly electrically connected to the second chip 21, thereby realizing the interconnection between the first chip 11 and the second chip 21, further shortening the interconnection path between the chips, and further improving the signal transmission efficiency.

[0047] Specifically, such as Figure 2 As shown, the first surface 311 of the silicon bridge body 31 is the lower surface of the silicon bridge body 31, the second surface 312 of the silicon bridge body 31 is the upper surface of the silicon bridge body 31, the first bump 321 is disposed on the first surface 311 and protrudes downward from the first surface 311, and the second bump 322 is disposed on the second surface 312 and protrudes upward from the second surface 312.

[0048] In some embodiments, there are multiple first bumps 321 and multiple second bumps 322. In this embodiment, by setting multiple first bumps 321 and multiple second bumps 322, it is convenient for multiple first bumps 321 to be electrically connected to multiple first chips 11 respectively, and multiple second bumps 322 to be electrically connected to multiple second chips 21 respectively, thereby reducing interference between different signal paths and improving signal transmission quality.

[0049] Specifically, such as Figure 2As shown, there are four first bumps 321. The two first bumps 321 on the left are electrically connected to the first chip 11 on the left, and the two first bumps 321 on the right are electrically connected to the first chip 11 on the right. There are four second bumps 322. The two second bumps 322 on the left are electrically connected to the second chip 21 on the left, and the two second bumps 322 on the right are electrically connected to the second chip 21 on the right.

[0050] In some embodiments, the silicon bridge structure 3 further includes a connecting line 33 disposed within the silicon bridge body 31. The connecting line 33 connects the first bumps 321 to each other and / or connects the second bumps 322 to each other and / or connects the first bumps 321 and the second bumps 322 to each other. The interconnection of the first bumps 321 and the second bumps 322 is achieved through the connection line 33.

[0051] Specifically, such as Figure 2 As shown, connecting line 33 connects the first protrusions 321 to each other and / or connects the second protrusions 322 to each other and / or connects the first protrusions 321 and the second protrusions 322 to each other. This can be understood as: connecting line 33 connects the first protrusions 321 to each other; or, connecting line 33 connects the second protrusions 322 to each other; or, connecting line 33 connects the first protrusions 321 to each other and connects the second protrusions 322 to each other; or, connecting line 33 connects the first protrusions 321 to each other and connects the first protrusions 321 and the second protrusions 322 to each other; or, connecting line 33 connects the first protrusions 321 to each other and connects the second protrusions 322 to each other and connects the first protrusions 321 and the second protrusions 322 to each other.

[0052] For example, connector 33 is a copper wire.

[0053] In some embodiments, the passive surface 112 of the first chip faces the active surface 211 of the second chip. In this embodiment, the passive surface 112 of the first chip faces the active surface 211 of the second chip, thereby achieving interconnection between the passive surface 112 of the first chip and the active surface 211 of the second chip. That is to say, the silicon bridge structure 3 not only acts on the active surface 211 of the second chip, but also constructs a connection channel on the passive surface 112 of the first chip, further improving the interconnection efficiency between chips.

[0054] Specifically, such as Figure 1 As shown, the passive surface 112 of the first chip faces the active surface 211 of the second chip, which can be understood as: the passive surface 112 of the first chip faces the active surface 211 of the second chip, and the active surface 211 of the second chip faces the passive surface 112 of the first chip.

[0055] In some embodiments, such as Figure 1 As shown, the packaging structure also includes a first electrical connector 4, which is connected between the first chip 11 and the second chip 21 that are stacked on top of each other. The first electrical connector 4 enables electrical connection between the stacked first chip 11 and the second chip 21.

[0056] Optionally, there are multiple first electrical connectors 4, which are spaced apart between the stacked first chip 11 and second chip 21. By using multiple first electrical connectors 4, the connection area between the first chip 11 and the second chip 21 is increased, thereby improving the reliability of the packaging structure.

[0057] For example, the first electrical connector 4 is a copper block or a solder ball.

[0058] In some embodiments, such as Figure 1 As shown, the packaging structure also includes a substrate 5, with at least two chip layers disposed on and electrically connected to the substrate 5. By disposing of at least two chip layers on the substrate 5 and electrically connecting them to the substrate 5, the stability of the chip during the packaging process can be improved, while achieving high-density interconnection between the chip and the substrate 5, thereby increasing the integration of the packaging structure.

[0059] In some embodiments, such as Figure 1 As shown, the packaging structure also includes a second electrical connector 6, which is disposed between the substrate 5 and the active surface of a layer of chips adjacent to the substrate 5, to electrically connect the substrate 5 and the layer of chips. The second electrical connector 6 enables electrical connection between the substrate 5 and the active surface of the layer of chips adjacent to the substrate 5.

[0060] Specifically, such as Figure 1 As shown, the chip layer adjacent to the substrate 5 is the first chip layer 1, that is, the second electrical connector 6 is disposed between the active surface 111 of the first chip and the substrate 5.

[0061] Optionally, multiple second electrical connectors 6 are provided, spaced apart between the substrate 5 and the active surface of a chip layer adjacent to the substrate 5. The arrangement of multiple second electrical connectors 6 increases the connection area between the substrate 5 and the chip layer, thereby improving the reliability of the packaging structure.

[0062] For example, the second electrical connector 6 is a copper block or a solder ball.

[0063] The electronic device according to embodiments of this disclosure includes a printed circuit board and a package structure. The package structure includes a package structure employing any of the above embodiments, and the printed circuit board is connected to the package structure.

[0064] The electronic device of this disclosure improves the performance of the electronic device by including the packaging structure of the above embodiments.

[0065] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0067] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0068] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0069] In this disclosure, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0070] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A packaging structure, characterized in that, include: At least two layers of chips are stacked and arranged at intervals between each other. The at least two layers of chips include a first layer of chips and a second layer of chips that are adjacent to each other. The first layer of chips includes a plurality of first chips that are arranged at intervals between each other, and the second layer of chips includes a plurality of second chips that are arranged at intervals between each other. A silicon bridge structure is disposed between a first-layer chip and a second-layer chip. The silicon bridge structure is electrically connected to a plurality of first chips and a plurality of second chips to electrically connect the first chips and the second chips.

2. The packaging structure according to claim 1, characterized in that, There are two of each chip: one first chip stacked with one second chip, and another first chip stacked with another second chip.

3. The packaging structure according to claim 1, characterized in that, The first chip consists of four chips arranged in a rectangular array, and the second chip consists of four chips arranged in a rectangular array. The first chip and the second chip correspond one-to-one and are stacked together.

4. The packaging structure according to claim 1, characterized in that, The silicon bridge structure includes a silicon bridge body and bumps. The bumps are disposed on the silicon bridge body and are electrically connected to the first chip and the second chip.

5. The packaging structure according to claim 4, characterized in that, The silicon bridge body has a first surface and a second surface. The bumps include a first bump and a second bump that are electrically connected to each other. The first bump is disposed on the first surface, and the second bump is disposed on the second surface. The first bump is electrically connected to the first chip, and the second bump is electrically connected to the second chip.

6. The packaging structure according to claim 5, characterized in that, There are multiple first bumps and multiple second bumps.

7. The packaging structure according to claim 5, characterized in that, The silicon bridge structure also includes connecting lines disposed within the silicon bridge body, the connecting lines connecting the first bumps to each other and / or connecting the second bumps to each other and / or connecting the first bumps and the second bumps to each other.

8. The packaging structure according to any one of claims 1-7, characterized in that, The passive surface of the first chip faces the active surface of the second chip.

9. The packaging structure according to any one of claims 1-7, characterized in that, The packaging structure also includes a first electrical connector, which is connected between the first chip and the second chip stacked on top of each other.

10. The packaging structure according to any one of claims 1-7, characterized in that, The packaging structure also includes a substrate, and the at least two chip layers are disposed on the substrate and electrically connected to the substrate.

11. The packaging structure according to claim 10, characterized in that, The packaging structure further includes a second electrical connector, which is disposed between the substrate and the active surface of a layer of chip adjacent to the substrate, to electrically connect the substrate and the layer of chip.

12. An electronic device, characterized in that, include: Printed circuit boards; The packaging structure is the packaging structure according to any one of claims 1-11, and the printed circuit board is connected to the packaging structure.

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