A multi-protocol display interface compatible circuit

Abstract

The utility model relates to multi -protocol display interface technical field discloses a kind of multi -protocol display interface compatible circuit, comprising: interface signal input circuit, video processing circuit, video interface circuit, video format conversion circuit, RGB TTL screen circuit, MIPI screen circuit and LVDS screen circuit, the input end of interface signal input circuit connects external computer video signal output end, the input end of video processing circuit is connected to the output end of interface signal input circuit, the input end of video interface circuit is connected to the output end of video processing circuit, the input end of video format conversion circuit is respectively connected to the output end of video interface circuit LVDS screen circuit and, the input end of MIPI screen circuit is respectively connected to the output end of video format conversion circuit RGB TTL screen circuit.The circuit can achieve the purpose that single circuit board is compatible with 3 kinds of protocol screen display, reduce hardware iteration development and production cost.

Description

Technical Field

[0001] This utility model relates to the field of multi-protocol display interface technology, specifically to a multi-protocol display interface compatible circuit. Background Technology

[0002] In recent years, with the rapid development of the electronics industry, intelligent display devices have also achieved remarkable success, and high-definition displays have gained favor among consumers. Currently, high-definition display protocol interfaces include RGB, LVDS, MIPI, eDP, HDMI, miniLVDS, V-by-One, etc.

[0003] MIPI stands for Mobile Industry Processor Interface. The MIPI protocol is an open standard proposed by the MIPI Alliance, designed to provide a high-speed, low-power serial interface for communication between processors and other modules in mobile devices. It is primarily used for communication between cameras (via the CSI-2 protocol) and display devices (via the DSI protocol) and processors. The MIPI protocol includes a physical layer (such as D-PHY and C-PHY) and a protocol layer, supporting high-speed data transmission and low-power modes, and is widely used in smartphones, tablets, VR devices, smart TVs, automotive electronics, and other fields. Compared to traditional RGB and LVDS interfaces, the MIPI interface offers higher bandwidth, lower power consumption, and smaller size, making it particularly suitable for mobile devices and embedded applications.

[0004] LVDS stands for Low Voltage Differential Signaling. It's a signaling technology for high-speed data transmission that uses a pair of differential signal lines (positive and negative) to transmit data. The main characteristics of LVDS are low voltage swing (approximately 350mV), current-driven mode, and high data transmission rate. Due to its differential signal characteristics, LVDS has good noise immunity and low electromagnetic interference (EMI) performance. LVDS is commonly used for point-to-point or point-to-multipoint connections and is widely applied in LCD displays, high-speed backplanes, cables, and board-to-board data transmission.

[0005] Among them, RGB TTL (Transistor-Transistor Logic) is an RGB signal transmission standard based on digital logic levels, mainly used for early computer video output (such as VGA), industrial control displays, or old game consoles (such as NES / FC).

[0006] However, display protocol interfaces on the market are generally independent, which is cumbersome in hardware iteration development and cannot reduce hardware iteration openness or lower costs.

[0007] Therefore, a circuit solution compatible with multiple protocol display interfaces is needed to integrate physical sockets for the three independent interfaces of RGB TTL, LVDS and MIPI on a single circuit board, thereby achieving the goal of a single circuit board being compatible with screens displaying three protocols (TTL protocol, LVDS protocol and MIPI protocol), and reducing hardware iteration development and production costs. Utility Model Content

[0008] The purpose of this utility model is to provide a circuit scheme that is compatible with multiple protocol display interfaces. By adopting an interface signal input circuit, a video processing circuit, a video interface circuit, a video format conversion circuit, an RGB TTL screen circuit, a MIPI screen circuit, and an LVDS screen circuit, it is possible to achieve the goal of a single circuit board being compatible with three protocols (TTL protocol, LVDS protocol, and MIPI protocol) for screen display, thereby reducing hardware iteration development and production costs.

[0009] The specific technical solution of this utility model is as follows:

[0010] A multi-protocol display interface compatible circuit includes: an interface signal input circuit, a video processing circuit, a video interface circuit, a video format conversion circuit, an RGB TTL screen circuit, a MIPI screen circuit, and an LVDS screen circuit. The input terminal of the interface signal input circuit is connected to the video signal output terminal of an external computer. The output terminal of the interface signal input circuit is connected to the input terminal of the video processing circuit. The output terminal of the video processing circuit is connected to the input terminal of the video interface circuit. The output terminal of the video interface circuit is connected to the input terminal of the LVDS screen circuit and the input terminal of the video format conversion circuit. The output terminal of the video format conversion circuit is connected to the input terminal of the RGB TTL screen circuit and the input terminal of the MIPI screen circuit.

[0011] The video interface circuit includes a direct connection port circuit and a disconnectable connection port circuit. The input terminals of the direct connection port circuit and the disconnectable connection port circuit are respectively connected to the output terminals of the video processing circuit. The output terminal of the direct connection port circuit is connected to the input terminal of the LVDS screen circuit, and the output terminal of the disconnectable connection port circuit is connected to the input terminal of the video format conversion circuit.

[0012] Furthermore, the interface signal input circuit is selected as a USB interface circuit or a Type-C interface circuit.

[0013] Further, the video processing circuit includes chip U4, magnetic bead FB3, capacitors C34 and C35, resistors R31, R42, R43, C45, R49, and C50, a crystal resonator, magnetic bead FB9, capacitors C71 and C72. Terminal "91" of chip U4 is connected to one end of magnetic bead FB3 and one end of capacitor C35. The other end of magnetic bead FB3 and one end of capacitor C34 are connected to an external DC power supply. The other ends of capacitors C35 and C34 are grounded together with terminal "92" of chip U4. Terminal "90" of chip U4 is connected to one end of resistor R31, and the other end of resistor R31 is grounded. Terminal "64" of chip U4 is connected to one end of resistor R42, and the other end of resistor R42 is connected to the input terminal of the interface signal input circuit. Terminal "60" of chip U4 is connected to one end of resistor R43. One end of the resistor R43 is grounded. The other end of the chip U4 “49” terminal is connected to one end of the capacitor C45, and the other end of the capacitor C45 is grounded. The other end of the chip U4 “41” terminal is connected to one end of the crystal resonator. The other end of the chip U4 “40” terminal is connected to the other end of the crystal resonator. The other ends of the chip U4 “37” and “38” terminals are connected to one end of the capacitor C50 and one end of the resistor R49. The other end of the capacitor C50 is grounded. The other end of the resistor R49 is connected to an external DC power supply. The other ends of the chip U4 “30” and “31” terminals are connected to one end of the capacitor C71 and one end of the magnetic bead FB9. The other end of the magnetic bead FB9 and one end of the capacitor C72 are connected to an external DC power supply. The other ends of the capacitor C71 and the other ends of the capacitor C72 are grounded. The other ends of the chip U4 “29” and “32” terminals are grounded. The other ends of the chip U4 “93-102” terminals are respectively connected to the input terminals of the direct connection port circuit.

[0014] Among them, magnetic beads FB3 and FB9 can be used to suppress high-frequency noise and spike interference from power signals, and can also absorb electrostatic pulses, making the power signal received by chip U4 more stable.

[0015] Furthermore, the crystal resonator includes a resistor R47, a chip Y1, a capacitor C48, and a capacitor C49. The terminal of the chip U4 "41" is connected to one end of the resistor R47, the terminal of the chip Y1 "3", and one end of the capacitor C48. The terminal of the chip U4 "40" is connected to the other end of the resistor R47, the terminal of the chip Y1 "1", and one end of the capacitor C49. The terminals of the chip Y1 "2", the terminal of the chip Y1 "4", the other end of the capacitor C48, and the other end of the capacitor C49 are all grounded.

[0016] The crystal resonator can generate a precise oscillation frequency, providing a stable clock signal for chip U4 and ensuring system timing synchronization.

[0017] Further, the direct connection interface circuit includes interface J2, resistors R52, R53, R54, R55, R56, R58, R59, R74, R75, R76, R77, R78, and capacitor C61. Terminals "8" and "9", "11" and "12", "14" and "15", "17" and "18", and "20" and "21" of interface J2 are respectively connected to the output terminal of the video processing circuit. Terminal "5" of interface J2 is connected to one end of capacitor C61 and one end of resistor R59. The other end of capacitor C61 is grounded, and the other end of resistor R59 is connected to an external DC power supply. The J2 "6" terminal is connected to an external DC power supply via resistor R52. The J2 "26" terminal is connected to resistors R53 and R74. The J2 "27" terminal is connected to resistors R54 and R75. The J2 "28" terminal is connected to resistors R56 and R76. The J2 "33" terminal is connected to resistors R55 and R77. The J2 "34" terminal is connected to resistors R58 and R78. The other ends of resistors R53, R54, R55, R56, and R58 are all connected to an external DC power supply. Resistors R74, R75, R76, R77, and R78 are all grounded.

[0018] Furthermore, the direct connection interface circuit also includes resistors R50, R51, R65, R67, and R69. The J2 "31" terminal is connected to the negative terminal of the MIPI screen circuit's lighting control via resistor R50. The J2 "32" terminal is connected to the negative terminal of the MIPI screen circuit's lighting control via resistor R51. The J2 "36" and "37" terminals are connected to the DC power supply via resistor R65. The J2 "39" terminal is connected to the positive terminal of the MIPI screen circuit's lighting control via resistor R67. The J2 "40" terminal is connected to the positive terminal of the MIPI screen circuit's lighting control via resistor R69.

[0019] Furthermore, the J2 "35" terminal of the interface is connected to the low control terminal of the RGB TTL screen circuit, and the J2 "38" terminal of the interface is connected to the high control terminal of the RGB TTL screen circuit.

[0020] Among them, interface J2 is selected as the FH12A-40S-0.5SH model interface, which can be used for subsequent electrical connection between flexible flat cable (FFC) and flexible printed circuit board (FPC), and can be used for high frequency signal transmission, high density PCB layout and routing, etc.

[0021] Furthermore, the disconnectable interface circuit includes a MIPI screen disconnect interface circuit and a TTL screen disconnect interface circuit. The input terminal of the MIPI screen disconnect interface circuit is connected to the output terminal of the video processing circuit, the input terminal of the TTL screen disconnect interface circuit is connected to the output terminal of the video processing circuit, the output terminal of the MIPI screen disconnect interface circuit is connected to the input terminal of the video format conversion circuit, and the output terminal of the TTL screen disconnect interface circuit is connected to the input terminal of the video format conversion circuit.

[0022] The MIPI screen disconnection interface circuit is not working, while the TTL screen disconnection interface circuit is working.

[0023] Alternatively, the MIPI screen disconnection interface circuit may be operational while the TTL screen disconnection interface circuit may be inoperable.

[0024] Alternatively, the MIPI screen disconnection interface circuit is operational, and the TTL screen disconnection interface circuit is operational.

[0025] Furthermore, the TTL screen disconnection interface circuit includes resistors R190, R191, R192, R193, R194, R195, R196, R197, R198, and R199. One end of resistor R190, one end of resistor R191, one end of resistor R192, one end of resistor R193, one end of resistor R194, one end of resistor R195, one end of resistor R196, and one end of resistor R199... One end of resistor R190, one end of resistor R191, one end of resistor R192, one end of resistor R193, one end of resistor R194, one end of resistor R195, one end of resistor R196, one end of resistor R197, one end of resistor R198, and one end of resistor R199 are respectively connected to the input end of the video format conversion circuit.

[0026] Furthermore, the MIPI screen disconnection interface circuit includes resistors 217, 218, 219, 220, 221, 222, 223, 224, 225, and 226. One end of each of the following resistors is connected to the output terminal of the video processing circuit: one end of each of the following resistors is connected to the input terminal of the video format conversion circuit: one end of each of the following resistors is connected to the input terminal of the video format conversion circuit: one end of each of the following resistors is connected to the input terminal of the video format conversion circuit: one end of each of the following resistors is connected to the input terminal of the video format conversion circuit: one end of each of the following resistors is connected to the output terminal of the video processing ...

[0027] Furthermore, the video format conversion circuit includes an RGB TTL conversion circuit and a MIPI conversion circuit. The input terminal of the RGB TTL conversion circuit is connected to the output terminal of the video interface circuit, the input terminal of the MIPI conversion circuit is connected to the output terminal of the video interface circuit, the output terminal of the RGB TTL conversion circuit is connected to the input terminal of the RGB TTL screen circuit, and the output terminal of the MIPI conversion circuit is connected to the input terminal of the MIPI screen circuit.

[0028] Furthermore, the RGB TTL conversion circuit includes a chip U15, a resistor R236, and an RGB parallel capacitor. The "25" terminal of the chip U15 is connected to one end of the resistor R236, and the other end of the resistor R236 is connected to an external DC power supply. The "56" terminal of the chip U15 is connected to one end of the RGB parallel capacitor and the external DC power supply, and the other end of the RGB parallel capacitor is grounded.

[0029] Furthermore, the RGB parallel capacitors include capacitors C202, C199, C200, C201, and C203, which are connected in parallel.

[0030] Parallel capacitors can increase the total capacitance, reduce the equivalent resistance, and improve current carrying capacity. They can also filter out high and low frequency noise, optimize signal quality, absorb voltage fluctuations, reduce ripple interference, and stabilize the output voltage.

[0031] Furthermore, the MIPI conversion circuit includes a chip U10, a resistor R165, and a resistor R166. The "20" terminal of the chip U10 is connected to the data control terminal of the MCU control circuit through the resistor R165, and the "21" terminal of the chip U10 is connected to the clock control terminal of the MCU control circuit through the resistor R166.

[0032] Furthermore, the MIPI screen circuit includes a MIPI screen interface circuit, which includes an interface J8 and a capacitor C183. Terminals "14" and "15" of the interface J8 are connected to one end of the capacitor C183, and the other end of the capacitor C183 is grounded. Terminals "1" and "2" of the interface J8 serve as the positive terminal for the lighting control of the MIPI screen circuit, and terminals "4", "5", "6", and "7" of the interface J8 serve as the negative terminal for the lighting control of the MIPI screen circuit. That is, terminals "1" and "2" of the interface J8 are connected to the positive terminal for the lighting control of the direct connection interface circuit, and terminals "4", "5", "6", and "7" of the interface J8 are connected to the negative terminal for the lighting control of the direct connection interface circuit.

[0033] Among them, interface J8 is selected from the FPC 45 model interface, which realizes parallel transmission of multiple signals and can perform high-frequency or high-speed data interaction and other operations.

[0034] Furthermore, the RGB TTL screen circuit includes an RGB TTL screen interface circuit, which includes an interface J9. The interface J9 "41" terminal is connected to the high control terminal of the direct connection port circuit, and the interface J9 "42" terminal is connected to the low control terminal of the direct connection port circuit.

[0035] Among them, interface J9 is selected from the FPC50-0.5-CX model interface, which can perform high-density signal transmission and circuit connection, and has high-density integration adaptability.

[0036] Furthermore, the LVDS screen circuit includes a screen based on the LVDS protocol.

[0037] Furthermore, the RGB TTL screen circuit also includes a screen with the RGB TTL protocol.

[0038] Furthermore, the MIPI screen circuit also includes a screen based on the MIPI protocol.

[0039] Beneficial effects

[0040] This utility model provides a circuit scheme that is compatible with multiple protocol display interfaces. By employing an interface signal input circuit, a video processing circuit, a video interface circuit, a video format conversion circuit, an RGB TTL screen circuit, a MIPI screen circuit, and an LVDS screen circuit, it is possible to achieve the goal of a single circuit board being compatible with three protocols (TTL protocol, LVDS protocol, and MIPI protocol) for screen display, thereby reducing hardware iteration development and production costs.

[0041] Among them, the circuit scheme that is compatible with multiple protocol display interfaces, compared with complex circuit switches or high-speed signal distribution chips, solves the problems of signal integrity and signal reflection by selecting the lowest cost physical resistors and making reasonable arrangements. It can independently drive screens with three protocols, namely RGB TTL, LVDS and MIPI, without failure, thereby achieving the goal of multi-protocol compatibility and reducing hardware iteration development and production costs. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure of a multi-protocol display interface compatible circuit according to the present invention.

[0043] Figure 2 This is a schematic diagram of the video processing circuit of a multi-protocol display interface compatible circuit according to this utility model.

[0044] Figure 3 This is a schematic diagram of the direct connection port circuit of a multi-protocol display interface compatible circuit according to this utility model.

[0045] Figure 4 This is a schematic diagram of the disconnectable connection port circuit of a multi-protocol display interface compatible circuit according to this utility model.

[0046] Figure 5 This is a schematic diagram of the RGB TTL conversion circuit of a multi-protocol display interface compatible circuit according to this utility model.

[0047] Figure 6 This is a schematic diagram of the MIPI conversion circuit of a multi-protocol display interface compatible circuit according to this utility model.

[0048] Figure 7 This is a schematic diagram of the MCU control circuit of a multi-protocol display interface compatible circuit according to this utility model.

[0049] Figure 8 This is a schematic diagram of the MIPI screen interface circuit of a multi-protocol display interface compatible circuit according to this utility model.

[0050] Figure 9 This is a schematic diagram of the RGB TTL screen interface circuit of a multi-protocol display interface compatible circuit according to this utility model.

[0051] Figure descriptions: 01. Interface signal input circuit; 02. Video interface circuit; 03. RGB TTL screen circuit; 04. Video format conversion circuit; 05. LVDS screen circuit; 06. Video processing circuit; 07. MIPI screen circuit. Detailed Implementation

[0052] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0053] See Figure 1As shown, this utility model provides a multi-protocol display interface compatible circuit, which includes: an interface signal input circuit 01, a video processing circuit 06, a video interface circuit 02, a video format conversion circuit 04, an RGB TTL screen circuit 03, a MIPI screen circuit 07, and an LVDS screen circuit 05. The input terminal of the interface signal input circuit 01 is connected to the video signal output terminal of an external computer, the output terminal of the interface signal input circuit 01 is connected to the input terminal of the video processing circuit 06, the output terminal of the video processing circuit 06 is connected to the input terminal of the video interface circuit 02, the output terminal of the video interface circuit 02 is connected to the input terminal of the LVDS screen circuit 05 and the input terminal of the video format conversion circuit 04, and the output terminal of the video format conversion circuit 04 is connected to the input terminal of the RGB TTL screen circuit 03 and the input terminal of the MIPI screen circuit 07.

[0054] The video interface circuit 02 includes a direct connection port circuit and a disconnectable connection port circuit. The input terminals of the direct connection port circuit and the disconnectable connection port circuit are respectively connected to the output terminals of the video processing circuit 06. The output terminal of the direct connection port circuit is connected to the input terminal of the LVDS screen circuit 05, and the output terminal of the disconnectable connection port circuit is connected to the input terminal of the video format conversion circuit 04.

[0055] The disconnectable interface circuit includes a MIPI screen disconnect interface circuit and a TTL screen disconnect interface circuit. The input terminal of the MIPI screen disconnect interface circuit is connected to the output terminal of the video processing circuit 06, the input terminal of the TTL screen disconnect interface circuit is connected to the output terminal of the video processing circuit 06, the output terminal of the MIPI screen disconnect interface circuit is connected to the input terminal of the video format conversion circuit 04, and the output terminal of the TTL screen disconnect interface circuit is connected to the input terminal of the video format conversion circuit 04.

[0056] Among them, the MIPI screen disconnection interface circuit is not working, while the TTL screen disconnection interface circuit is working.

[0057] Alternatively, the MIPI screen disconnection interface circuit is working, while the TTL screen disconnection interface circuit is not.

[0058] Alternatively, the MIPI screen disconnection interface circuit is working, and the TTL screen disconnection interface circuit is also working.

[0059] The video format conversion circuit 04 includes an RGB TTL conversion circuit and a MIPI conversion circuit. The input of the RGB TTL conversion circuit is connected to the output of the video interface circuit 02, the input of the MIPI conversion circuit is connected to the output of the video interface circuit 02, the output of the RGB TTL conversion circuit is connected to the input of the RGB TTL screen circuit 03, and the output of the MIPI conversion circuit is connected to the input of the MIPI screen circuit 07.

[0060] Among them, the interface signal input circuit 01 is selected as either a USB interface circuit or a Type-C interface circuit, with a preferred Type-C interface circuit, which means that the computer video signal is transmitted to the video processing circuit through the Type-C interface.

[0061] Among them, see Figure 2 As shown, the video processing circuit 06 includes chip U4, magnetic bead FB3, capacitors C34 and C35, resistors R31, R42, R43, C45, R49, and C50, a crystal resonator, magnetic bead FB9, capacitors C71 and C72. Terminal "91" of chip U4 is connected to one end of magnetic bead FB3 and one end of capacitor C35. The other end of magnetic bead FB3 and one end of capacitor C34 are connected to an external DC power supply. The other ends of capacitors C35 and C34 are grounded together with terminal "92" of chip U4. Terminal "90" of chip U4 is connected to one end of resistor R31, and the other end of resistor R31 is grounded. Terminal "64" of chip U4 is connected to one end of resistor R42, and the other end of resistor R42 is connected to the input terminal of interface signal input circuit 01. Terminal "60" of chip U4 is connected to resistor R43. One end of the resistor R43 is grounded. Terminal 49 of chip U4 is connected to one end of capacitor C45, and the other end of capacitor C45 is grounded. Terminal 41 of chip U4 is connected to one end of the crystal resonator. Terminal 40 of chip U4 is connected to the other end of the crystal resonator. Terminals 37 and 38 of chip U4 are connected to one end of capacitor C50 and one end of resistor R49. The other end of capacitor C50 is grounded. The other end of resistor R49 is connected to an external DC power supply. Terminals 30 and 31 of chip U4 are connected to one end of capacitor C71 and one end of magnetic bead FB9. The other end of magnetic bead FB9 and one end of capacitor C72 are connected to an external DC power supply. The other ends of capacitor C71 and C72 are grounded. Terminals 29 and 32 of chip U4 are grounded. Terminals 93-102 of chip U4 are connected to the input terminals of the direct connection port circuit respectively.

[0062] The crystal resonator includes a resistor R47, a chip Y1, a capacitor C48, and a capacitor C49. Terminal 41 of chip U4 is connected to one end of resistor R47, terminal 3 of chip Y1, and one end of capacitor C48. Terminal 40 of chip U4 is connected to the other end of resistor R47, terminal 1 of chip Y1, and one end of capacitor C49. Terminals 2 and 4 of chip Y1, the other end of capacitor C48, and the other end of capacitor C49 are all grounded. Chip U4 is a DL-4120 model chip, which can process the video signal transmitted from the computer and output it as an LDVS signal to the video interface circuit.

[0063] Specifically, terminals "62", "61", "56", "54", "52", and "51" of chip U4 are all connected to the output of the Type-C interface circuit. This Type-C interface circuit transfers the video data signal output from the computer to the USB interface terminal of chip U4 in the video processing circuit, and then to chip U4 in the video processing circuit for processing. Chip U4 is selected as the DL-4120 model chip, which can amplify the incoming video signal through the USB interface to achieve subsequent low-power display.

[0064] Among them, see Figure 3 As shown, the direct connection interface circuit includes interface J2, resistors R52, R53, R54, R55, R56, R58, R59, R74, R75, R76, R77, R78, and capacitor C61. Terminals "8" and "9", "11" and "12", "14" and "15", "17" and "18", and "20" and "21" of interface J2 are respectively connected to the video processing... At the output of circuit 06, terminal J2 "5" connects to one end of capacitor C61 and one end of resistor R59, with the other end of capacitor C61 grounded. The other end of resistor R59 is connected to an external DC power supply. Terminal J2 "6" connects to an external DC power supply via resistor R52. Terminal J2 "26" connects to resistors R53 and R74. Terminal J2 "27" connects to resistors R54 and R75. Terminal J2 "28" connects to resistors R56 and R76. Terminal J2 "33" connects to... Resistors R55 and R77 are connected to resistors R58 and R78 via terminal J2 "34". The other ends of resistors R53, R54, R55, R56, and R58 are connected to an external DC power supply. Resistors R74, R75, R76, R77, and R78 are grounded. This direct connection circuit also includes resistors R50, R51, R65, R67, and R69. Terminal J2 "31" connects to... Resistor R50 is connected to the negative terminal of the MIPI screen circuit 07 for lighting control. Terminal J2 "32" is connected to the negative terminal of the MIPI screen circuit 07 for lighting control via resistor R51. Terminals J2 "36" and "37" are connected to the DC power supply via resistor R65. Terminal J2 "39" is connected to the positive terminal of the MIPI screen circuit 07 for lighting control via resistor R67. Terminal J2 "40" is connected to the positive terminal of the MIPI screen circuit 07 for lighting control via resistor R69. Terminal J2 "35" is connected to the low control terminal of the RGB TTL screen circuit, and terminal J2 "38" is connected to the high control terminal of the RGB TTL screen circuit.

[0065] Among them, the "2" and "3" terminals of interface J2 are connected to the same power supply (3.3V).

[0066] Among them, see Figure 4 As shown, the TTL screen disconnection interface circuit includes resistors R190, R191, R192, R193, R194, R195, R196, R197, R198, and R199. One end of resistors R190, R191, R192, R193, R194, R195, and R196 are also present. One end of resistor R198 and one end of resistor R199 are connected to the output terminal of video processing circuit 06, respectively. The other ends of resistors R190, R191, R192, R193, R194, R195, R196, R197, R198, and R199 are connected to the input terminal of video format conversion circuit 04, respectively.

[0067] The MIPI screen disconnection interface circuit includes resistors 217, 218, 219, 220, 221, 222, 223, 224, 225, and 226. One end of resistors 217, 218, 219, 220, 221, 222, 223, 224, 225, and 226 are respectively connected to the output terminal of the video processing circuit 06. The other ends of resistors 217, 218, 219, 220, 221, 222, 223, 224, 225, and 226 are respectively connected to the input terminal of the video format conversion circuit 04.

[0068] Among them, see Figure 5 As shown, the RGB TTL conversion circuit includes chip U15, resistor R236, and RGB parallel capacitors. Terminal "25" of chip U15 is connected to one end of resistor R236, and the other end of resistor R236 is connected to an external DC power supply. Terminal "56" of chip U15 is connected to one end of the RGB parallel capacitor and the external DC power supply, and the other end of the RGB parallel capacitor is grounded. The RGB parallel capacitors include capacitors C202, C199, C200, C201, and C203, which are connected in parallel. The chip U15 is a GM8284DD model chip, which can realize the conversion of LVDS to TTL signals.

[0069] Among them, see Figure 6 As shown, the MIPI conversion circuit includes chip U10, resistor R165, and resistor R166. Terminal "20" of chip U10 is connected to the data control terminal of the MCU control circuit through resistor R165, and terminal "21" of chip U10 is connected to the clock control terminal of the MCU control circuit through resistor R166. The chip U10 is selected as the GM8829C model, which supports the conversion of single / dual channel LVDS input to 1-4 channel MIPI output.

[0070] Among them, see Figure 8 As shown, the MIPI screen circuit 07 includes a MIPI screen interface circuit, which includes an interface J8 and a capacitor C183. Terminals "14" and "15" of the interface J8 are connected to one end of the capacitor C183, and the other end of the capacitor C183 is grounded. Terminals "1" and "2" of the interface J8 serve as the positive terminal for the lighting control of the MIPI screen circuit 07, and terminals "4", "5", "6", and "7" of the interface J8 serve as the negative terminal for the lighting control of the MIPI screen circuit 07. That is, terminals "1" and "2" of the interface J8 are connected to the positive terminal for the lighting control of the direct connection interface circuit, and terminals "4", "5", "6", and "7" of the interface J8 are connected to the negative terminal for the lighting control of the direct connection interface circuit.

[0071] Among them, see Figure 9 As shown, the RGB TTL screen circuit 03 includes an RGB TTL screen interface circuit, which includes an interface J9. The interface J9 "41" terminal is connected to the high control terminal of the direct connection port circuit, and the interface J9 "42" terminal is connected to the low control terminal of the direct connection port circuit.

[0072] Among them, the LVDS screen circuit 05 includes a screen with the LVDS protocol; the RGB TTL screen circuit 03 also includes a screen with the RGB TTL protocol; and the MIPI screen circuit 07 also includes a screen with the MIPI protocol.

[0073] Among them, see Figure 7 As shown, the MCU control circuit includes chip U9, which is an STM32F103C8 chip.

[0074] The specific implementation of this utility model: After the computer video signal is input through the Type-C interface, it is processed by the DL-4120 video processing module and then sent out as an LVDS signal. This signal can then drive an LVDS protocol screen via the J2 interface connector. At this time, neither the TTL nor MIPI selection resistors are attached.

[0075] In this solution, the video input signal, after being processed by the video processing module, outputs an LVDS protocol signal, which can drive an LVDS screen. LVDS is a low-voltage, high-speed differential signal, requiring high signal integrity and minimal reflection loss. To ensure compatibility with RGB TTL and MIPI screens, hardware channel switching is implemented at the LVDS signal interface. On the top layer of the front side of the circuit board, ten 0Ω selection resistors switch to the MIPI video format conversion module. The second layer of the circuit board is fully grounded to ensure impedance control and interference shielding. On the bottom layer of the back side of the circuit board, in the same location, the LVDS signal, after passing through a via, switches to the RGB TTL video format conversion module via ten 0Ω selection resistors. The penultimate layer of the circuit board is fully grounded to ensure impedance control and interference shielding. This physical method of selecting the signal using resistors on both sides minimizes signal reflection loss and interference, while ensuring that connecting to any type of screen—RGB TTL, MIPI, or LVDS—is unaffected.

[0076] Specifically, the LVDS signal sent by the main video processing module is connected to the GM8829C video format conversion processing module at the back end through resistors R190~R199 on the top layer of the circuit board. The LVDS protocol signal is converted into a MIPI protocol signal, which can drive the MIPI protocol screen through the J8 interface socket.

[0077] Specifically, the LVDS signal sent by the main video processing module is connected to the GM8284DD video format conversion processing module at the back end after passing through vias and resistors at the bottom of the circuit board via resistors R217~R226 on the bottom of the circuit board. The LVDS protocol signal is converted into an RGB TTL protocol signal, which can drive an RGB TTL protocol screen through the J9 interface socket.

[0078] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A multi-protocol display interface compatible circuit, characterized in that, The multi-protocol display interface compatible circuit includes: an interface signal input circuit, a video processing circuit, a video interface circuit, a video format conversion circuit, an RGB TTL screen circuit, a MIPI screen circuit, and an LVDS screen circuit. The input terminal of the interface signal input circuit is connected to the video signal output terminal of an external computer. The output terminal of the interface signal input circuit is connected to the input terminal of the video processing circuit. The output terminal of the video processing circuit is connected to the input terminal of the video interface circuit. The output terminal of the video interface circuit is connected to the input terminal of the LVDS screen circuit and the input terminal of the video format conversion circuit. The output terminal of the video format conversion circuit is connected to the input terminal of the RGB TTL screen circuit and the input terminal of the MIPI screen circuit. The video interface circuit includes a direct connection port circuit and a disconnectable connection port circuit. The input terminals of the direct connection port circuit and the disconnectable connection port circuit are respectively connected to the output terminals of the video processing circuit. The output terminal of the direct connection port circuit is connected to the input terminal of the LVDS screen circuit, and the output terminal of the disconnectable connection port circuit is connected to the input terminal of the video format conversion circuit.

2. The multi-protocol display interface compatible circuit according to claim 1, characterized in that, The interface signal input circuit is selected from either a USB interface circuit or a Type-C interface circuit.

3. The multi-protocol display interface compatible circuit according to claim 1, characterized in that, The video processing circuit includes chip U4, magnetic bead FB3, capacitors C34 and C35, resistors R31, R42, R43, C45, R49, and C50, a crystal resonator, magnetic bead FB9, capacitors C71 and C72. Terminal "91" of chip U4 is connected to one end of magnetic bead FB3 and one end of capacitor C35. The other end of magnetic bead FB3 and one end of capacitor C34 are connected to an external DC power supply. The other ends of capacitors C35 and C34 are grounded together with terminal "92" of chip U4. Terminal "90" of chip U4 is connected to one end of resistor R31, and the other end of resistor R31 is grounded. Terminal "64" of chip U4 is connected to one end of resistor R42, and the other end of resistor R42 is connected to the input terminal of the interface signal input circuit. Terminal "60" of chip U4 is connected to one end of resistor R43. The other end of resistor R43 is grounded. Terminal U4"49 of chip U4 is connected to one end of capacitor C45, and the other end of capacitor C45 is grounded. Terminal U4"41 of chip U4 is connected to one end of crystal resonator. Terminal U4"40 of chip U4 is connected to the other end of crystal resonator. Terminals "37" and "38" of chip U4 are connected to one end of capacitor C50 and one end of resistor R49. The other end of capacitor C50 is grounded. The other end of resistor R49 is connected to an external DC power supply. Terminals "30" and "31" of chip U4 are connected to one end of capacitor C71 and one end of magnetic bead FB9. The other end of magnetic bead FB9 and one end of capacitor C72 are connected to an external DC power supply. The other ends of capacitor C71 and C72 are grounded. Terminals "29" and "32" of chip U4 are grounded. Terminals "93-102" of chip U4 are respectively connected to the input terminals of the direct connection port circuit.

4. The multi-protocol display interface compatible circuit according to claim 1, characterized in that, The direct connection interface circuit includes interface J2, resistors R52, R53, R54, R55, R56, R58, R59, R74, R75, R76, R77, R78, and capacitor C61. Terminals "8" and "9", "11" and "12", "14" and "15", "17" and "18", and "20" and "21" of interface J2 are respectively connected to the output of the video processing circuit. Terminal "5" of interface J2 is connected to one end of capacitor C61 and one end of resistor R59. The other end of capacitor C61 is grounded, and the other end of resistor R59 is connected to an external DC power supply. Terminal J2"6" is connected to an external DC power supply via resistor R52. Terminal J2"26" is connected to resistors R53 and R74. Terminal J2"27" is connected to resistors R54 and R75. Terminal J2"28" is connected to resistors R56 and R76. Terminal J2"33" is connected to resistors R55 and R77. Terminal J2"34" is connected to resistors R58 and R78. The other ends of resistors R53, R54, R55, R56, and R58 are all connected to an external DC power supply. Resistors R74, R75, R76, R77, and R78 are all grounded.

5. A multi-protocol display interface compatible circuit according to claim 1, characterized in that, The disconnectable interface circuit includes a MIPI screen disconnect interface circuit and a TTL screen disconnect interface circuit. The input terminal of the MIPI screen disconnect interface circuit is connected to the output terminal of the video processing circuit, the input terminal of the TTL screen disconnect interface circuit is connected to the output terminal of the video processing circuit, the output terminal of the MIPI screen disconnect interface circuit is connected to the input terminal of the video format conversion circuit, and the output terminal of the TTL screen disconnect interface circuit is connected to the input terminal of the video format conversion circuit. The MIPI screen disconnection interface circuit is not working, while the TTL screen disconnection interface circuit is working. Alternatively, the MIPI screen disconnection interface circuit may be operational while the TTL screen disconnection interface circuit may be inoperable. Alternatively, the MIPI screen disconnection interface circuit is operational, and the TTL screen disconnection interface circuit is operational.

6. The multi-protocol display interface compatible circuit according to claim 5, characterized in that, The TTL screen disconnection interface circuit includes resistors R190, R191, R192, R193, R194, R195, R196, R197, R198, and R199. One end of resistor R190, one end of resistor R191, one end of resistor R192, one end of resistor R193, one end of resistor R194, one end of resistor R195, one end of resistor R196, and one end of resistor R197... One end of resistor R190, one end of resistor R191, and one end of resistor R192 are respectively connected to the output terminal of the video processing circuit. The other ends of resistors R193, R194, R195, R196, R197, R198, and R199 are respectively connected to the input terminal of the video format conversion circuit.

7. A multi-protocol display interface compatible circuit according to claim 6, characterized in that, The MIPI screen disconnect interface circuit includes resistors 217, 218, 219, 220, 221, 222, 223, 224, 225, and 226. One end of each of the following resistors is connected to the output of the video processing circuit: 217, 218, 219, 220, 221, 222, 223, 224, 225, and 226. The other ends of each of the following resistors are connected to the input of the video format conversion circuit: 217, 218, 219, 220, 221, 222, 223, 224, 225, and 226.

8. A multi-protocol display interface compatible circuit according to claim 1, characterized in that, The video format conversion circuit includes an RGB TTL conversion circuit and a MIPI conversion circuit. The input terminal of the RGB TTL conversion circuit is connected to the output terminal of the video interface circuit, the input terminal of the MIPI conversion circuit is connected to the output terminal of the video interface circuit, the output terminal of the RGB TTL conversion circuit is connected to the input terminal of the RGB TTL screen circuit, and the output terminal of the MIPI conversion circuit is connected to the input terminal of the MIPI screen circuit.

9. A multi-protocol display interface compatible circuit according to claim 8, characterized in that, The RGB TTL conversion circuit includes a chip U15, a resistor R236, and an RGB parallel capacitor. The "25" terminal of the chip U15 is connected to one end of the resistor R236, and the other end of the resistor R236 is connected to an external DC power supply. The "56" terminal of the chip U15 is connected to one end of the RGB parallel capacitor and the external DC power supply, and the other end of the RGB parallel capacitor is grounded.

10. A multi-protocol display interface compatible circuit according to claim 8, characterized in that, The MIPI conversion circuit includes chip U10, resistor R165 and resistor R166. The "20" terminal of chip U10 is connected to the data control terminal of the MCU control circuit through resistor R165, and the "21" terminal of chip U10 is connected to the clock control terminal of the MCU control circuit through resistor R166.

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