Power circuit board and motor controller

Abstract

The application discloses a power circuit board and a motor controller. The power circuit board comprises a first circuit board body, an upper bridge arm power tube and a lower bridge arm power tube, and a gate interlocking circuit. The gate interlocking circuit comprises a first acquisition unit, a second acquisition unit, a logic processing unit and a grounding unit. The first acquisition unit is used for acquiring a first gate potential signal of the upper bridge arm power tube. The second acquisition unit is used for acquiring a second gate potential signal of the lower bridge arm power tube. The logic processing unit is configured to generate a trigger signal when the first gate potential signal and the second gate potential signal are both on. The grounding unit is configured to control the gate of the upper bridge arm power tube to be on with the ground and control the gate of the lower bridge arm power tube to be on with the ground based on the trigger signal. According to the power circuit board, the upper bridge arm power tube and the lower bridge arm power tube are prevented from being on for a long time without relying on a driving signal, and the bridge arm shoot-through problem is solved.

Description

Technical Field

[0001] This application relates to the field of switching device driving, and in particular to a power circuit board and motor controller. Background Technology

[0002] The motor controller includes a power circuit board and a drive circuit board that can be interconnected. The switching devices to be driven, namely the upper bridge arm power transistor and the lower bridge arm power transistor, are located on the power circuit board, while the drive chip used to drive the upper bridge arm power transistor and the lower bridge arm power transistor is located on the drive circuit board.

[0003] In related technologies, the power circuit board and the drive circuit board are connected to each other through docking terminals. When there is a large vibration at the docking terminals, the docking terminals are prone to disconnection. At this time, the power transistors on the power circuit board cannot be turned off in time because they do not receive the drive signal. The upper and lower bridge arm power transistors will be conducting for a long time, resulting in bridge arm shoot-through. Utility Model Content

[0004] This application provides a power circuit board and a motor controller that can prevent the upper and lower bridge arm power transistors from being turned on for extended periods without relying on drive signals, thereby solving the bridge arm shoot-through problem.

[0005] In a first aspect, embodiments of this application provide a power circuit board, comprising: a first circuit board body; an upper bridge power transistor and a lower bridge power transistor disposed on the first circuit board body; and a gate interlock circuit disposed on the first circuit board body. The gate interlock circuit includes a first acquisition unit, a second acquisition unit, a logic processing unit, and a grounding unit. The first acquisition unit is connected to the gate of the upper bridge power transistor to acquire a first gate potential signal of the upper bridge power transistor. The second acquisition unit is connected to the gate of the lower bridge power transistor to acquire a second gate potential signal of the lower bridge power transistor. The logic processing unit is connected to the first acquisition unit and the second acquisition unit respectively. The output terminal of the logic processing unit is connected to the grounding unit. The grounding unit is connected to the gate of the upper bridge power transistor and the gate of the lower bridge power transistor. The logic processing unit is configured to generate a trigger signal when the first gate potential signal and the second gate potential signal are both on-potential. The grounding unit is configured to control the gate of the upper bridge power transistor to be connected to ground and the gate of the lower bridge power transistor to be connected to ground based on the trigger signal.

[0006] According to the foregoing embodiments of the first aspect of this application, the logic processing unit includes an AND gate circuit, the two input terminals of the AND gate circuit are respectively connected to the first acquisition unit and the second acquisition unit, and the output terminal of the AND gate circuit is connected to the grounding unit.

[0007] According to any of the foregoing embodiments of the first aspect of this application, the first acquisition unit includes a first isolation chip, the high-voltage side input terminal of the first isolation chip is electrically connected to the gate of the upper bridge arm power transistor, and the low-voltage side output terminal of the first isolation chip is electrically connected to one input terminal of the AND gate circuit; the second acquisition unit includes a second isolation chip, the high-voltage side input terminal of the second isolation chip is electrically connected to the gate of the lower bridge arm power transistor, and the low-voltage side output terminal of the second isolation chip is electrically connected to the other input terminal of the AND gate circuit.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the first acquisition unit further includes a first resistor, which is electrically connected between the high-voltage side input terminal of the first isolation chip and the gate of the upper bridge arm power transistor; the second acquisition unit further includes a second resistor, which is electrically connected between the high-voltage side input terminal of the second isolation chip and the gate of the lower bridge arm power transistor.

[0009] According to any of the foregoing embodiments of the first aspect of this application, the grounding unit includes: a first grounding subunit, electrically connected to the output terminal of the AND gate circuit and the gate of the upper bridge arm power transistor, respectively, the first grounding subunit being configured to control the gate of the upper bridge arm power transistor to be connected to ground based on the trigger signal output by the AND gate circuit; and a second grounding subunit, electrically connected to the output terminal of the AND gate circuit and the gate of the lower bridge arm power transistor, respectively, the second grounding subunit being configured to control the gate of the lower bridge arm power transistor to be connected to ground based on the trigger signal output by the AND gate circuit.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the first grounding subunit includes a first grounding switch and a first feedback module. One end of the first grounding switch is electrically connected to the gate of the upper bridge arm power transistor, and the other end of the first grounding switch is grounded. The control terminal of the first grounding switch is connected to the first feedback module, and the first feedback module is connected to the output terminal of the AND gate circuit. The first feedback module is configured to control the first grounding switch to conduct when the AND gate circuit outputs the trigger signal. The second grounding subunit includes a second grounding switch and a second feedback module. One end of the second grounding switch is electrically connected to the gate of the lower bridge arm power transistor, and the other end of the second grounding switch is grounded. The control terminal of the second grounding switch is connected to the second feedback module, and the second feedback module is connected to the output terminal of the AND gate circuit. The second feedback module is configured to control the second grounding switch to conduct when the AND gate circuit outputs the trigger signal.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the first feedback module includes a third isolation chip and a first control switch. One end of the first control switch is grounded, and the other end of the first control switch is electrically connected to the low-voltage input terminal of the third isolation chip. The control terminal of the first control switch is connected to the output terminal of the AND gate circuit, and the high-voltage output terminal of the third isolation chip is electrically connected to the control terminal of the first grounding switch. The second feedback module includes a fourth isolation chip and a second control switch. One end of the second control switch is grounded, and the other end of the second control switch is electrically connected to the low-voltage input terminal of the fourth isolation chip. The control terminal of the second control switch is connected to the output terminal of the AND gate circuit, and the high-voltage output terminal of the fourth isolation chip is electrically connected to the control terminal of the second grounding switch.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the first grounding switch and the second grounding switch are PNP transistors, and the first control switch and the second control switch are NPN transistors.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the power circuit board further includes: a first docking terminal disposed on the first circuit board body, the first docking terminal being electrically connected to the gate of the upper bridge arm power transistor and the gate of the lower bridge arm power transistor, and the first docking terminal being used to dock with the drive circuit board.

[0014] Secondly, embodiments of this application provide a motor controller, which includes: a power circuit board according to any of the foregoing embodiments of the first aspect of this application; a drive circuit board, the drive circuit board including a second circuit board body, a first drive chip and a second drive chip, the first drive chip and the second drive chip being disposed on the second circuit board body, the drive circuit board being able to interface with the power circuit board, the first drive chip being used to drive the upper bridge arm power transistor, and the second drive chip being used to drive the lower bridge arm power transistor.

[0015] According to an embodiment of this application, a power circuit board includes a gate interlock circuit disposed on a first circuit board body. The gate interlock circuit includes a first acquisition unit, a second acquisition unit, a logic processing unit, and a grounding unit. The first acquisition unit acquires a first gate potential signal of the upper bridge arm power transistor, and the second acquisition unit acquires a second gate potential signal of the lower bridge arm power transistor. The logic processing unit is configured to generate a trigger signal when both the first and second gate potential signals are simultaneously on-state. The grounding unit is configured to control the gate of the upper bridge arm power transistor to be connected to ground based on the trigger signal, and to control the gate of the lower bridge arm power transistor to be connected to ground. This allows the potentials of the gates of both the upper and lower bridge arm power transistors to be grounded without relying on a drive signal when both are on, thereby turning off the upper and lower bridge arm power transistors and preventing them from being on for extended periods. This solves the bridge arm shoot-through problem without relying on a drive signal. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a structural block diagram of an embodiment of the power circuit board of this application;

[0018] Figure 2 This is a structural block diagram of the upper bridge arm power transistor P1, the lower bridge arm power transistor P2, and the gate interlock circuit in one embodiment of the power circuit board of this application.

[0019] Figure 3 This is a circuit diagram of an embodiment of the power circuit board of this application;

[0020] Figure 4 This is a circuit diagram of an embodiment of the motor controller of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0023] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0024] This application provides a power circuit board. Figure 1 This is a structural block diagram of an embodiment of the power circuit board of this application. The power circuit board 100 includes a first circuit board body 110, an upper bridge power transistor P1 and a lower bridge power transistor P2, and a gate interlock circuit 120.

[0025] The upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 are disposed on the first circuit board body 110. The gate interlock circuit 120 is disposed on the first circuit board body 110.

[0026] Figure 2 This is a structural block diagram of the upper bridge power transistor P1, the lower bridge power transistor P2, and the gate interlock circuit in one embodiment of the power circuit board of this application. The gate interlock circuit 120 includes a first acquisition unit 121, a second acquisition unit 122, a logic processing unit 123, and a grounding unit 124. The first acquisition unit 121 is connected to the gate of the upper bridge power transistor P1 to acquire the first gate potential signal of the upper bridge power transistor P1. The second acquisition unit 122 is connected to the gate of the lower bridge power transistor P2 to acquire the second gate potential signal of the lower bridge power transistor P2. The logic processing unit 123 is connected to the first acquisition unit 121 and the second acquisition unit 122, respectively. The output terminal of the logic processing unit 123 is connected to the grounding unit 124. The grounding unit 124 is connected to the gate of the upper bridge power transistor P1 and the gate of the lower bridge power transistor P2. The logic processing unit 123 is configured to generate a trigger signal when both the first gate potential signal and the second gate potential signal are simultaneously on. Grounding unit 124 is configured to control the gate of the upper bridge arm power transistor P1 to be connected to ground based on a trigger signal, and to control the gate of the lower bridge arm power transistor P2 to be connected to ground. In one example, the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 are both turned on when the level is high.

[0027] According to an embodiment of this application, a power circuit board 100 includes a gate interlock circuit 120 disposed on a first circuit board body 110. The gate interlock circuit 120 includes a first acquisition unit 121, a second acquisition unit 122, a logic processing unit 123, and a grounding unit 124. The first acquisition unit 121 acquires the first gate potential signal of the upper bridge arm power transistor P1, and the second acquisition unit 122 acquires the second gate potential signal of the lower bridge arm power transistor P2. The logic processing unit 123 is capable of generating a trigger signal when both the first gate potential signal and the second gate potential signal are simultaneously on. Based on the trigger signal, the grounding unit 124 controls the gate of the upper bridge arm power transistor P1 to be connected to ground, and controls the gate of the lower bridge arm power transistor P2 to be connected to ground. Thus, when both the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 are turned on, the potential of the gate of the upper bridge arm power transistor P1 and the gate of the lower bridge arm power transistor P2 is grounded without relying on the drive signal, thereby turning off the upper bridge arm power transistor and the lower bridge arm power transistor, avoiding the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 from being turned on for a long time, thus solving the bridge arm shoot-through problem without relying on the drive signal.

[0028] In some embodiments, the power circuit board 100 further includes a first docking terminal 130, which is disposed on the first circuit board body 110. The first docking terminal 130 is electrically connected to the gate of the upper bridge arm power transistor P1 and the gate of the lower bridge arm power transistor P2, and is used to dock with the drive circuit board.

[0029] When there is significant vibration at the first docking terminal 130, the connection between the first docking terminal 130 and the drive circuit board is prone to breakage. In this case, the drive signal from the drive circuit board cannot be transmitted to the power circuit board 100. When a power transistor in one of the bridge arms of the power circuit board 100 should be turned off, it cannot be turned off in time due to the lack of a drive signal, resulting in the gate of the power transistor failing to discharge. In this embodiment, by providing a gate interlock circuit 120 on the power circuit board 100, when both the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 are on, the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 can be turned off without relying on a drive signal, thus preventing the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 from being on for extended periods.

[0030] Figure 3This is a circuit diagram of a power circuit board according to an embodiment of this application. In some embodiments, the logic processing unit 123 includes an AND gate circuit AND1. The two input terminals of the AND gate circuit AND1 are respectively connected to the first acquisition unit 121 and the second acquisition unit 122, and the output terminal of the AND gate circuit AND1 is connected to the ground unit 124. In some embodiments, the trigger signal is a high-level signal output by the AND gate circuit AND1. In this embodiment, the logic processing unit 123 includes the AND gate circuit AND1. Therefore, when and only when the first acquisition unit 121 and the second acquisition unit 122 simultaneously acquire that the gates of the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 are both at a high level, the AND gate circuit AND1 outputs a high-level signal as a trigger signal for controlling the ground unit 124.

[0031] In some embodiments, the first acquisition unit 121 includes a first isolation chip XQ1, the high-voltage side input terminal of the first isolation chip XQ1 is electrically connected to the gate of the upper bridge arm power transistor P1, and the low-voltage side output terminal of the first isolation chip XQ1 is electrically connected to one input terminal of the AND gate circuit AND1.

[0032] In some embodiments, the second acquisition unit 122 includes a second isolation chip XQ2. The high-voltage side input terminal of the second isolation chip XQ2 is electrically connected to the gate of the lower bridge arm power transistor P2, and the low-voltage side output terminal of the second isolation chip XQ2 is electrically connected to another input terminal of the AND gate circuit AND1.

[0033] The first isolation chip XQ and the second isolation chip XQ2 are, for example, optocoupler isolation chips.

[0034] In some embodiments, the first acquisition unit 121 further includes a first resistor R1, which is electrically connected between the high-voltage side input terminal of the first isolation chip XQ1 and the gate of the upper bridge power transistor P1.

[0035] In some embodiments, the second acquisition unit 122 further includes a second resistor R2, which is electrically connected between the high-voltage side input terminal of the second isolation chip XQ2 and the gate of the lower bridge arm power transistor P2.

[0036] By setting the first resistor R1 and the second resistor R2, voltage division can be performed in the circuit when the first acquisition unit 121 and the second acquisition unit 122 acquire voltage, which facilitates the first acquisition unit 121 and the second acquisition unit 122 to acquire accurate potential information.

[0037] In some embodiments, the grounding unit 124 includes a first grounding subunit 1241 and a second grounding subunit 1242. The first grounding subunit 1241 is electrically connected to the output of the AND gate circuit AND1 and the gate of the upper bridge arm power transistor P1, respectively. The first grounding subunit 1241 is configured to control the gate of the upper bridge arm power transistor P1 to be connected to ground based on the trigger signal output by the AND gate circuit AND1. The second grounding subunit 1242 is electrically connected to the output of the AND gate circuit AND1 and the gate of the lower bridge arm power transistor P2, respectively. The second grounding subunit 1242 is configured to control the gate of the lower bridge arm power transistor P2 to be connected to ground based on the trigger signal output by the AND gate circuit AND1.

[0038] In some embodiments, the first grounding subunit 1241 includes a first grounding switch Q1 and a first feedback module F1. One end of the first grounding switch Q1 is electrically connected to the gate of the upper bridge arm power transistor P1, and the other end of the first grounding switch Q1 is grounded. The control terminal of the first grounding switch Q1 is connected to the first feedback module F1. The first feedback module F1 is connected to the output terminal of the AND gate circuit AND1. The first feedback module F1 is configured to control the first grounding switch Q1 to turn on based on the output trigger signal of the AND gate circuit AND1.

[0039] In some embodiments, the second grounding subunit 1242 includes a second grounding switch Q2 and a second feedback module F2. One end of the second grounding switch Q2 is electrically connected to the gate of the lower bridge arm power transistor P2, and the other end of the second grounding switch Q2 is grounded. The control terminal of the second grounding switch Q2 is connected to the second feedback module F2. The second feedback module F2 is connected to the output terminal of the AND gate circuit AND1. The second feedback module F2 is configured to control the second grounding switch Q2 to turn on based on the output trigger signal of the AND gate circuit AND1.

[0040] In some embodiments, the first feedback module F1 includes a third isolation chip XQ3 and a first control switch Q3. One end of the first control switch Q3 is grounded, and the other end of the first control switch Q3 is electrically connected to the low-voltage input terminal of the third isolation chip XQ3. The control terminal of the first control switch Q3 is connected to the output terminal of the AND gate circuit AND1. The high-voltage output terminal of the third isolation chip XQ3 is electrically connected to the control terminal of the first grounding switch Q1.

[0041] In some embodiments, the second feedback module F2 includes a fourth isolation chip XQ4 and a second control switch Q4. One end of the second control switch Q4 is grounded, and the other end of the second control switch Q4 is electrically connected to the low-voltage input terminal of the fourth isolation chip XQ4. The control terminal of the second control switch Q4 is connected to the output terminal of the AND gate circuit AND1. The high-voltage output terminal of the fourth isolation chip XQ4 is electrically connected to the control terminal of the second grounding switch Q2.

[0042] The third isolation chip XQ3 and the fourth isolation chip XQ are, for example, optocoupler isolation chips.

[0043] In some embodiments, the first grounding switch Q1 and the second grounding switch Q2 are PNP transistors, and the first control switch Q3 and the second control switch Q4 are NPN transistors. In one example, the upper bridge power transistor P1 and the lower bridge power transistor P2 are turned on when they are at a high level. When the first acquisition unit 121 and the second acquisition unit 122 simultaneously acquire that the gates of the upper bridge power transistor P1 and the lower bridge power transistor P2 are both at a high level, the AND gate circuit AND1 outputs a high-level signal. At this time, the first control switch Q3 and the second control switch Q4 are turned on, causing the low-voltage input terminal of the third isolation chip XQ3 and the low-voltage input terminal of the fourth isolation chip XQ4 to be pulled down. Correspondingly, the control terminals of the first grounding switch Q1 and the second grounding switch Q2 are also pulled down, causing the first grounding switch Q1 and the second grounding switch Q2 to be turned on. The first grounding switch Q1 grounds the gate of the upper bridge power transistor P1, and the second grounding switch Q2 grounds the gate of the lower bridge power transistor P1.

[0044] This application also provides a motor controller, which includes the power circuit board 100 and the drive circuit board of any of the foregoing embodiments. Figure 4 This is a circuit diagram of an embodiment of the motor controller of this application. The power circuit board 100 includes a first circuit board body 110, an upper bridge power transistor P1 and a lower bridge power transistor P2, and a gate interlock circuit 120. The upper bridge power transistor P1 and the lower bridge power transistor P2 are disposed on the first circuit board body 110. The gate interlock circuit 120 is disposed on the first circuit board body 110. The gate interlock circuit 120 includes a first acquisition unit 121, a second acquisition unit 122, a logic processing unit 123, and a grounding unit 124. The first acquisition unit 121 is connected to the gate of the upper bridge power transistor P1 to acquire the first gate potential signal of the upper bridge power transistor P1. The second acquisition unit 122 is connected to the gate of the lower bridge power transistor P2 to acquire the second gate potential signal of the lower bridge power transistor P2. The logic processing unit 123 is connected to the first acquisition unit 121 and the second acquisition unit 122 respectively. The output terminal of the logic processing unit 123 is connected to the grounding unit 124. Grounding unit 124 is connected to the gate of the upper bridge arm power transistor P1 and the gate of the lower bridge arm power transistor P2. Logic processing unit 123 is configured to generate a trigger signal when both the first gate potential signal and the second gate potential signal are simultaneously on. Grounding unit 124 is configured to control the gate of the upper bridge arm power transistor P1 to be connected to ground based on the trigger signal, and to control the gate of the lower bridge arm power transistor P2 to be connected to ground.

[0045] The driving circuit board 200 includes a second circuit board body 210, a first driving chip 221 and a second driving chip 222. The first driving chip 221 and the second driving chip 222 are disposed on the second circuit board body 210. The driving circuit board 200 can be connected to the power circuit board 100. The first driving chip 221 is used to drive the upper bridge arm power transistor P1, and the second driving chip 222 is used to drive the lower bridge arm power transistor P2.

[0046] In some embodiments, the power circuit board 100 further includes a first docking terminal 130, which is disposed on the first circuit board body 110. The first docking terminal 130 is electrically connected to the gate of the upper bridge arm power transistor P1 and the gate of the lower bridge arm power transistor P2, and is used to dock with the drive circuit board 200.

[0047] In some embodiments, the drive circuit board 200 includes a second mating terminal 230 disposed on the second circuit board body 210. The second mating terminal 230 is electrically connected to the first drive chip 221 and the second drive chip 222, and is used to mate with the power circuit board 100. Specifically, the second mating terminal 230 can mate with and be electrically connected to the first mating terminal 130.

[0048] In related technologies, the power circuit board 100 and the drive circuit board 200 are connected to each other through the first docking terminal 130 and the second docking terminal. When there is a large vibration at the first docking terminal 130 and the second docking terminal, the first docking terminal 130 and the second docking terminal are prone to disconnection. At this time, when the power transistor of a certain bridge arm on the power circuit board 100 should be turned off, it cannot be turned off in time because it does not receive the drive signal. As a result, the gate of the power transistor cannot discharge and only relies on the gate bias resistor to discharge naturally. The discharge speed is slow (in one example, the natural discharge is about 20us, while the short circuit time of the power transistor is generally less than 6us, and the dead time of the upper and lower bridge arms is generally 2.5us). The power transistor will be in the conducting state for a long time. This will cause the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 to be conducting for a long time, which will lead to the bridge arm shoot-through.

[0049] According to an embodiment of this application, the power circuit board 100 of the motor controller includes a gate interlock circuit 120 disposed on a first circuit board body 110. The gate interlock circuit 120 includes a first acquisition unit 121, a second acquisition unit 122, a logic processing unit 123, and a grounding unit 124. The first acquisition unit 121 acquires the first gate potential signal of the upper bridge arm power transistor P1, and the second acquisition unit 122 acquires the second gate potential signal of the lower bridge arm power transistor P2. The logic processing unit 123 can generate a trigger signal when both the first gate potential signal and the second gate potential signal are simultaneously on. Based on the trigger signal, the grounding unit 124 controls the gate of the upper bridge arm power transistor P1 to be connected to ground, and controls the gate of the lower bridge arm power transistor P2 to be connected to ground. Thus, when both the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 are turned on, the potential of the gate of the upper bridge arm power transistor P1 and the gate of the lower bridge arm power transistor P2 is grounded without relying on the drive signal, thereby turning off the upper bridge arm power transistor and the lower bridge arm power transistor, avoiding the upper bridge arm power transistor P1 and the lower bridge arm power transistor P2 from being turned on for a long time, thus solving the bridge arm shoot-through problem without relying on the drive signal.

[0050] This application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0051] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A power circuit board, characterized in that, include: First circuit board body; The upper bridge arm power transistor and the lower bridge arm power transistor are disposed on the first circuit board body; as well as A gate interlock circuit is disposed on the first circuit board body. The gate interlock circuit includes a first acquisition unit, a second acquisition unit, a logic processing unit, and a grounding unit. The first acquisition unit is connected to the gate of the upper bridge arm power transistor to acquire the first gate potential signal of the upper bridge arm power transistor. The second acquisition unit is connected to the gate of the lower bridge arm power transistor to acquire the second gate potential signal of the lower bridge arm power transistor. The logic processing unit is connected to the first acquisition unit and the second acquisition unit respectively. The output terminal of the logic processing unit is connected to the grounding unit. The grounding unit is connected to the gate of the upper bridge arm power transistor and the gate of the lower bridge arm power transistor. The logic processing unit is configured to generate a trigger signal when the first gate potential signal and the second gate potential signal are both on potentials. The grounding unit is configured to control the gate of the upper bridge arm power transistor to be connected to ground and the gate of the lower bridge arm power transistor to be connected to ground based on the trigger signal.

2. The power circuit board as described in claim 1, characterized in that, The logic processing unit includes an AND gate circuit. The two input terminals of the AND gate circuit are respectively connected to the first acquisition unit and the second acquisition unit, and the output terminal of the AND gate circuit is connected to the grounding unit.

3. The power circuit board as described in claim 2, characterized in that, The first acquisition unit includes a first isolation chip. The high-voltage side input terminal of the first isolation chip is electrically connected to the gate of the upper bridge arm power transistor, and the low-voltage side output terminal of the first isolation chip is electrically connected to one input terminal of the AND gate circuit. The second acquisition unit includes a second isolation chip. The high-voltage side input terminal of the second isolation chip is electrically connected to the gate of the lower bridge arm power transistor, and the low-voltage side output terminal of the second isolation chip is electrically connected to the other input terminal of the AND gate circuit.

4. The power circuit board as described in claim 3, characterized in that, The first acquisition unit further includes a first resistor, which is electrically connected between the high-voltage side input terminal of the first isolation chip and the gate of the upper bridge power transistor; The second acquisition unit also includes a second resistor, which is electrically connected between the high-voltage side input terminal of the second isolation chip and the gate of the lower bridge arm power transistor.

5. The power circuit board as described in claim 2, characterized in that, The grounding unit includes: The first grounding sub-unit is electrically connected to the output terminal of the AND gate circuit and the gate of the upper bridge arm power transistor, respectively. The first grounding sub-unit is configured to control the gate of the upper bridge arm power transistor to be connected to ground based on the trigger signal output by the AND gate circuit. The second grounding sub-unit is electrically connected to the output terminal of the AND gate circuit and the gate of the lower bridge arm power transistor, respectively. The second grounding sub-unit is configured to control the gate of the lower bridge arm power transistor to be connected to ground based on the trigger signal output by the AND gate circuit.

6. The power circuit board as described in claim 5, characterized in that, The first grounding subunit includes a first grounding switch and a first feedback module. One end of the first grounding switch is electrically connected to the gate of the upper bridge arm power transistor, and the other end of the first grounding switch is grounded. The control terminal of the first grounding switch is connected to the first feedback module, and the first feedback module is connected to the output terminal of the AND gate circuit. The first feedback module is configured to control the first grounding switch to turn on when the AND gate circuit outputs the trigger signal. The second grounding subunit includes a second grounding switch and a second feedback module. One end of the second grounding switch is electrically connected to the gate of the lower bridge arm power transistor, and the other end of the second grounding switch is grounded. The control terminal of the second grounding switch is connected to the second feedback module, and the second feedback module is connected to the output terminal of the AND gate circuit. The second feedback module is configured to control the second grounding switch to turn on when the AND gate circuit outputs the trigger signal.

7. The power circuit board as described in claim 6, characterized in that, The first feedback module includes a third isolation chip and a first control switch. One end of the first control switch is grounded, and the other end of the first control switch is electrically connected to the low-voltage input terminal of the third isolation chip. The control terminal of the first control switch is connected to the output terminal of the AND gate circuit, and the high-voltage output terminal of the third isolation chip is electrically connected to the control terminal of the first grounding switch. The second feedback module includes a fourth isolation chip and a second control switch. One end of the second control switch is grounded, and the other end of the second control switch is electrically connected to the low-voltage input terminal of the fourth isolation chip. The control terminal of the second control switch is connected to the output terminal of the AND gate circuit, and the high-voltage output terminal of the fourth isolation chip is electrically connected to the control terminal of the second grounding switch.

8. The power circuit board as described in claim 7, characterized in that, The first grounding switch and the second grounding switch are PNP transistors, and the first control switch and the second control switch are NPN transistors.

9. The power circuit board as described in claim 1, characterized in that, Also includes: A first docking terminal is disposed on the first circuit board body. The first docking terminal is electrically connected to the gate of the upper bridge arm power transistor and the gate of the lower bridge arm power transistor. The first docking terminal is used to dock with the drive circuit board.

10. A motor controller, characterized in that, include: The power circuit board as described in any one of claims 1 to 9; A driving circuit board includes a second circuit board body, a first driving chip, and a second driving chip. The first driving chip and the second driving chip are disposed on the second circuit board body. The driving circuit board can interface with the power circuit board. The first driving chip is used to drive the upper bridge arm power transistor, and the second driving chip is used to drive the lower bridge arm power transistor.

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