A power switching circuit
By combining MOSFETs and transistors in the circuit design, the problems of lifespan, power loss and stability of traditional power switching circuits in multi-power input scenarios are solved, and efficient, stable power switching and seamless power conversion are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- DONGGUAN BOYU ELECTRONIC TECH CO LTD
- Filing Date
- 2025-08-04
- Publication Date
- 2026-06-26
AI Technical Summary
Traditional power switching circuits suffer from problems such as limited lifespan, poor contact, high power loss, slow response speed, and unstable switching in multi-power input scenarios, making it difficult to meet the dynamic requirements of complex application scenarios.
The circuit design employs a combination of MOSFETs and transistors. MOSFETs Q1 and Q2 control the switching on and off of the two power supplies. Combined with capacitor C1 and MOSFET Q5, seamless switching is achieved, eliminating dead time and improving switching stability and efficiency.
It achieves efficient and stable power switching, eliminates system failures caused by switching delays and misoperations, and ensures the stability and continuity of output voltage.
Smart Images
Figure CN224418505U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power supply circuit technology, specifically to a power switching circuit. Background Technology
[0002] In modern electronic devices and systems, the design of power supply circuits is crucial, especially in scenarios requiring multiple power inputs. Achieving efficient and reliable power switching becomes a key issue. Traditional power switching circuits typically rely on mechanical switches or simple diode isolation to select and switch power sources. However, these methods have significant shortcomings. While mechanical switches can achieve power switching, their lifespan is limited, and they are prone to poor contact in high-frequency switching scenarios. Although diode isolation is simple and reliable, it leads to significant power loss in practical applications, affecting the overall system efficiency. Furthermore, traditional solutions often lack precise control over the power switching process, making it difficult to meet the dynamic requirements of complex application scenarios.
[0003] As electronic devices place increasingly higher demands on power management, existing power switching circuits are gradually revealing their limitations in terms of response speed, power consumption control, and switching stability. Especially in scenarios with multiple power inputs, ensuring the stability and continuity of the output voltage during power switching, while avoiding system failures due to switching delays or misoperations, has become a pressing technical challenge. Utility Model Content
[0004] The purpose of this invention is to address the aforementioned shortcomings in the prior art by providing a power output circuit.
[0005] The purpose of this utility model is achieved through the following technical solution: a power switching circuit, including a first input port, a second input port and an output port; the power switching circuit also includes MOSFET Q1, MOSFET Q2, transistor Q4, resistor R2, resistor R3, resistor R4 and resistor R5;
[0006] The drain of the MOS transistor Q1 is connected to the first input port; the source of the MOS transistor Q1 is connected to the output port; and the gate of the MOS transistor Q1 is connected to the output port through resistor R3.
[0007] The base of transistor Q4 is connected to the first input port through resistor R4; the base of transistor Q4 is grounded through resistor R5; the emitter of transistor Q4 is grounded; and the collector of transistor Q4 is connected to the gate of MOSFET Q1.
[0008] The gate of the MOS transistor Q2 is grounded through resistor R2; the source of the MOS transistor Q2 is connected to the second input port; and the drain of the MOS transistor Q2 is connected to the output port.
[0009] The present invention is further configured such that the MOS transistor Q1 is a P-type MOS transistor.
[0010] The present invention is further configured such that the MOS transistor Q2 is a P-type MOS transistor.
[0011] The present invention is further configured such that the transistor Q4 is an NPN transistor.
[0012] The present invention is further configured such that the power switching circuit includes a MOSFET Q5; the gate of the MOSFET Q5 is connected to the output port; the source of the MOSFET Q5 is connected to the first input port; and the drain of the MOSFET Q5 is connected to the base of the transistor Q4.
[0013] The present invention is further configured such that the MOS transistor Q5 is a P-type MOS transistor.
[0014] The present invention is further configured such that a capacitor C1 is provided between the collector of the transistor Q4 and the gate of the MOS transistor Q1.
[0015] The beneficial effects of this utility model are as follows: By rationally configuring components such as MOSFETs, transistors, and resistors, this utility model achieves efficient and stable power switching; by controlling the on / off of the two power supplies with MOSFETs Q1 and Q2 respectively, smooth and efficient power switching is achieved; by introducing MOSFET Q5 and capacitor C1, the switching off of MOSFET Q1 and the switching on of MOSFET Q2 can be seamlessly connected, eliminating dead time. Attached Figure Description
[0016] Figure 1 This is the circuit schematic diagram of this utility model;
[0017] Wherein: 1. First input port; 2. Second input port; 3. Output port. Detailed Implementation
[0018] The present invention will be further described in conjunction with the following embodiments.
[0019] Depend on Figure 1 As can be seen, the power switching circuit described in this embodiment includes a first input port 1, a second input port 2, and an output port 3; the power switching circuit also includes MOSFET Q1, MOSFET Q2, transistor Q4, resistor R2, resistor R3, resistor R4, and resistor R5;
[0020] The drain of the MOS transistor Q1 is connected to the first input port 1; the source of the MOS transistor Q1 is connected to the output port 3; and the gate of the MOS transistor Q1 is connected to the output port 3 through a resistor R3.
[0021] The base of transistor Q4 is connected to the first input port 1 through resistor R4; the base of transistor Q4 is grounded through resistor R5; the emitter of transistor Q4 is grounded; and the collector of transistor Q4 is connected to the gate of MOSFET Q1.
[0022] The gate of MOSFET Q2 is grounded through resistor R2; the source of MOSFET Q2 is connected to the second input port 2; and the drain of MOSFET Q2 is connected to the output port 3. In this embodiment of the power switching circuit, MOSFET Q1 is a P-type MOSFET. In this embodiment of the power switching circuit, MOSFET Q2 is a P-type MOSFET. In this embodiment of the power switching circuit, transistor Q4 is an NPN transistor.
[0023] Specifically, in this embodiment, the power switching circuit is used such that the first input port 1 is connected to the main power supply, the second input port 2 is connected to the backup power supply, and the output port 3 is connected to the load. When there is voltage input at the first input port 1, the MOSFET Q1 is activated as the main control switching element to realize the power path from the first input port 1 to the output port 3. Specifically, the drain of the MOSFET Q1 is directly connected to the first input port 1, and its source is connected to the output port 3. The gate of the MOSFET Q1 forms a feedback loop with the output port 3 through the resistor R3. This design allows the conduction state of the MOSFET Q1 to be dynamically adjusted according to the voltage change of the output port 3, thereby ensuring the voltage stability of the output port 3. In addition, the presence of the resistor R3 not only provides a stable reference level for the gate of the MOSFET Q1, but also optimizes the overall performance of the circuit through the feedback mechanism.
[0024] Meanwhile, transistor Q4 and its peripheral circuits together form a control module used to adjust the conduction or cutoff state of MOSFET Q1. Transistor Q4 is an NPN transistor. The base of transistor Q4 is connected to the first input port 1 through resistor R4 and grounded through resistor R5. The emitter of transistor Q4 is grounded, and the collector of transistor Q4 is connected to the gate of MOSFET Q1.
[0025] When there is a voltage input at the first input port 1, the base of transistor Q4 receives a high-level signal through resistor R4, causing transistor Q4 to conduct. At this time, the collector voltage of transistor Q4 decreases, which in turn causes the gate voltage of MOSFET Q1 to drop below its threshold voltage, thereby turning on MOSFET Q1 and transmitting the voltage of the first input port 1 to the output port 3. Resistors R4 and R5 form a voltage divider network, which precisely adjusts the base voltage of transistor Q4 to ensure that transistor Q4 can achieve reliable operation under different input voltage conditions.
[0026] Additionally, when there is a voltage input at the first input port 1, the gate voltage of MOSFET Q2 rises above its threshold voltage, causing MOSFET Q2 to turn off, and the backup power supply does not work.
[0027] When there is no voltage input at the first input port 1 and a voltage input at the second input port 2, the gate voltage of MOSFET Q2 is pulled low to ground, causing MOSFET Q2 to conduct and transmit the voltage from the second input port 2 to the output port 3. The function of resistor R2 is to ensure that MOSFET Q2 is in the off state when it does not receive voltage from the second input port 2, thereby avoiding unnecessary power consumption and current leakage.
[0028] When the first input port 1 loses voltage input and the second input port 2 starts to supply power, the base current of transistor Q4 disappears, transistor Q4 is cut off, and the gate voltage of MOSFET Q1 is pulled up through resistor R3, thereby turning off MOSFET Q1; in addition, MOSFET Q2 is turned on, completing the seamless switching from the first input port 1 to the second input port 2.
[0029] The power switching circuit described in this embodiment further includes a MOSFET Q5; the gate of the MOSFET Q5 is connected to the output port 3; the source of the MOSFET Q5 is connected to the first input port 1; and the drain of the MOSFET Q5 is connected to the base of the transistor Q4. In this embodiment, the MOSFET Q5 is a P-type MOSFET.
[0030] Specifically, in this embodiment, through the above settings, when the first input port 1 is powered, the gate-source voltage difference of MOSFET Q5 is zero, causing MOSFET Q5 to be in an off state. At this time, there is no impact on the overall circuit and no power consumption. When the first input port 1 loses power, the output port 3 maintains a high voltage briefly due to the load capacitor, causing the gate voltage of MOSFET Q5 to be greater than the source voltage of MOSFET Q5. MOSFET Q5 is instantly saturated and turned on, thereby forming a 0.1Ω ultra-low resistance path between the base of transistor Q4 and ground. The peak current can forcefully remove the base charge of transistor Q4, thereby forcing transistor Q4 to turn off within 100ns, greatly improving the turn-off speed of transistor Q4.
[0031] In this embodiment, a power switching circuit includes a capacitor C1 between the collector of transistor Q4 and the gate of MOSFET Q1. Specifically, when power is available at the first input port 1, capacitor C1 is charged. When power is lost at the first input port 1, the collector voltage of transistor Q4 jumps from 0.3V to 12V. The coupling effect of capacitor C1 causes the gate voltage of MOSFET Q1 to jump instantaneously by 10.9V, increasing the gate voltage of MOSFET Q1 from 0.3V to 11.2V. Subsequently, the gate voltage of MOSFET Q1 is slowly increased to 12V through the slow charging via resistor R3, thereby delaying the turn-off time of MOSFET Q1 and waiting for MOSFET Q2 to be fully turned on.
[0032] In this embodiment, the cooperation between MOSFET Q5 and capacitor C1 enables MOSFET Q4 to turn off faster and MOSFET Q1 to turn off slower, thereby creating a 220ns power supply overlap period to achieve zero voltage drop switching. This allows the power supply to the output port 3 to seamlessly switch to the second input port 2 when the first input port 1 is powered off, without any reset or fluctuation throughout the process.
[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit the scope of protection of this utility model. Although this utility model has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this utility model without departing from the essence and scope of the technical solutions of this utility model.
Claims
1. A power switching circuit, characterized in that: It includes a first input port (1), a second input port (2), and an output port (3); the power switching circuit also includes MOSFET Q1, MOSFET Q2, transistor Q4, resistor R2, resistor R3, resistor R4, and resistor R5; The drain of the MOS transistor Q1 is connected to the first input port (1); the source of the MOS transistor Q1 is connected to the output port (3); the gate of the MOS transistor Q1 is connected to the output port (3) through resistor R3. The base of transistor Q4 is connected to the first input port (1) through resistor R4; the base of transistor Q4 is grounded through resistor R5; the emitter of transistor Q4 is grounded; the collector of transistor Q4 is connected to the gate of MOS transistor Q1. The gate of the MOS transistor Q2 is grounded through resistor R2; the source of the MOS transistor Q2 is connected to the second input port (2); and the drain of the MOS transistor Q2 is connected to the output port (3).
2. The power switching circuit according to claim 1, characterized in that: The MOS transistor Q1 is a P-type MOS transistor.
3. The power switching circuit according to claim 1, characterized in that: The MOS transistor Q2 is a P-type MOS transistor.
4. The power switching circuit according to claim 1, characterized in that: The transistor Q4 is an NPN transistor.
5. A power switching circuit according to claim 1, characterized in that: The power switching circuit also includes a MOS transistor Q5; the gate of the MOS transistor Q5 is connected to the output port (3); the source of the MOS transistor Q5 is connected to the first input port (1); and the drain of the MOS transistor Q5 is connected to the base of the transistor Q4.
6. A power switching circuit according to claim 5, characterized in that: The MOSFET Q5 is a P-type MOSFET.
7. A power switching circuit according to claim 5, characterized in that: A capacitor C1 is provided between the collector of the transistor Q4 and the gate of the MOSFET Q1.