A flexible circuit substrate
By using a combination of TiO2 or SiO2 buffer layer with sputter Cu layer and electroplated copper layer on flexible circuit board, the problems of environmental pollution and high production cost in the manufacturing of flexible printed circuit boards are solved, and the fine lines and high frequency performance are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NANTONG DEAN ELECTRONIC MATERIALS CO LTD
- Filing Date
- 2025-08-07
- Publication Date
- 2026-06-26
Smart Images
Figure CN224419008U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of flexible circuit technology, specifically a flexible circuit substrate. Background Technology
[0002] In recent years, with the miniaturization and high performance of electronic devices, the mounting technology for interfaces of components and substrates has been continuously developing towards higher density. This has also led to higher precision requirements in the corresponding flexible printed circuit boards (FPCs). The technological evolution of FPCs focuses on three main directions: ultra-fine lines, high-frequency materials, and heterogeneous integration. Future breakthroughs will continue towards "lightweight, thin, flexible, and high-frequency." An FPC is a printed circuit board that uses flexible substrates (such as PI and PET) instead of traditional rigid substrates (such as FR-4). Conductive lines are formed by etching copper foil, giving it the characteristics of being bendable, foldable, and rollable.
[0003] FCCL is an abbreviation for Flexible Copper Clad Laminate, which is the core material for manufacturing flexible printed circuit boards (FPCs). Its manufacturing method involves forming a copper film on a heat-resistant film. Its core function is to provide mechanical support and electrical interconnection for flexible circuits, enabling bendable and foldable electronic circuits (such as foldable phone screens and internal connections in wearable devices).
[0004] There are generally three mainstream FCCL manufacturing technologies currently available:
[0005] 1. PI + sputter Ni / Cr alloy + sputter Cu layer + electroplated copper: The most significant drawback of this process is that the Ni / Cr alloy layer cannot be completely etched along with the Cu, requiring an additional Ni / Cr alloy etching step. Furthermore, the etching of the Ni / Cr alloy involves alkaline etching (containing ammonia) and acidic etching (nitric acid, hydrofluoric acid, etc.), resulting in significant environmental pollution from the etching wastewater.
[0006] 2. PI + copper foil: In this system, the copper foil is directly laminated to the PI. This method does not require secondary etching, but the copper foil used is relatively thick, which is not conducive to the fabrication of fine circuits.
[0007] 3. PI + Adhesive + Copper Foil: This process bonds copper foil and PI together with adhesive. It is suitable for low-cost electronics, but it has poor high-frequency performance, high dielectric loss, which leads to attenuation of 5G high-frequency signals; insufficient heat resistance, which makes SMT soldering prone to delamination; poor thickness uniformity: uneven adhesive coating affects the etching accuracy of ultra-fine lines; the process also has the problem of adhesive overflow.
[0008] To address the current manufacturing process, there is a need to develop a buffer bonding layer that allows for thinner electroplated copper layers with better adhesion between the plating and the substrate, eliminates the need for secondary etching of functional layers, and thereby provides flexible circuits with better electrical performance. Utility Model Content
[0009] The purpose of this invention is to provide a flexible circuit board to solve the problems mentioned in the background art.
[0010] To achieve the above objectives, this utility model provides the following technical solution:
[0011] A flexible circuit board, comprising:
[0012] A PI substrate, wherein a functional layer is disposed on the surface of the PI substrate;
[0013] The functional layer includes a buffer layer of TiO2 or SiO2 and CrxOy material sequentially disposed on the PI substrate, a sputter Cu layer disposed on the buffer layer, and an electroplated copper layer disposed on the sputter Cu layer.
[0014] Preferably, the functional layer is disposed on any one surface of the PI substrate or on both surfaces of the PI substrate.
[0015] Preferably, the thickness of the buffer layer is 1-100 nm.
[0016] Preferably, the thickness of the sputter Cu layer is 50-1000 nm.
[0017] Preferably, the material of the buffer layer can also be any one of Al2O3, ZrO2, HfO2, AlN, and SiC.
[0018] Compared with the prior art, the beneficial effects of this utility model are:
[0019] This invention utilizes a buffer layer made of TiO2, SiO2, or CrxOy material. Compared to the nickel-chromium alloy layer used in traditional technologies, this eliminates the need for secondary etching, reducing production steps, lowering production costs, and minimizing the generation of etching waste, making it more environmentally friendly. Compared to the traditional technique of directly bonding copper foil and PI substrate, the electroplated copper layer and sputter Cu layer are thinner, allowing for the fabrication of fine lines and providing better adhesion. Compared to the traditional technique of bonding copper foil and PI with adhesive, this invention offers superior high-frequency performance, lower dielectric loss, and improved heat resistance, thickness uniformity, and etching precision for ultra-fine lines, while eliminating the problem of adhesive overflow. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the structure of the present invention with a functional layer on one side;
[0021] Figure 2 This is a schematic diagram of the structure of this utility model, in which functional layers are provided on both sides;
[0022] Figure 3 This is a schematic diagram of the structure of this utility model after applying the mesh layer;
[0023] Figure 4 This is a schematic diagram of the structure of the mesh layer after the application of the mesh layer in this utility model.
[0024] In the diagram: 1. PI substrate; 2. Buffer layer; 3. Sputter Cu layer; 4. Electroplated copper layer; 5. Mesh layer; 6. Mesh channel. Detailed Implementation
[0025] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0026] Please see Figures 1 to 4 This utility model provides a technical solution:
[0027] Example 1: A flexible circuit board, comprising:
[0028] PI substrate 1, on which a functional layer is provided, the functional layer can be provided on any one side of PI substrate 1 or on both sides.
[0029] The functional layer includes a buffer layer 2, a sputter Cu layer 3, and an electroplated copper layer 4. The buffer layer 2 is disposed on the PI substrate 1 by magnetron sputtering. The material of the buffer layer 2 is TiO2, SiO2, or CrxOy. CrxOy can be chromium suboxide or chromium trioxide. Experiments have shown that the material of the buffer layer 2 can also be any of Al2O3, ZrO2, HfO2, AlN, or SiC. Due to the presence of the buffer layer 2, etching is not required. The thickness of the buffer layer 2 is 1-100 nm. The sputter Cu layer 3 is disposed on the buffer layer 2 by magnetron sputtering. The electroplated copper layer 4 is disposed on the sputter Cu layer 3 by electroplating. The thickness of the sputter Cu layer is 50-1000 nm. The sputter Cu layer 3 and the electroplated copper layer 4 are etched to form the shape of wires to form a circuit.
[0030] Production process:
[0031] First face:
[0032] PI substrate 1 inspection > backing film application > traction film application > cutting to appropriate length > placing in coating chamber > vacuuming coating machine > magnetron sputtering of buffer layer 2 (1-100nm) > magnetron sputtering of copper (50-1000nm) > exiting coating chamber > standing for 24 hours;
[0033] Second side:
[0034] Remove the backing of the previous process > complete the coating and cover the surface > place it in the coating chamber > vacuum the coating machine > magnetron sputtering to coat the buffer layer 2 (1-100nm) > magnetron sputtering to coat copper (50-1000nm) > exit the coating chamber > replace the protective film.
[0035] Remove the protective film, perform electroplating to form an electroplated copper layer 4, and then etch out the circuit.
[0036] Example 2: The only difference between Example 2 and Example 1 is that a mesh layer 5 is provided between the PI substrate 1 and the buffer layer 2. A mesh groove 6 is provided on the surface of the mesh layer 5, so that the buffer layer 2 is embedded in the mesh groove 6. The mesh layer 5 is set on the PI substrate 1 by magnetron sputtering, and the buffer layer 2 is set on the mesh layer 5. The material of the mesh layer 5 can be a molybdenum-tungsten alloy or metallic chromium, or other materials with a coefficient of thermal expansion between the PI substrate 1 and the buffer layer 2. When materials such as SiO2 with a large difference in coefficient of thermal expansion from the PI substrate are used, the difference in coefficient of thermal expansion can be alleviated. When plating the mesh layer 5 and the buffer layer 2, a baffle with a corresponding pattern is set so that the surface of the mesh layer 5 forms the mesh groove 6, and the buffer layer 2 is embedded in the mesh groove 6, which improves the bonding effect between the buffer layer 2 and the PI substrate 1.
[0037] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A flexible circuit board, characterized in that, include: A PI substrate, wherein a functional layer is disposed on the surface of the PI substrate; The functional layer sequentially includes a buffer layer made of one of TiO2, SiO2, or CrxOy disposed on the PI substrate, a sputter Cu layer disposed on the buffer layer, and an electroplated copper layer disposed on the sputter Cu layer.
2. The flexible circuit board according to claim 1, characterized in that: The functional layer is disposed on any one side of the PI substrate or on both sides of the PI substrate.
3. The flexible circuit board according to claim 1, characterized in that: The thickness of the buffer layer is 1-100 nm.
4. The flexible circuit board according to claim 1, characterized in that: The thickness of the sputter Cu layer is 50-1000 nm.
5. A flexible circuit board according to claim 1, characterized in that: The buffer layer can also be made of any one of Al2O3, ZrO2, HfO2, AlN, or SiC.