Solar cell and solar cell module

Abstract

The utility model relates to solar cell technical field discloses a solar cell piece and battery assembly. Solar cell piece includes: semiconductor substrate, a plurality of first grid lines and a plurality of second grid lines, at least one surface of semiconductor substrate includes a plurality of electrode areas along first direction extension and along second direction interval arrangement, first direction and second direction are perpendicular, at least partial first grid line interval arrangement in a plurality of electrode areas, second grid line and electrode area intersection form several intersection points, and the filling grid of the area greater than the intersection point area is arranged at least partial intersection point. The utility model sets up first grid line in partial electrode area, and first grid line interval arrangement, evenly collects the current in semiconductor substrate, reduces the number of first grid line, reduces the cost, sets up the filling grid at the intersection point of second grid line and electrode area, strengthens the connection strength of grid line electrode and solder strip, guarantees the reliability of current collection and export, improves the photoelectric conversion efficiency of solar cell.

Description

Technical Field

[0001] This utility model relates to the field of solar cell technology, specifically to a solar cell and a battery module. Background Technology

[0002] Solar power generation devices, also known as solar cells or photovoltaic cells, can directly convert solar energy into electrical energy. Their basic principle is based on the photovoltaic effect of the PN junction in the solar cell layer. However, the cost of photovoltaic power generation limits the wider application of photovoltaic products. A solar cell layer typically consists of several cells connected in series or parallel. Metal grid electrodes are usually printed on the front and back of the cells. These metal grid electrodes are typically made of silver paste and include several main grid lines and several fine grid lines. The fine grid lines collect the photogenerated electrons and holes generated by the cells and transmit them to the main grid lines. The main grid lines collect the current collected by the fine grid lines and serve as solder joints connecting the cells, thus guiding the current to an external circuit.

[0003] To reduce silver paste usage, busbarless (OBB) technology has gradually become a research focus. This technology eliminates the traditional main grid lines, retaining only the sub-grid lines. The core idea is to extract current through direct interconnection between the solder ribbon and the sub-grid lines. This not only saves silver paste and reduces costs but also reduces shading effects on the solar cell, increasing power output. However, in practice, the complete absence of a main grid on the front side of the solar cell significantly increases the welding difficulty, making it prone to incomplete soldering and reducing the cell's output power. Furthermore, the sub-grid lines tend to be thinner and more numerous, further increasing the welding difficulty between the cell and the solder ribbon, making it difficult to guarantee welding stability and current collection efficiency, thus affecting the photoelectric conversion efficiency of the solar cell. Utility Model Content

[0004] In view of this, the present invention provides a solar cell and a battery module to solve the problem that existing solar cells are difficult to balance photoelectric conversion efficiency and economic benefits.

[0005] In a first aspect, the present invention provides a solar cell, comprising: a semiconductor substrate, a plurality of first grid lines and a plurality of second grid lines, wherein the semiconductor substrate comprises two surfaces disposed opposite to each other, at least one surface comprising a plurality of electrode regions extending along a first direction and spaced apart along a second direction, the first direction and the second direction being perpendicular to each other; at least a portion of the first grid lines are spaced apart within the plurality of electrode regions; the second grid lines intersect with the electrode regions to form a plurality of intersection points, and at least a portion of the intersection points are provided with filling grids, the area of ​​the filling grids being larger than the area of ​​the intersection points.

[0006] Beneficial effects: The number and position of the electrode regions in this invention are consistent with the number and position of the main grid lines required in conventional solutions. However, the first grid lines are only set in some electrode regions. The first grid lines are spaced apart, which not only collects the current in the semiconductor substrate evenly, but also reduces the number of first grid lines, thereby reducing the shading of the semiconductor substrate by the first grid lines, effectively reducing the use of silver paste, lowering costs, and achieving high economic benefits. At the same time, a filler grid is set at the intersection of the second grid line and the electrode region. The area of ​​the filler grid is much larger than the area of ​​the intersection itself, increasing the contact area and helping to enhance the connection reliability between the grid line electrode and the solder ribbon, ensuring the reliability of current collection and output, and thus improving the photoelectric conversion efficiency of the solar cell.

[0007] In one alternative implementation, the number of first gate lines ranges from 8 to 16.

[0008] Beneficial effects: Compared with conventional solutions, this utility model reduces the number of main grid lines by approximately half, greatly reducing the shading of the solar cells and significantly lowering the cost of silver paste.

[0009] In one alternative embodiment, the width of the first gate line ranges from 25 μm to 35 μm, and the height of the first gate line ranges from 2 μm to 5 μm.

[0010] Beneficial effects: In this invention, the width of the first grid line is significantly reduced while the height remains unchanged, further reducing the amount of silver paste used. With the reduction in the number and width of the first grid lines, the silver paste loss is reduced by at least 20%, resulting in a significant reduction in cost.

[0011] In one alternative implementation, in the second direction, a first gate line is provided on the outermost electrode regions on both sides of the semiconductor substrate.

[0012] Beneficial effects: In the multiple first grid lines arranged at intervals in the second direction, the first grid lines are set in the leftmost and rightmost electrode regions of the semiconductor substrate to ensure the effective collection and transmission of photogenerated carriers at the edge and to ensure the output efficiency of the solar cell.

[0013] In one alternative implementation, the number of electrode regions is set to N. When N is odd, the number of first gate lines is n = (N+1) / 2, and there is a blank electrode region between any two adjacent first gate lines.

[0014] Beneficial effects: When the number of electrode regions is N, and N is an odd number, when the condition that the two outermost electrode regions in the second direction are both provided with the first gate line is met, there is a blank electrode region between every two adjacent first gate lines, and the current collection of the first gate line on the entire semiconductor substrate surface is uniform and efficient.

[0015] In one optional implementation, the number of electrode regions is set to N; when both N and N / 2 are even, the number of first gate lines n = N / 2, wherein the first gate lines are not provided on the nth and (n+1)th electrode regions; when N is even but N / 2 is odd, the number of first gate lines n = N / 2+1, wherein the first gate lines are provided on both the nth and (n+1)th electrode regions.

[0016] Beneficial effects: When the number of electrode regions is N, satisfying the condition that the two outermost electrode regions in the second direction are both provided with a first gate line, there are two cases. One is when N and N / 2 are both even numbers, in which the nth and (n+1)th electrode regions are not provided with a first gate line, resulting in two blank electrode regions between a pair of adjacent first gate lines, and one blank electrode region between other adjacent first gate lines. The other case is when N is even but N / 2 is odd, in which the nth and (n+1)th electrode regions are both provided with a first gate line, resulting in no blank electrode regions between a pair of adjacent first gate lines, and one blank electrode region between other adjacent first gate lines. For different cases, the first gate line can be flexibly set in the middle region to enhance the current collection effect of the first gate line on the entire semiconductor substrate surface.

[0017] In one alternative implementation, the width of the second gate line is 10 μm and the height is 5 μm.

[0018] In one optional embodiment, the fill grid includes one or more of the following shapes: ellipse, rectangle, rhombus, and I-shape; when the fill grid is ellipse, rectangle, or rhombus, the width of the fill grid in the second direction is 500 to 1000 times the width of the second grid line, and the width of the fill grid in the first direction is 50 to 200 times the width of the second grid line; when the fill grid is I-shaped, the width of the fill grid in the second direction is 200 to 1000 times the width of the second grid line, and the width of the fill grid in the first direction is 50 to 200 times the width of the second grid line.

[0019] Beneficial effects: The intersection of the second grid line and the electrode area is thickened with elliptical, rectangular, rhomboid, and I-shaped silver paste filling grids. The flexible arrangement of different shapes increases the contact area between the solder ribbon and the grid line electrode during soldering, thereby enhancing the connection strength between the grid line electrode and the solder ribbon, and improving the reliability of current collection and output. If the filling grid uses the same material as the first and second grid lines, only one screen printing is required. If they are different, two printings are needed: first printing the first and second grid lines, then printing the filling grid to increase the contact area between the grid line electrode and the solder ribbon, thus improving the connection strength. Furthermore, the added shape filling also makes the solar cell more aesthetically pleasing. When setting the size of the filling grid, this invention uses the narrower second grid line as a reference for determining the magnification factor, resulting in higher precision.

[0020] In one alternative implementation, the first gate line is located on the surface of the semiconductor substrate, and the second gate line passes through the passivation layer on the surface of the semiconductor substrate.

[0021] Beneficial effects: In this invention, the first gate line does not need to burn through the passivation layer on the surface of the semiconductor substrate; it floats on the surface of the semiconductor substrate and its main function is to collect and transmit current, while also serving as a connection and welding function. The second gate line, however, needs to burn through the surface passivation layer, and its main function is to collect and transmit photogenerated carriers.

[0022] Secondly, the present invention also provides a battery assembly, comprising: a plurality of solar cells as described above and a solder strip, wherein the solder strip is connected in series with adjacent solar cells and the solder strip is disposed corresponding to the electrode area on the solar cell.

[0023] Beneficial effects: Several solar cells are connected by solder ribbons to form multiple cell strings, and the cell strings are connected to form a battery module. The number and position of the solder ribbons correspond to the electrode areas. Using the solar cells of this invention to construct a battery module effectively reduces the amount of silver paste used. At the same time, the use of filled grids increases the contact area between the grid line electrodes and the solder ribbons, thereby enhancing the connection strength, ensuring the reliability of the battery module, and ultimately improving the photoelectric conversion efficiency and power generation. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of the solar cell according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of the first structure of the filling grid according to an embodiment of the present utility model;

[0027] Figure 3 This is a schematic diagram of the second structure of the filling grid according to an embodiment of the present utility model;

[0028] Figure 4 This is a schematic diagram of the third structure of the filling grid according to an embodiment of the present utility model;

[0029] Figure 5 This is a schematic diagram of the fourth structure of the filling grid according to an embodiment of the present invention.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1. Semiconductor substrate; 101. Electrode region; 2. First gate line; 3. Second gate line; 4. Fill gate. Detailed Implementation

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit it. It should also be noted that, for ease of description, only the parts relevant to the present invention are shown in the drawings, not all of the structures. In the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concept of the present invention. The accompanying drawings show various structural schematic diagrams according to embodiments of the present invention. These drawings are not drawn to scale, and some details are enlarged for clarity and may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from actual practices due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if one layer / component is "above" another layer / component in one orientation, then when the orientation is reversed, that layer / component can be "below" that other layer / component.

[0033] refer to Figures 1 to 5 This embodiment provides a solar cell, including: a semiconductor substrate 1, a plurality of first grid lines 2 and a plurality of second grid lines 3, wherein the semiconductor substrate 1 includes two surfaces disposed opposite to each other, at least one surface including a plurality of electrode regions 101 extending along a first direction and spaced apart along a second direction, the first direction and the second direction being perpendicular to each other; at least a portion of the first grid lines 2 are spaced apart within the plurality of electrode regions 101; the second grid lines 3 intersect with the electrode regions 101 to form a plurality of intersection points, and at least a portion of the intersection points are provided with filling grids 4, the area of ​​the filling grids 4 being larger than the area of ​​the intersection points.

[0034] Specifically, the substrate material of the semiconductor substrate 1 can be a silicon wafer, or other compound semiconductor materials such as gallium arsenide, or perovskite materials. The semiconductor substrate 1 typically includes a substrate and functional film layers disposed on both sides of the substrate layer. A PN junction is formed in the substrate through doping diffusion. Then, different functional film layers are disposed on the front and back sides of the substrate according to the requirements of different types of solar cells. The first gate line 2 and the second gate line 3 are gate line electrodes disposed on the front and back sides of the semiconductor substrate 1. The gate line electrodes are usually made of metal paste such as silver paste to collect and transport photogenerated carriers in the semiconductor substrate 1. In this embodiment, the semiconductor substrate 1 is described using a silicon wafer as the substrate, with surface passivation layers disposed on both sides of the silicon wafer. The number of first gate lines 2 to be disposed is usually determined according to the size of the semiconductor substrate 1. A semiconductor substrate 1 of the same size as in the conventional scheme is selected to determine the multiple electrode regions 101 on it. That is, the number and position of the electrode regions 101 in this embodiment are consistent with the number and position of the main gate lines to be disposed in the conventional scheme. Figure 1 The dashed box shown represents an electrode region 101, which can be defined by partial positioning marks at both ends along the first direction. In this embodiment, the first gate line 2 is only provided in a portion of the electrode region 101, with at least a portion of the first gate lines 2 spaced apart. This uniformly collects the current in the semiconductor substrate 1 while reducing the number of first gate lines 2, thereby reducing the shading of the semiconductor substrate 1 by the first gate lines 2, effectively reducing the use of silver paste and lowering costs. Simultaneously, a filling gate 4 is provided at the intersection of the second gate line 3 and the electrode region 101. That is, part of the filling gate 4 spaced apart on the second gate line 3 overlaps with the first gate line 1, and the other part is located in the electrode region 101 where the first gate line 2 is not provided. The area of ​​the filling gate 4 is much larger than the area of ​​the intersection itself. Figure 1 The diagram only shows a small black dot representing the filler grid 4. The increased contact area allows all the solder strips in the electrode region 101 to reliably connect with the grid line electrodes (including the first grid line 2, the second grid line 3, and the filler grid 4), effectively enhancing the connection reliability between the grid line electrodes and the solder strips, ensuring the reliability of current collection and output, and thus improving the photoelectric conversion efficiency and power generation efficiency of the solar cell.

[0035] In one embodiment, the number of the first gate lines 2 ranges from 8 to 16.

[0036] It is known that, based on the conventional scheme where the number of main grid lines ranges from 16 to 30, that is, the number of electrode regions 101 in this embodiment ranges from 16 to 30, and the number of first grid lines 2 ranges from 8 to 16. Compared with the conventional scheme, the number of main grid lines is reduced by approximately half, which greatly reduces the shading of the solar cells and significantly reduces the cost of using silver paste.

[0037] Based on the above scheme, the width of the first gate line 2 in this embodiment ranges from 25μm to 35μm, and the height of the first gate line 2 ranges from 2μm to 5μm.

[0038] In conventional schemes, the width of the main gate line ranges from 50μm to 60μm. In this embodiment, the width of the first gate line 2 is significantly reduced while the height remains unchanged, further reducing the amount of silver paste used. With the reduction in the number and width of the first gate line 2, the silver paste loss is reduced by at least 20%, resulting in a significant reduction in cost.

[0039] In one embodiment, in the second direction, the outermost electrode regions 101 on both sides of the semiconductor substrate 1 are provided with first gate lines 2.

[0040] refer to Figure 1 In this embodiment, among the multiple first grid lines 2 arranged at intervals in the second direction, it is necessary to ensure that the first grid lines 2 must be set in the leftmost and rightmost electrode regions 101 of the semiconductor substrate 1 to ensure the effective collection and transmission of photogenerated carriers at the edge and to ensure the output efficiency of the solar cell.

[0041] In one embodiment, assuming the number of electrode regions 101 is set to N, when N is odd, the number of first gate lines 2 is n = (N+1) / 2, and at this time there is a blank electrode region 101 between any two adjacent first gate lines 2.

[0042] It is important to understand that the multiple first gate lines 2 are spaced apart in multiple electrode regions 101. This spacing can be between one blank electrode region 101, or between two or more blank electrode regions 101, depending on the size of the semiconductor substrate 1. Blank electrode regions 101 are those where no first gate lines 2 are located. For example, in this embodiment, the semiconductor substrate has dimensions of 182mm*182mm, but can be set to a maximum of 210mm*210mm.

[0043] Based on this, in this embodiment, when the number of electrode regions 101 is N and N is an odd number, and the condition that the two outermost electrode regions 101 in the second direction are both provided with the first gate line 2 is met, there is a blank electrode region 101 between the adjacent first gate lines 2, and the current collection of the first gate line 2 on the entire surface of the semiconductor substrate 1 is uniform and efficient.

[0044] In another embodiment, the number of electrode regions 101 is set to N, which falls into two categories:

[0045] One approach is when both N and N / 2 are even numbers, the number of first grid lines 2, n = N / 2. In this case, the nth and (n+1)th electrode regions 101 do not have first grid lines 2. That is, when the number of electrode regions 101 is N, and both N and N / 2 are even, if the condition that the two outermost electrode regions 101 in the second direction both have first grid lines 2 is met, then there will be two blank electrode regions 101 between a pair of adjacent first grid lines 2, and one blank electrode region 101 between other adjacent first grid lines 2. For example, if the number of electrode regions 101, N, is 16, then the number of first grid lines 2, n, is 8. In this case, the 8th and 9th electrode regions 101 along the second direction do not have first grid lines 2, while the 1st, 3rd, 5th, 7th, 10th, 12th, 14th, and 16th electrode regions 101 have first grid lines 2.

[0046] Another approach is when N is even but N / 2 is odd, in which case the number of first grid lines 2, n = N / 2 + 1, is set on both the nth and (n+1th)th electrode regions 101. That is, when N is even but N / 2 is odd, setting the first grid line on both the nth and (n+1th)th electrode regions 101 results in a group of adjacent first grid lines 2 without any blank electrode regions 101 between them, while other adjacent first grid lines 2 have a blank electrode region 101 between them. For example, if the number of electrode regions 101, N, is 18, then the number of first grid lines 2, n, is 10. In this case, the first grid line 2 is set on the 9th and 10th electrode regions 101 along the second direction, and the first grid line 2 is also set on the 1st, 3rd, 5th, 7th, 9th, 10th, 12th, 14th, 16th, and 18th electrode regions 101.

[0047] In summary, for different situations, the first gate line 2 is flexibly set in the middle region of the semiconductor substrate 1 to enhance the current collection effect of the first gate line 2 on the entire surface of the semiconductor substrate 1.

[0048] In one embodiment, the width of the second gate line 3 is 10 μm and the height is 5 μm, which meets the basic requirements for collecting photogenerated carriers.

[0049] like Figures 2 to 5 As shown, the filling grid 4 includes one or more of the following shapes: ellipse, rectangle, rhombus, and I-shape. When the filling grid 4 is ellipse, rectangle, or rhombus, the width of the filling grid 4 in the second direction is 500 to 1000 times the width of the second grid line 3, and the width of the filling grid 4 in the first direction is 50 to 200 times the width of the second grid line 3. When the filling grid 4 is I-shaped, the width of the filling grid 4 in the second direction is 200 to 1000 times the width of the second grid line 3, and the width of the filling grid 4 in the first direction is 50 to 200 times the width of the second grid line 3.

[0050] Specifically, at the intersection of the second grid line 3 and the electrode region 101, the grid 4 is thickened by filling it with elliptical, rectangular, rhomboid, or I-shaped silver paste to increase the contact area. If the filling grid 4 is made of the same material as the first grid line 2 and the second grid line 3, only one screen printing is required. If they are different, two printings are required: first printing the first grid line 2 and the second grid line 3, and then printing the filling grid 4, in order to increase the contact area between the grid line electrode and the solder ribbon, thereby improving the connection strength. In addition, the addition of shape filling also makes the solar cell more aesthetically pleasing.

[0051] In this embodiment, the filling grid 4 set at the intersection of the first grid line 2 and the second grid line 3 is used as an example for specific explanation.

[0052] refer to Figure 2 When the fill grid 4 is elliptical, the major axis of the ellipse is collinear with the second grid line 3, and the minor axis is collinear with the first grid line 2. The length of the major axis of the ellipse is between 500 and 1000 times the width of the second grid line 3, and the length of the minor axis is between 50 and 200 times the width of the second grid line 3.

[0053] refer to Figure 3 When the fill grid 4 is rectangular, the long side of the rectangle is parallel to the second grid line 3, the short side is parallel to the first grid line 2, the center of the rectangle coincides with the intersection point, the length of the long side of the rectangle is between 500 and 1000 times the width of the second grid line 3, and the length of the short side is between 50 and 200 times the width of the second grid line 3.

[0054] refer to Figure 4 When the fill grid 4 is rhomboid, the long diagonal of the rhomboid is conformal to the second grid line 3, and the short diagonal is collinear with the first grid line 2. The length of the long diagonal of the rhomboid is between 500 and 1000 times the width of the second grid line 3, and the length of the short diagonal is between 50 and 200 times the width of the second grid line 3.

[0055] refer to Figure 5 When the fill grid 4 is H-shaped, the range of its first side a is 50 to 200 times the width of the second grid line 3, the range of its second side b is 100 to 600 times the width of the second grid line 3, and the range of its third side c is 50 to 200 times the width of the second grid line 3.

[0056] In this embodiment, when the fill grid is set to size 4, the magnification factor is determined based on the second grid line 3, which has a smaller width, resulting in higher accuracy.

[0057] In one embodiment, the first gate line 2 is located on the surface of the semiconductor substrate 1, and the second gate line 3 passes through the passivation layer on the surface of the semiconductor substrate 1.

[0058] In this embodiment, the first gate line 2 does not need to burn through the passivation layer on the surface of the semiconductor substrate 1. It floats on the surface of the semiconductor substrate 1, and its main function is to collect and transmit current, while also serving as a connection and welding function. The second gate line 3, on the other hand, needs to burn through the surface passivation layer, and its main function is to collect and transmit photogenerated carriers.

[0059] This embodiment also provides a battery assembly, including: a plurality of solar cells as described above and solder ribbons, wherein the solder ribbons are connected in series with adjacent solar cells, and the solder ribbons are disposed corresponding to the electrode regions 101 on the solar cells.

[0060] Several of the aforementioned solar cells are connected by solder ribbons to form multiple cell strings, and the cell strings are connected to form a battery module. In this embodiment, the number and position of the solder ribbons correspond to the electrode region 101. Using the solar cells of this embodiment to construct a battery module effectively reduces the amount of silver paste used, while using the filled grid 4 to enhance the connection strength between the grid line electrodes and the solder ribbons, ensuring the reliability of the battery module, thereby improving the photoelectric conversion efficiency and power generation.

[0061] Further functional descriptions of the above structures are the same as those of the corresponding embodiments described above, and will not be repeated here.

[0062] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0063] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate, the semiconductor substrate including two surfaces disposed opposite to each other, at least one of the surfaces including a plurality of electrode regions extending along a first direction and spaced apart along a second direction, the first direction and the second direction being perpendicular to each other; Multiple first gate lines, at least some of which are spaced apart within the multiple electrode regions; Multiple second gate lines intersect with the electrode region to form several intersection points, and at least some of the intersection points are provided with filling gates, the area of ​​which is larger than the area of ​​the intersection points.

2. The solar cell according to claim 1, characterized in that, The number of the first gate lines ranges from 8 to 16.

3. The solar cell according to claim 2, characterized in that, The width of the first gate line ranges from 25μm to 35μm, and the height of the first gate line ranges from 2μm to 5μm.

4. The solar cell according to claim 1, characterized in that, In the second direction, the first gate line is provided in the electrode regions located on the outermost sides of the semiconductor substrate.

5. The solar cell according to claim 4, characterized in that, The number of electrode regions is set to N. When N is odd, the number of first gate lines n = (N+1) / 2, and there is a blank electrode region between any two adjacent first gate lines.

6. The solar cell according to claim 4, characterized in that, The number of electrode regions is set to N; when both N and N / 2 are even, the number of first gate lines n = N / 2, wherein no first gate line is provided on the nth and (n+1)th electrode regions; when N is even but N / 2 is odd, the number of first gate lines n = N / 2 + 1, wherein the first gate line is provided on both the nth and (n+1)th electrode regions.

7. The solar cell according to claim 1, characterized in that, The second gate line has a width of 10 μm and a height of 5 μm.

8. The solar cell according to claim 7, characterized in that, The filling grid includes one or more of the following shapes: elliptical, rectangular, rhomboid, and I-shaped. When the filling grid is elliptical, rectangular, or rhomboid, the width of the filling grid in the second direction is 500 to 1000 times the width of the second grid line, and the width of the filling grid in the first direction is 50 to 200 times the width of the second grid line. When the filling grid is H-shaped, the width of the filling grid in the second direction is 200 to 1000 times the width of the second grid line, and the width of the filling grid in the first direction is 50 to 200 times the width of the second grid line.

9. The solar cell according to any one of claims 1-8, characterized in that, The first gate line is located on the surface of the semiconductor substrate, and the second gate line passes through the passivation layer on the surface of the semiconductor substrate.

10. A battery assembly, characterized in that, include: Solar cell according to any one of claims 1-9; And solder strips, which are connected in series with adjacent solar cells, and the solder strips are arranged corresponding to the electrode areas on the solar cells.

Images