A circuit for removing signal edge jitter
By using a clock signal adjustment module to perform phase shifting processing on the signals of the microcontroller and the clock circuit module, the problem of clock signal jitter in the microcontroller is solved, and stable operation of the circuit is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 广州意新智能电子有限公司
- Filing Date
- 2025-08-28
- Publication Date
- 2026-07-03
Smart Images
Figure CN224459765U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of clock signal processing, and in particular to a circuit for removing signal edge jitter. Background Technology
[0002] In circuits, crystal oscillators are crucial components of clock modules. However, because the clock signal generated by crystal oscillation is weak, the initial clock signal directly output by the clock module is easily affected by external electromagnetic interference. Therefore, existing technologies often connect the clock module to a microcontroller, and the microcontroller outputs its own clock signal based on the initial clock signal from the corresponding clock module as the circuit's operating clock signal. However, due to differences in microcontroller manufacturing processes, some microcontrollers' output clock signals may exhibit signal edge jitter, meaning there is a technical defect of unstable microcontroller clock signals used to control circuit operation, which can easily affect the normal operation of the circuit. Utility Model Content
[0003] Therefore, the purpose of this application is to provide a circuit for removing signal edge jitter, which can overcome the shortcomings of the prior art.
[0004] To achieve the above objectives, the technical solution adopted in this application is as follows:
[0005] A circuit for removing signal edge jitter includes: a clock circuit module, a microcontroller, and a clock signal adjustment module; the clock circuit module includes a first clock signal output terminal, the microcontroller includes a first clock signal input terminal and a second clock signal output terminal; the clock signal adjustment module includes a second clock signal input terminal, a third clock signal input terminal, and a third clock signal output terminal.
[0006] The first clock signal output terminal of the clock circuit module is connected to the first clock signal input terminal of the microcontroller, and the second clock signal output terminal of the microcontroller is connected to the second clock signal input terminal of the clock signal adjustment module.
[0007] The first clock signal output terminal of the clock circuit module is connected to the third clock signal input terminal of the clock signal adjustment module; the third clock signal output terminal of the clock signal adjustment module is used to output the target clock signal; the clock signal adjustment module is used to perform phase shift adjustment processing on the microcontroller clock signal output by the microcontroller according to the initial clock signal output by the clock circuit module, so as to obtain the target clock signal with signal edge jitter removed.
[0008] In one embodiment, the clock signal adjustment module includes a phase shifting unit and a trigger; the phase shifting unit includes a fourth clock signal input terminal and a fourth clock signal output terminal, and the trigger includes a fifth clock signal input terminal, a sixth clock signal input terminal, and a fifth clock signal output terminal;
[0009] The fourth clock signal input terminal of the phase shifting unit is the second clock signal input terminal of the clock signal adjustment module; the phase shifting unit is used to perform phase shifting processing on the microcontroller clock signal output by the microcontroller to obtain a phase shifted signal; the fourth clock signal output terminal of the phase shifting unit is used to output the phase shifted signal;
[0010] The fifth clock signal input terminal of the trigger is the third clock signal input terminal of the clock signal adjustment module; the sixth clock signal input terminal of the trigger is connected to the fourth clock signal output terminal of the phase shift unit; the fifth clock signal output terminal of the trigger is the third clock signal output terminal of the clock signal adjustment module; the fifth clock signal output terminal of the trigger is used to output the target clock signal obtained according to the phase shift signal and the initial clock signal.
[0011] In one embodiment, the phase-shifting unit includes a first resistor and a phase-shifting capacitor;
[0012] The first end of the first resistor is the fourth clock signal input terminal of the phase shifting unit, the second end of the first resistor is connected to the first end of the phase shifting capacitor, and the second end of the phase shifting capacitor is grounded; wherein, the first end of the phase shifting capacitor is the fourth clock signal output terminal of the phase shifting unit.
[0013] In one embodiment, the phase-shifting unit further includes a first diode and a second resistor;
[0014] The cathode of the first diode is connected to the first end of the first resistor, the anode of the first diode is connected to the first end of the second resistor, and the second end of the second resistor is connected to the first end of the phase-shifting capacitor.
[0015] In one embodiment, the phase-shifting unit further includes a second diode and a third resistor;
[0016] The anode of the second diode is connected to the first end of the first resistor, the cathode of the second diode is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first end of the phase-shifting capacitor.
[0017] In one implementation, the trigger is an edge-triggered trigger.
[0018] In one embodiment, the circuit further includes a power amplifier module, the input of which is connected to the third clock signal output of the clock signal adjustment module.
[0019] In one implementation, the clock circuit module includes a crystal oscillator, a first capacitor, and a second capacitor;
[0020] The first terminal of the crystal oscillator is the first clock signal output terminal of the clock circuit module, and the first terminal of the crystal oscillator is grounded through the first capacitor; the second terminal of the crystal oscillator is grounded through the second capacitor.
[0021] In one implementation, the first capacitor and the second capacitor have the same value.
[0022] In one implementation, the clock circuit module further includes a fourth resistor connected in parallel across the two ends of the crystal oscillator.
[0023] Compared with traditional technologies, the beneficial effects of the circuit for removing signal edge jitter described in this application are:
[0024] The circuit for removing signal edge jitter in this application is based on the connection relationship between the clock signal adjustment module and the microcontroller and the clock circuit module. The clock signal adjustment module can receive the microcontroller clock signal output by the microcontroller and the initial clock signal output by the clock circuit module. The clock signal adjustment module can perform phase shift adjustment processing on the microcontroller clock signal output by the microcontroller according to the initial clock signal output by the clock circuit module to obtain the target clock signal with removed signal edge jitter, thereby improving the stability of the output clock signal and facilitating the normal operation of the circuit.
[0025] To better understand and implement this application, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of a circuit for removing signal edge jitter according to an embodiment of this application;
[0027] Figure 2 This is a schematic diagram of a clock signal output circuit in the prior art;
[0028] Figure 3 This is a schematic diagram of the power amplifier module connection for a circuit that removes signal edge jitter according to an embodiment of this application;
[0029] Figure 4 This is a schematic diagram of a phase-shifting unit in a circuit for removing signal edge jitter according to an embodiment of this application;
[0030] Figure 5 This is a circuit diagram of a circuit for removing signal edge jitter according to an embodiment of this application.
[0031] 100. Clock circuit module; 300. Microcontroller; 500. Clock signal adjustment module; 510. Phase shift unit; 530. Trigger; 700. Power amplifier module. Detailed Implementation
[0032] To further illustrate the various embodiments, this application provides accompanying drawings. These drawings are part of the disclosure of this application and are mainly used to illustrate the embodiments, and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementation methods and the advantages of this application.
[0033] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "left", "right", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application.
[0034] Please see Figure 1 , Figure 1 This is a schematic diagram of a circuit for removing signal edge jitter provided in this embodiment. The circuit includes:
[0035] The system includes a clock circuit module 100, a microcontroller 300, and a clock signal adjustment module 500. The clock circuit module 100 includes a first clock signal output terminal, and the microcontroller 300 includes a first clock signal input terminal and a second clock signal output terminal. The clock signal adjustment module 500 includes a second clock signal input terminal, a third clock signal input terminal, and a third clock signal output terminal.
[0036] The first clock signal output terminal of the clock circuit module 100 is connected to the first clock signal input terminal of the microcontroller 300, and the second clock signal output terminal of the microcontroller 300 is connected to the second clock signal input terminal of the clock signal adjustment module 500.
[0037] The first clock signal output terminal of the clock circuit module 100 is connected to the third clock signal input terminal of the clock signal adjustment module 500; the third clock signal output terminal of the clock signal adjustment module 500 is used to output a target clock signal; the clock signal adjustment module 500 is used to perform phase shift adjustment processing on the microcontroller clock signal output by the microcontroller 300 according to the initial clock signal output by the clock circuit module 100, so as to obtain the target clock signal with signal edge jitter removed.
[0038] Please see Figure 2 In the existing technology, the clock signal output is directly output from the I / O port of the microcontroller 300, which has the disadvantage of large signal jitter. This causes the signal output by the PA to jitter with the clock signal, and fails to meet the high precision requirements.
[0039] Compared with traditional technologies, the beneficial effects of the circuit for removing signal edge jitter described in this application are:
[0040] The circuit for removing signal edge jitter in this application is based on the connection relationship between the clock signal adjustment module 500 and the microcontroller 300 and the clock circuit module 100, respectively. The clock signal adjustment module 500 can receive the microcontroller clock signal output by the microcontroller 300 and the initial clock signal output by the clock circuit module 100. The clock signal adjustment module 500 can perform phase shift adjustment processing on the microcontroller clock signal output by the microcontroller 300 according to the initial clock signal output by the clock circuit module 100 to obtain the target clock signal with removed signal edge jitter, thereby improving the stability of the output clock signal and facilitating the normal operation of the circuit.
[0041] Please see Figure 3 In one feasible embodiment, the circuit further includes a power amplifier module 700, the input of which is connected to the third clock signal output of the clock signal adjustment module 500. The power amplifier module 700 is a power amplifier (PA).
[0042] Please see Figure 4 In one feasible embodiment, the clock signal adjustment module 500 includes a phase shift unit 510 and a trigger 530; the phase shift unit 510 includes a fourth clock signal input terminal and a fourth clock signal output terminal, and the trigger 530 includes a fifth clock signal input terminal, a sixth clock signal input terminal and a fifth clock signal output terminal;
[0043] The fourth clock signal input terminal of the phase shifting unit 510 is the second clock signal input terminal of the clock signal adjustment module 500; the phase shifting unit 510 is used to perform phase shifting processing on the microcontroller clock signal output by the microcontroller 300 to obtain a phase-shifted signal; the fourth clock signal output terminal of the phase shifting unit 510 is used to output the phase-shifted signal.
[0044] The fifth clock signal input terminal of the trigger 530 is the third clock signal input terminal of the clock signal adjustment module 500; the sixth clock signal input terminal of the trigger 530 is connected to the fourth clock signal output terminal of the phase shift unit 510; the fifth clock signal output terminal of the trigger 530 is the third clock signal output terminal of the clock signal adjustment module 500; the fifth clock signal output terminal of the trigger 530 is used to output the target clock signal obtained according to the phase shift signal and the initial clock signal.
[0045] In this embodiment, the phase-shifting unit 510 is used to perform phase-shifting processing on the microcontroller clock signal, thereby changing the phase of the signal to obtain a phase-shifted signal. The trigger 530 is used to output a target clock signal with stable signal edges based on the changes in the signal edges of the phase-shifted signal and the initial clock signal.
[0046] Please see Figure 5 In one feasible embodiment, the phase-shifting unit 510 includes a first resistor R2 and a phase-shifting capacitor C3;
[0047] The first end of the first resistor R2 is the fourth clock signal input terminal of the phase shifting unit 510, and the second end of the first resistor R2 is connected to the first end of the phase shifting capacitor C3, and the second end of the phase shifting capacitor C3 is grounded; wherein, the first end of the phase shifting capacitor C3 is the fourth clock signal output terminal of the phase shifting unit 510.
[0048] In this embodiment, the first resistor R2 and the phase-shifting capacitor C3 constitute an RC phase-shifting circuit to perform phase-shifting processing on the microcontroller clock signal, thereby obtaining a phase-shifted signal.
[0049] The trigger 530 is U2.
[0050] In one feasible embodiment, the phase shifting unit 510 further includes a first diode D1 and a second resistor R3;
[0051] The cathode of the first diode D1 is connected to the first end of the first resistor R2, the anode of the first diode D1 is connected to the first end of the second resistor R3, and the second end of the second resistor R3 is connected to the first end of the phase-shifting capacitor C3.
[0052] Specifically, at the falling edge of the microcontroller clock signal, the cathode potential of the first diode D1 is lower than the anode potential, so the first diode D1 is turned on. At this time, the phase-shifting capacitor C3 outputs current to the second clock signal output terminal of the microcontroller 300 through the first resistor R2, and also through the second resistor R3 and the first diode D1, which increases the current throughput and helps to obtain a phase-shifting signal with a faster falling edge.
[0053] In one feasible embodiment, the phase shifting unit 510 further includes a second diode D2 and a third resistor R4;
[0054] The anode of the second diode D2 is connected to the first end of the first resistor R2, the cathode of the second diode D2 is connected to the first end of the third resistor R4, and the second end of the third resistor R4 is connected to the first end of the phase-shifting capacitor C3.
[0055] At the rising edge of the microcontroller clock signal, the potential of the anode of the second diode D2 is higher than that of the cathode of the second diode D2, so the second diode D2 is turned on. At this time, the second clock signal output terminal of the microcontroller 300 outputs current to the phase-shifting capacitor C3 through the first resistor R2, and also through the second diode D2 and the third resistor R4, which increases the current flow and is beneficial to obtaining a phase-shifting signal with a faster rising edge.
[0056] In one feasible embodiment, the flip-flop 530 is an edge-triggered flip-flop 530. The flip-flop 530 receives input data when a predetermined transition (positive or negative transition) of the clock pulse CP arrives. The flip-flop 530 does not trigger during CP=1 and CP=0, or when an unpredictable transition of CP occurs. A commonly used positive edge-triggered flip-flop 530 is a D flip-flop 530. In this embodiment, the flip-flop 530 model used may be SN74LVC1G175DCKR.
[0057] In one feasible embodiment, the clock circuit module 100 includes a crystal oscillator, a first capacitor C1, and a second capacitor C2;
[0058] The first terminal of the crystal oscillator is the first clock signal output terminal of the clock circuit module 100, and the first terminal of the crystal oscillator is grounded through the first capacitor C1; the second terminal of the crystal oscillator is grounded through the second capacitor C2.
[0059] In one feasible embodiment, the first capacitor C1 and the second capacitor C2 have the same value.
[0060] The first capacitor C1 and the second capacitor C2 have the same value, which can improve the balance of the high and low levels of the initial clock signal output by the clock circuit module 100.
[0061] In one feasible embodiment, the clock circuit module 100 further includes a fourth resistor R connected in parallel across the crystal oscillator.
[0062] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the scope of protection of this application.
Claims
1. A circuit for removing signal edge jitter, characterized by, include: Clock circuit module, microcontroller and clock signal adjustment module; The clock circuit module includes a first clock signal output terminal, and the microcontroller includes a first clock signal input terminal and a second clock signal output terminal; the clock signal adjustment module includes a second clock signal input terminal, a third clock signal input terminal, and a third clock signal output terminal. The first clock signal output terminal of the clock circuit module is connected to the first clock signal input terminal of the microcontroller, and the second clock signal output terminal of the microcontroller is connected to the second clock signal input terminal of the clock signal adjustment module. The first clock signal output terminal of the clock circuit module is connected to the third clock signal input terminal of the clock signal adjustment module; the third clock signal output terminal of the clock signal adjustment module is used to output the target clock signal; the clock signal adjustment module is used to perform phase shift adjustment processing on the microcontroller clock signal output by the microcontroller according to the initial clock signal output by the clock circuit module, so as to obtain the target clock signal with signal edge jitter removed.
2. The circuit for removing signal edge jitter of claim 1, wherein: The clock signal adjustment module includes a phase shifting unit and a trigger; the phase shifting unit includes a fourth clock signal input terminal and a fourth clock signal output terminal, and the trigger includes a fifth clock signal input terminal, a sixth clock signal input terminal and a fifth clock signal output terminal. The fourth clock signal input terminal of the phase shifting unit is the second clock signal input terminal of the clock signal adjustment module; the phase shifting unit is used to perform phase shifting processing on the microcontroller clock signal output by the microcontroller to obtain a phase-shifted signal; The fourth clock signal output terminal of the phase shifting unit is used to output the phase shifting signal; The fifth clock signal input terminal of the trigger is the third clock signal input terminal of the clock signal adjustment module; the sixth clock signal input terminal of the trigger is connected to the fourth clock signal output terminal of the phase shift unit; the fifth clock signal output terminal of the trigger is the third clock signal output terminal of the clock signal adjustment module; the fifth clock signal output terminal of the trigger is used to output the target clock signal obtained according to the phase shift signal and the initial clock signal.
3. The circuit for removing signal edge jitter of claim 2, wherein: The phase-shifting unit includes a first resistor and a phase-shifting capacitor; The first end of the first resistor is the fourth clock signal input terminal of the phase shifting unit, the second end of the first resistor is connected to the first end of the phase shifting capacitor, and the second end of the phase shifting capacitor is grounded; wherein, the first end of the phase shifting capacitor is the fourth clock signal output terminal of the phase shifting unit.
4. The circuit for removing signal edge jitter of claim 3, wherein: The phase-shifting unit further includes a first diode and a second resistor; The cathode of the first diode is connected to the first end of the first resistor, the anode of the first diode is connected to the first end of the second resistor, and the second end of the second resistor is connected to the first end of the phase-shifting capacitor.
5. The circuit for removing signal edge jitter of claim 3, wherein: The phase-shifting unit also includes a second diode and a third resistor; The anode of the second diode is connected to the first end of the first resistor, the cathode of the second diode is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first end of the phase-shifting capacitor.
6. The circuit of claim 3, wherein: The trigger is an edge-triggered trigger.
7. The circuit of claim 1, wherein: The circuit also includes a power amplifier module, the input of which is connected to the third clock signal output of the clock signal adjustment module.
8. The circuit of claim 1, wherein: The clock circuit module includes a crystal oscillator, a first capacitor, and a second capacitor; The first terminal of the crystal oscillator is the first clock signal output terminal of the clock circuit module, and the first terminal of the crystal oscillator is grounded through the first capacitor; the second terminal of the crystal oscillator is grounded through the second capacitor.
9. The circuit for removing signal edge jitter of claim 8, wherein: The first capacitor has the same value as the second capacitor.
10. The circuit for removing signal edge jitter of claim 8, wherein: The clock circuit module also includes a fourth resistor, which is connected in parallel across the two ends of the crystal oscillator.