Semiconductor device

Abstract

This invention provides a semiconductor device comprising: a substrate, a gate located on the substrate, a drain terminal located on the same side of the gate, and a substrate lead-out terminal. A shallow trench isolation structure is formed in the substrate between the drain terminal and the substrate lead-out terminal, and a groove is formed in the shallow trench isolation structure, within which an auxiliary gate is formed. The auxiliary gate reduces the electric field strength at the corners of the shallow trench isolation structure, while the groove within the shallow trench isolation structure, by thinning the structure, increases the auxiliary gate's control over the electric field strength, thereby improving the source-drain breakdown voltage of the device. Furthermore, this invention only reduces the thickness of the shallow trench isolation structure and adds the auxiliary gate without changing other process conditions, thus not affecting subsequent process steps and therefore not impacting other performance indicators of the device.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing, and in particular to a semiconductor device. Background Technology

[0002] High-voltage (HV) devices come in single-finger and multi-finger structures. WAT (Wafer Acceptance Test) data shows that the source-drain breakdown voltage (BVds) of multi-finger structures is approximately 5V higher than that of single-finger structures for similar devices.

[0003] The industry typically adjusts the source-drain breakdown voltage of devices by changing the IMP (ion implantation) conditions. Taking NMOS as an example, the source-drain breakdown voltage of NMOS is generally adjusted by increasing the N drift region concentration and reducing the depletion region width. However, changing the IMP conditions will also affect other performance indicators of the device (such as reliability and electrical parameters). Utility Model Content

[0004] The purpose of this invention is to provide a semiconductor device that can improve the source-drain breakdown voltage of the device without affecting other performance indicators of the device.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor device, comprising: a substrate, a gate located on the substrate, a drain terminal located on the same side of the gate terminal and a substrate lead-out terminal, wherein a shallow trench isolation structure is formed in the substrate between the drain terminal and the substrate lead-out terminal, and a groove is formed in the shallow trench isolation structure, wherein an auxiliary gate is formed in the groove.

[0006] Optionally, the shallow trench isolation structure includes a shallow trench and an isolation material filled within the shallow trench; the groove exposes a portion of the sidewall of the shallow trench.

[0007] Optionally, the cross-sectional width of the auxiliary gate is smaller than the cross-sectional width of the groove.

[0008] Optionally, the shallow trench isolation structure includes a shallow trench and an isolation material filled within the shallow trench; the sidewalls of the trench expose a portion of the isolation material.

[0009] Optionally, the sidewall of the auxiliary gate is in contact with the insulating material.

[0010] Optionally, the depth of the groove is 1 / 15 to 14 / 15 of the thickness of the shallow trench isolation structure.

[0011] Optionally, the thickness of the shallow trench isolation structure is The depth of the groove is or

[0012] Optionally, a source terminal is also provided on the other side of the gate, and a source drift region surrounding the source terminal is formed in the substrate. A drain drift region surrounding the drain terminal and a substrate drift region surrounding the substrate lead-out terminal are also formed in the substrate.

[0013] Optionally, the substrate leads are ring-shaped, surrounding the gate, the auxiliary gate, the drain drift region, and the source drift region.

[0014] Optionally, the thickness of the auxiliary gate is equal to the thickness of the gate.

[0015] Compared with existing technologies, the semiconductor device provided by this invention features a groove formed within a shallow trench isolation structure between the drain and the substrate lead-out terminal. An auxiliary gate is formed within this groove. The auxiliary gate reduces the electric field strength at the corners of the shallow trench isolation structure. Furthermore, the groove formation within the shallow trench isolation structure, by thinning the structure, increases the auxiliary gate's control over the electric field strength, thereby improving the source-drain breakdown voltage of the device. Simultaneously, this invention only reduces the thickness of the shallow trench isolation structure and adds the auxiliary gate without altering other process conditions, thus not affecting subsequent process steps and consequently not impacting other performance indicators of the device. Attached Figure Description

[0016] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the scope of the present invention. Wherein:

[0017] Figure 1 It is a cross-sectional view of a semiconductor device in the prior art.

[0018] Figure 2 It is a cross-sectional view of a semiconductor device with an auxiliary gate.

[0019] Figure 3 This is a cross-sectional view of a semiconductor device provided in an embodiment of the present invention.

[0020] Figure 4 This is a top view of a semiconductor device provided in an embodiment of the present invention.

[0021] Figure 5 This is a cross-sectional view of a semiconductor device provided in another embodiment of the present invention.

[0022] Figure 6 This is a simulation diagram of the drain-end electric field of a device structure without thinning a shallow trench isolation structure according to an embodiment of this utility model.

[0023] Figure 7 This utility model provides a shallow trench isolation structure with reduced thickness. Simulation diagram of the drain-end electric field of the device structure at that time.

[0024] Figure 8 This utility model provides a shallow trench isolation structure with reduced thickness. Simulation diagram of the drain-end electric field of the device structure at that time.

[0025] Figure 9 This utility model provides a shallow trench isolation structure with reduced thickness. Simulation diagram of the drain-end electric field of the device structure at that time.

[0026] Figure 10 This is a schematic diagram of the drain end electric field strength of the device structure when the shallow trench isolation structure is thinned to different thicknesses according to an embodiment of this utility model.

[0027] Explanation of reference numerals in the attached figures:

[0028] 10-Substrate; 11-Gate; 12-Shallow trench isolation structure; 121-Shallow trench; 122-Groove; 13-Auxiliary gate; 14-Drain terminal; 15-Substrate lead-out terminal; 16-Drain drift region; 17-Substrate drift region; 18-Source terminal; 19-Source drift region; 20, 21, 22, 23-Shallow trench isolation structure; 24-Gate dielectric layer; 25-Trap region. Detailed Implementation

[0029] Figure 1 This is a cross-sectional view of a semiconductor device in the prior art. Please refer to it. Figure 1 As shown, the semiconductor device includes a substrate 10, a gate 11 located on the substrate 10, a source terminal 18 and a drain terminal 14 located on both sides of the gate 11, and a substrate lead-out terminal 15. A source drift region 19, a drain drift region 16, and a substrate drift region 17 are also formed within the substrate 10. A plurality of shallow trench isolation structures are also formed within the substrate 10, and a shallow trench isolation structure 12 is formed within the substrate 10 between the drain terminal 14 and the substrate lead-out terminal 15.

[0030] TCAD (Technology Computer Aided Design, a semiconductor process simulation and device simulation tool) simulation revealed that the reduced source-drain breakdown voltage of the single-finger structure is due to the uneven electric field distribution in the junction region of the drain drift region 16 and the substrate drift region 17, with the electric field concentrated at the corner of the shallow trench isolation structure 12.

[0031] The inventors discovered through simulation that placing an auxiliary gate on the shallow trench isolation structure 12 between the drain terminal 14 and the substrate lead-out terminal 15 can improve the field strength at the corner of the shallow trench isolation structure 12 and increase the source-drain breakdown voltage of the device. Figure 2 As shown, an auxiliary gate 13 is disposed on the shallow trench isolation structure 12 between the drain terminal 14 and the substrate lead-out terminal 15. The auxiliary gate 13 can reduce the electric field strength at the corner of the shallow trench isolation structure 12, thereby improving the source-drain breakdown voltage of the device. However, since the shallow trench isolation structure 12 is relatively thick (approximately...), the auxiliary gate 13 can reduce the electric field strength at the corner of the shallow trench isolation structure 12, thereby improving the source-drain breakdown voltage of the device. This will result in the auxiliary gate 13 having a limited effect on improving the field strength of the shallow trench isolation structure 12.

[0032] The most effective way to improve gate control capability in a MOS structure is to change the thickness of the oxide layer. The inventors have found that this principle can be applied to improve the control of the auxiliary gate 13 over the field strength by improving the thickness of the shallow trench isolation structure 12, thereby improving the source-drain breakdown voltage of the device.

[0033] Further research reveals that this invention provides a semiconductor device comprising: a substrate, a gate located on the substrate, a drain terminal and a substrate lead-out terminal located on the same side of the gate terminal, wherein a shallow trench isolation structure is formed in the substrate between the drain terminal and the substrate lead-out terminal, and a groove is formed in the shallow trench isolation structure, wherein an auxiliary gate is formed in the groove.

[0034] The semiconductor device provided by this invention forms a groove within a shallow trench isolation structure between the drain terminal and the substrate lead-out terminal. An auxiliary gate is formed within this groove. The auxiliary gate reduces the electric field strength at the corners of the shallow trench isolation structure. Furthermore, forming a groove within the shallow trench isolation structure and thinning the structure increases the auxiliary gate's control over the electric field strength, thereby improving the source-drain breakdown voltage of the device. Simultaneously, this invention only reduces the thickness of the shallow trench isolation structure and adds the auxiliary gate without altering other process conditions, thus not affecting subsequent process steps and consequently not impacting other performance indicators of the device.

[0035] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales.

[0036] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used in this invention, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used in this invention, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used in this invention, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0037] Figure 3 This is a cross-sectional view of a semiconductor device provided in an embodiment of the present invention. Figure 4 This is a top view of a semiconductor device provided in an embodiment of the present invention. Figure 3 yes Figure 4 Cross-sectional view in the horizontal direction. Please refer to... Figure 3 and Figure 4 As shown, the semiconductor device provided in this embodiment of the present invention includes: a substrate 10, a gate 11 located on the substrate 10, a drain terminal 14 (D) and a substrate lead-out terminal 15 (B) located on the same side of the gate terminal 11, a shallow trench isolation structure 12 is formed in the substrate 10 between the drain terminal 14 and the substrate lead-out terminal 15, and a groove 122 is formed in the shallow trench isolation structure 12, and an auxiliary gate 13 is formed in the groove 122.

[0038] In this invention, a groove 122 is formed in the shallow trench isolation structure 12 between the drain terminal 14 and the substrate lead-out terminal 15, and an auxiliary gate 13 is formed in the groove 122. The auxiliary gate 13 can reduce the field strength at the corner of the shallow trench isolation structure 12, and the formation of the groove 122 in the shallow trench isolation structure 12 can reduce the thickness of the shallow trench isolation structure 12, thereby increasing the control of the field strength by the auxiliary gate 13, thereby improving the source-drain breakdown voltage of the device.

[0039] In one embodiment of this utility model, please refer to Figure 3As shown, the shallow trench isolation structure 12 includes a shallow trench 121 formed in the substrate 10 and an isolation material filled in the shallow trench 121. The shallow trench isolation structure 12 is formed simultaneously with other shallow trench isolation structures (e.g., shallow trench isolation structures 20, 21, etc.) in the substrate 10. After forming a plurality of shallow trench isolation structures flush with the upper surface of the substrate 10, the shallow trench isolation structure 12 between the drain end 14 and the substrate lead-out end 15 is etched to form a groove 122 to reduce the thickness of the shallow trench isolation structure 12. In this embodiment, the groove 122 exposes the sidewalls of the shallow trench 121, that is, the entire shallow trench isolation structure 12 is etched to remove part of the thickness of the isolation material, exposing part of the sidewalls of the shallow trench 121. Then, an auxiliary gate 13 is formed in the groove 122, the cross-sectional width of the auxiliary gate 13 being smaller than the cross-sectional width of the groove 122, that is, in Figure 3 In the horizontal direction shown, the auxiliary gate 13 does not contact the sidewall of the shallow trench 122, that is, it does not contact the substrate 10.

[0040] In one embodiment of this utility model, please refer to Figure 5 As shown, the shallow trench isolation structure 12 includes shallow trenches 121 formed in the substrate 10 and isolation material filled in the shallow trenches 122. The shallow trench isolation structure 12 is formed simultaneously with other shallow trench isolation structures (e.g., shallow trench isolation structures 20, 21, etc.) in the substrate 10. After forming a plurality of shallow trench isolation structures flush with the upper surface of the substrate 10, the shallow trench isolation structure 12 between the drain end 14 and the substrate lead-out end 15 is etched to form a groove 122 to reduce the thickness of the shallow trench isolation structure 12. In this embodiment, part of the isolation material is exposed on the sidewall of the groove 122, that is, in Figure 5 At the same horizontal level, the cross-sectional dimension of the groove 122 is smaller than that of the shallow trench isolation structure 12. This means that a portion of the shallow trench isolation structure 12 is etched to form the groove 122 within it, with the sidewalls and bottom of the groove 122 surrounded by the isolation material. Then, an auxiliary gate 13 is formed within the groove 122. The auxiliary gate 13 can cover the bottom and part of the sidewalls of the groove 122, meaning the sidewalls of the auxiliary gate 13 are in contact with the isolation material. Alternatively, the auxiliary gate 13 may not be in contact with the isolation material.

[0041] In one embodiment of this utility model, the depth of the groove 122 can be 1 / 15 to 14 / 15 of the thickness of the shallow trench isolation structure 12. That is, by forming grooves 122 of different depths, the thickness of the shallow trench isolation structure 12 can be reduced to different degrees. For example, the thickness of the shallow trench isolation structure 12 is... The depth of the groove 122 can be to For example, the depth of the groove 122 is or That is, the thickness of the shallow trench isolation structure 12 is reduced to or Of course, it's not limited to this.

[0042] In one embodiment of this invention, the gate 11 and the auxiliary gate 13 can be formed using the same process steps. For example, after forming a groove 122 in the shallow trench isolation structure 12, a gate material layer is formed on the substrate, and the gate material layer is etched to form the gate 11 and the auxiliary gate 13, thus eliminating the need for an additional photomask. Furthermore, the gate 11 and the auxiliary gate 13 have the same thickness and are made of the same material. Of course, the gate 11 and the auxiliary gate 13 can also be formed in different process steps, and the thickness of the auxiliary gate 13 can be different from that of the gate 11, and the material of the auxiliary gate 13 can also be different from that of the gate 11.

[0043] The thickness of the auxiliary gate 13 can be the same as or different from the thickness of the gate 11. The depth of the groove 122 is also within a certain range. Therefore, the upper surface of the auxiliary gate 13 can be higher than the upper surface of the substrate 10 or lower than the lower surface of the substrate 10. This utility model does not limit this.

[0044] A gate dielectric layer 24 is also formed between the gate 11 and the substrate 10. Since the auxiliary gate 13 is formed on the shallow trench isolation structure 12, and the thickness of the shallow trench isolation structure 12 is reduced in order to improve the control of the field strength of the auxiliary gate 13, there is no need to form an auxiliary gate dielectric layer between the auxiliary gate 13 and the shallow trench isolation structure 12.

[0045] Please continue to refer to this. Figures 3 to 5 As shown, in one embodiment of the present invention, a drain drift region 16 surrounding the drain terminal 14 and a substrate drift region 17 surrounding the substrate lead-out terminal 15 are further formed in the substrate 10.

[0046] A source terminal 18(S) is also provided on the other side of the gate 11, and a source drift region 19 surrounding the source terminal 18 is formed in the substrate 10. Figure 4As can be seen, the substrate lead-out terminal 15 is ring-shaped, surrounding the gate 11, the auxiliary gate 13, the drain drift region 16, and the source drift region 19.

[0047] Please refer to Figure 3 and Figure 5 As shown, the substrate 10 also has multiple shallow trench isolation structures formed to isolate different regions. For example, the shallow trench isolation structure 20 is used to isolate the source terminal 18 from the substrate lead-out terminal 15, the shallow trench isolation structure 21 is used to isolate the channel region from the source terminal 18, the shallow trench isolation structure 22 is used to isolate the channel region from the drain terminal 14, and the shallow trench isolation structure 23 is used to isolate the substrate lead-out terminal 15 from the remaining regions not shown in the figure.

[0048] Please refer to Figure 3 and Figure 5 As shown, a well region 25 is also formed in the substrate 10, and the source drift region 19, the drain drift region 16 and the substrate drift region 17 are all located above the well region 25.

[0049] This invention only reduces the thickness of the shallow trench isolation structure 12 and adds an auxiliary gate 13, without changing other process conditions or steps, and does not affect other performance indicators of the device, nor does it introduce additional costs. Furthermore, the auxiliary gate 13 does not need to be externally connected during operation, and does not add any additional downstream process steps.

[0050] In one embodiment of this utility model, taking NMOS as an example, the well region 25 is a P-well, i.e., HVPW, the source drift region 19 and the drain drift region 16 are N-drift regions, the substrate drift region 17 is a P-drift region, and the source terminal 18 and the drain terminal 14 are n-drift regions. + The substrate lead-out terminal 15 is p + .

[0051] The following uses a 55.55um / 2.78um high-voltage device as an example. With an auxiliary gate 13 added to the shallow trench isolation structure 12, the following figures are obtained with and without reducing the thickness of the shallow trench isolation structure (BSL), and with and after reducing the thickness of the shallow trench isolation structure: TCAD simulation is performed at that time. Figure 6 This is a simulation diagram of the drain-end electric field of a device structure without thinning a shallow trench isolation structure according to an embodiment of this utility model. Figure 7 This utility model provides a shallow trench isolation structure with reduced thickness. Simulation diagram of the drain-end electric field of the device structure at that time. Figure 8 This utility model provides a shallow trench isolation structure with reduced thickness. Simulation diagram of the drain-end electric field of the device structure at that time. Figure 9 This utility model provides a shallow trench isolation structure with reduced thickness. Simulation diagram of the drain-end electric field of the device structure at that time. By comparison Figures 6 to 9 As shown, compared to not reducing the thickness of the shallow trench isolation structure 12, reducing the thickness of the shallow trench isolation structure 12 (i.e., forming a groove within the shallow trench isolation structure 12) before forming the auxiliary gate 13 improves the electric field at the corner of the shallow trench isolation structure 12, effectively reducing the peak field strength, thereby significantly improving the source-drain breakdown voltage. Furthermore, the peak field strength decreases as the thickness of the shallow trench isolation structure 12 decreases, thus increasing the source-drain breakdown voltage as the thickness of the shallow trench isolation structure 12 decreases.

[0052] Figure 10 This is a schematic diagram of the drain end electric field strength of the device structure when the shallow trench isolation structure is thinned to different thicknesses according to an embodiment of this utility model. Figure 10 In the diagram, the horizontal axis represents the device location, and... Figures 6 to 9 The simulation graphs shown have a uniform horizontal axis, while the vertical axis represents the electric field intensity. Please refer to... Figure 10 As shown, the area with the horizontal coordinate between approximately 3 and 3.7 corresponds to the corner of the shallow trench isolation structure 12 near the drain end 14. Figure 10 It can be seen that as the thickness of the shallow trench isolation structure 12 is continuously reduced, the electric field strength at the corner of the shallow trench isolation structure 12 near the drain end 14 continuously decreases, and the peak field strength decreases with the reduction of the thickness of the shallow trench isolation structure 12.

[0053] Table 1

[0054]

[0055] Table 1 shows the source and drain breakdown voltages of semiconductor devices when the shallow trench isolation (STI) structure is thinned to different thicknesses. As can be seen from Table 1, the source and drain breakdown voltages increase with decreasing STI thickness. When the thickness is such that, the source-drain breakdown voltage rises to 41.9V.

[0056] In summary, the semiconductor device provided by this invention forms a groove within the shallow trench isolation structure between the drain terminal and the substrate lead-out terminal, and an auxiliary gate is formed within the groove. The auxiliary gate reduces the electric field strength at the corner of the shallow trench isolation structure. Furthermore, forming a groove within the shallow trench isolation structure and thinning the structure increases the auxiliary gate's control over the electric field strength, thereby improving the source-drain breakdown voltage of the device. Simultaneously, this invention only reduces the thickness of the shallow trench isolation structure and adds the auxiliary gate without altering other process conditions, thus not affecting subsequent process steps and consequently not impacting other performance indicators of the device.

[0057] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.

Claims

1. A semiconductor device, characterized by, include: A substrate, a gate located on the substrate, a drain terminal located on the same side of the gate, and a substrate lead-out terminal are provided. A shallow trench isolation structure is formed in the substrate between the drain terminal and the substrate lead-out terminal, and a groove is formed in the shallow trench isolation structure, and an auxiliary gate is formed in the groove.

2. The semiconductor device according to claim 1, characterized in that, The shallow trench isolation structure includes a shallow trench and an isolation material filled within the shallow trench; the groove exposes a portion of the sidewall of the shallow trench.

3. The semiconductor device of claim 2, wherein, The cross-sectional width of the auxiliary gate is smaller than the cross-sectional width of the groove.

4. The semiconductor device of claim 1, wherein The shallow trench isolation structure includes a shallow trench and an isolation material filled within the shallow trench; the sidewalls of the trench expose a portion of the isolation material.

5. The semiconductor device of claim 4, wherein, The sidewall of the auxiliary gate is in contact with the insulating material.

6. The semiconductor device of claim 1, wherein, The depth of the groove is 1 / 15 to 14 / 15 of the thickness of the shallow trench isolation structure.

7. The semiconductor device of claim 6, wherein The shallow trench isolation structure has a thickness of The depth of the recess is or 8. The semiconductor device according to any one of claims 1 to 7, wherein A source terminal is also provided on the other side of the gate. A source drift region surrounding the source terminal is formed in the substrate. A drain drift region surrounding the drain terminal and a substrate drift region surrounding the substrate lead-out terminal are also formed in the substrate.

9. The semiconductor device of claim 8, wherein, The substrate leads are ring-shaped, surrounding the gate, the auxiliary gate, the drain drift region, and the source drift region.

10. The semiconductor device of claim 1, wherein The thickness of the auxiliary gate is equal to the thickness of the gate.

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