Semiconductor structure

Abstract

A semiconductor structure includes at least one sphere, at least one bump, and at least one path. The at least one path is used to couple the at least one sphere to the at least one bump. The at least one path includes a plurality of first path edges and a plurality of second path edges, and an angle between one of the plurality of first path edges and one of the plurality of second path edges is equal to an angle between another of the plurality of first path edges and another of the plurality of second path edges.

Description

Technical Field

[0001] This disclosure pertains to a semiconductor structure. Background Technology

[0002] To meet electrical and physical constraints, substrate design faces the challenge of routing across a finite number of redistribution layers (RDLs). Some electronic design automation (EDA) routers directly route all nets. However, continuous net-by-net routing often results in poor routing quality. Furthermore, manual routing is inefficient. Utility Model Content

[0003] This disclosure includes a semiconductor structure comprising: at least one sphere; at least one bump; and at least one path for coupling at least one sphere to at least one bump, wherein the at least one path includes a first path edge and a second path edge, and the angle between one of the first path edges and one of the second path edges is equal to the angle between the other of the first path edges and the other of the second path edges.

[0004] This disclosure includes a semiconductor structure comprising: a sphere; a wiring layer located above the sphere; and a bump located above the wiring layer, wherein the wiring layer includes: routes for coupling the sphere to the bump, and wherein the routes are at equal angles to each other.

[0005] This disclosure includes a semiconductor structure comprising: a first bump; a first ball; a first beam path for coupling the first bump to the first ball; and a first path and a second path arranged parallel to each other with the first beam path; wherein the first bump in the first bump is connected to the first ball in the first ball via the first path; the second bump in the first bump is connected to the second ball in the first ball via the second path; and the first path and the second path are separated. Attached Figure Description

[0006] The various features disclosed herein can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1A to 1D These are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0008] Figure 1E This is a schematic diagram showing further details of the bundle path according to some embodiments of this disclosure;

[0009] Figure 1F Based on some embodiments disclosed herein, and Figure 1D A schematic diagram of the semiconductor device corresponding to the semiconductor device shown;

[0010] Figures 2A to 2C These are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0011] Figure 3A These are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0012] Figure 3B These are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0013] Figures 4A to 4E These are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0014] Figures 5A to 5C These are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0015] Figure 5D Some embodiments according to this disclosure Figure 5C A schematic diagram showing further details of the bundle path;

[0016] Figure 6A and Figure 6B This is a schematic diagram of a G-cell in a semiconductor device corresponding to a method of operation according to some embodiments of this disclosure;

[0017] Figure 7A and Figure 7B This is a schematic diagram of a G-cell in a semiconductor device corresponding to a method of operation according to some embodiments of this disclosure;

[0018] Figure 8A and Figure 8B This is a schematic diagram of a G-cell in a semiconductor device corresponding to a method of operation according to some embodiments of this disclosure;

[0019] Figures 9A to 9C These are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0020] Figures 10A to 10B These are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0021] Figures 11A to 11DThese are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0022] Figures 12A to 12D This is a schematic diagram of a G-cell in a semiconductor device corresponding to a method according to some embodiments of this disclosure;

[0023] Figure 13A and Figure 13B This is a schematic diagram of a G-cell in a semiconductor device corresponding to a method according to some embodiments of this disclosure;

[0024] Figures 14A to 14C These are schematic diagrams of semiconductor devices corresponding to methods of operation according to some embodiments of this disclosure;

[0025] Figure 14D This is a cross-sectional view of a structure corresponding to the above-described route structure according to some embodiments of this disclosure;

[0026] Figure 14E It is for manufacturing according to some embodiments of this disclosure. Figure 14D A flowchart of the method for the structure shown;

[0027] Figure 15A and Figure 15B This is a schematic diagram of a G-cell in a semiconductor device corresponding to a method according to some embodiments of this disclosure;

[0028] Figure 15C This is a schematic diagram of a congestion graph according to some embodiments of this disclosure;

[0029] Figure 16A and Figure 16B This is a schematic diagram of a G-cell in a semiconductor device corresponding to a method according to some embodiments of this disclosure;

[0030] Figure 17 This is a flowchart of a method for wiring a semiconductor device according to some embodiments of the present disclosure;

[0031] Figure 18 This is a flowchart of a method for wiring a semiconductor device according to some embodiments of the present disclosure;

[0032] Figure 19 Designed according to some embodiments of this disclosure Figure 1A A flowchart of a method using the semiconductor device shown;

[0033] Figure 20 Designed according to some embodiments of this disclosure Figure 1A A flowchart of a method using the semiconductor device shown;

[0034] Figure 21This is for design purposes based on some embodiments of the present disclosure. Figure 1A The diagram shows a block diagram of an electronic design automation (EDA) system for a semiconductor device.

[0035] [Symbol Explanation]

[0036] 100, 100F: Semiconductor devices

[0037] 600, 600A~600F, 800, G11, G12, G13, G14, G21, G22, G23, G24, G25~G28, G31, G32, G33, G34, G41, G42, G43, G51~G53, GCA1~GCA3, GCB1~GCB9, GCC1~GCC6, GS10~GS16: G Unit

[0038] 1400: Structure

[0039] 1400E, 1700, 1800, 1900, 2000: Method

[0040] 1500C: Congestion Map

[0041] 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1802, 1804, 1806, 1808, 1810, 1902, 1904, 1906, 1908, 2002, 2004, 2006, OP11~OP14, OP21~OP23, OP41~OP45, OP51~OP54, OP61, OP62, OP71, OP72, OP81, OP82, OP91~OP93, OP101~OP102, OP111~OP114, OP141~OP146: Operation

[0042] 2100: EDA System

[0043] 2110: I / O Interface

[0044] 2120: Hardware Processor

[0045] 2130: Network Interface

[0046] 2140: Network

[0047] 2150: Bus

[0048] 2160: Storage medium

[0049] 2161: Computer Program Code

[0050] 2162: Standard Unit Library

[0051] 2163: User Interface

[0052] 2164: Layout Diagram

[0053] 2165: Pattern Data Field

[0054] 2170: Manufacturing Tools

[0055] A11, A12, A13, A14, A21, A22, A23, A24, A31, A32, A33, A34, A41, A42, A51, A52, A61, A62, A71, A72: Angle

[0056] AG1: Steering Angle

[0057] AR1, AR2, AR3, AR4: Arrows

[0058] B1~B7, BS1, BS14: Ball

[0059] BD1, BD2: bundle

[0060] BL1~BL3: Blockages

[0061] BMP14, C1~C7, CS1: Bumps

[0062] BR1, BR2, BR3, BR4, BR5, BR6, BR7, BR11~BR14, BR19, BR21, BR61, BR62, BR81~BR84, BR91, BR92: Bundle routes

[0063] CI1: Circuit

[0064] CL1: Centerline

[0065] CR1~CR3: Zone

[0066] CR14, CRP14: Conductive pathways

[0067] D14: Grain

[0068] D31: Distance

[0069] DR1~DR7, DRS1: Routes

[0070] E81~E83, E121, E131, E141, E221, E231, E232, E241, E321, E322, E331, E341, E411, E412, E421, E422, E431, E432, E433, E521: Edge

[0071] EDR11~EDR16, EDR21~EDR26, EDR31~EDR36, EDR41~EDR44, EDR51~EDR54, EDR61~EDR64, EDR71~EDR74: Route Edge

[0072] EP1~EP7: Escape Point

[0073] GP1~GP2: Aggregation Points

[0074] ITP14: Intermediary Layer

[0075] L1~L10: Layers

[0076] N1~N7, N11~N16, N21~N26, N31, N32, N71~N74, NS1: net

[0077] P1~P4: Sales

[0078] PCB14: Printed Circuit Board

[0079] PO1: Edge area

[0080] PO2, PO3, PO11, PO12, PO13: Partial

[0081] RDL: Redistribution Layer

[0082] RY14: Wiring layer

[0083] SP1~SP5: Space

[0084] V11, V12, V14, V21, V22, V31, V32, V42, V52, V62, V72, V131, VP14: Through holes Detailed Implementation

[0085] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements, materials, values, steps, configurations, or the like are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Other elements, materials, values, steps, configurations, or the like are contemplated. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0086] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one component or feature and another illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly. As used herein, “approximately,” “about,” “roughly,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “approximately,” “about,” “roughly,” or “substantially” may be speculative unless explicitly specified. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the specification are merely examples and may decrease or vary as integrated circuits shrink.

[0087] The terms used throughout the following description and claims generally have their ordinary meaning as clearly established in the art or in the specific context in which each term is used. Those skilled in the art will understand that elements or processes may be referred to by different names. The many different embodiments detailed in this specification are merely illustrative and do not in any way limit the scope and spirit of this disclosure or any of the illustrative terms.

[0088] It is worth noting that terms such as “first” and “second” used herein to describe various components or processes are intended to distinguish one component or process from another. However, components, processes, and their sequences should not be limited by these terms. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and a second component may similarly be referred to as a first component.

[0089] In the following discussion and claims, the terms “comprising,” “including,” “containing,” “having,” “involving,” and the like shall be understood as open-ended, that is, interpreted as including but not limited to. As used herein, the term “and / or” includes any of the associated listed items and all combinations of one or more of the associated listed items, and is not mutually exclusive.

[0090] Figures 1A to 1D This is a schematic diagram of a semiconductor device 100 corresponding to a method including operations OP11 to OP14 according to some embodiments of this disclosure. In some embodiments, the method is performed by electronic design automation (EDA) tools to route the semiconductor device 100. Operations OP11 to OP14 are performed sequentially. Figures 1A to 1DThe schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0091] like Figure 1A As described, the semiconductor device 100 includes a circuit CI1, balls B1 to B3, and meshes N1 to N3. The circuit CI1 includes bumps C1 to C3. During operation OP11, the bumps and balls are connected via the meshes. Specifically, bump C1 is connected to ball B1 via mesh N1. Bump C2 is connected to ball B2 via mesh N2. Bump C3 is connected to ball B3 via mesh N3.

[0092] In some embodiments, each of nets N1 to N3 corresponds to a flight line in operation OP11. The flight line indicates a straight line connecting the bumps and balls. Bumps C1 to C3 and balls B1 to B3 are located on different layers.

[0093] like Figure 1B As described, the semiconductor device 100 further includes a bundle BD1 and aggregation points GP1 to GP2. In operation OP12, networks connected to the same input / output (I / O) interface or intellectual property (IP) core are grouped into bundles to utilize similar topologies and characteristics for wiring. Specifically, networks N1 to N3 are grouped into a bundle BD1 from aggregation point GP1 to aggregation point GP2. In some embodiments, the aggregation points in the bundle are connected by pins, such as bumps, balls, or vias. Specifically, aggregation points GP1 and GP2 in bundle BD1 connect networks N1 to N3. Bundle BD1 is a bundle with three grouped networks (such as networks N1 to N3).

[0094] like Figure 1B As described, in some embodiments, the distances between bump C1 and aggregation point GP1, bump C2 and aggregation point GP1, and bump C3 and aggregation point GP1 are approximately the same. The distances between ball B1 and aggregation point GP2, ball B2 and aggregation point GP2, and ball B3 and aggregation point GP2 are also approximately the same.

[0095] In some embodiments, the nets in the same bundle correspond to the same bus and perform similar functions. Examples of different buses are such as Double Data Rate (DDR) memory byte channels, Serial Peripheral Interface (SPI) mode, Clock (CLK) mode, General Purpose Input / Output (GPIO) mode, Peripheral Component Interconnect Express (PCIe) mode, SoundWire (SW) mode, Management Data Input / Output (MDIO) mode, DisplayPort (DP) mode, and the like.

[0096] like Figure 1C As described, the semiconductor device 100 further includes a beam path BR1, instead of a beam BD1. In operation OP13, the beam is converted into a beam path based on at least one global unit (G unit). Specifically, refer to... Figure 1B and Figure 1C According to G unit (such as Figure 8A and Figure 8B (G unit 800) to Figure 1B The beam BD1 in the middle is transformed into Figure 1C The bundle route BR1 in the middle.

[0097] like Figure 1D As described, the semiconductor device 100 further includes vias V11, V12, V21, V22, V31, V32, routes DR1-DR3, and spaces SP1-SP2, instead of a bundled route BR1. In some embodiments, bumps C1-C3 are on the same layer, and balls B1-B3 are on the same layer. Vias V11, V21, and V31 connect bumps C1-C3 to routes DR1-DR3, respectively, while vias V12, V22, and V32 connect balls B1-B3 to routes DR1-DR3, respectively. In some embodiments, the routes are spatially separated from each other. Specifically, route DR1 is separated from route DR2 by space SP1, and route DR2 is separated from route DR3 by space SP2. (See reference...) Figure 1C and Figure 1D Routes DR1 to DR3 are arranged parallel to each other along bundle route BR1.

[0098] In operation OP14, a route is generated that connects the bump and ball via through-holes and is guided by a beam path to electrically connect the bump and ball. Specifically, a route DR1 is generated that connects the bump C1 and ball B1 via through-holes V11 and V12 and is guided by a beam path BR1. A route DR2 is generated that connects the bump C2 and ball B2 via through-holes V21 and V22 and is guided by a beam path BR1. A route DR3 is generated that connects the bump C3 and ball B3 via through-holes V31 and V32 and is guided by a beam path BR1.

[0099] refer to Figures 1A to 1D In some embodiments, each of the bundle, the bundle path from which the bundle is transformed, and the path from which the bundle path is transformed is located between a bump and a ball corresponding to a grouped mesh in the bundle. Specifically, each of the bundle BD1, the bundle path BR1, and the paths DR1 to DR3 is located between bumps C1 to C3 and balls B1 to B3 corresponding to meshes N1 to N3 in the bundle BD1.

[0100] Figure 1E This is a schematic diagram showing further details of the bundle path BR1 according to some embodiments of this disclosure. Figure 1E As explained, routes DR1 to DR3 are located within route BR1. Route DR1 includes route edges EDR11 to EDR16. Route DR2 includes route edges EDR21 to EDR26. Route DR3 includes route edges EDR31 to EDR36. Route edges EDR11, EDR13, EDR15, EDR21, EDR23, EDR25, EDR31, EDR33, and EDR35 are respectively opposite to route edges EDR12, EDR14, EDR16, EDR22, EDR24, EDR26, EDR32, EDR34, and EDR36.

[0101] exist Figure 1E In the illustrated embodiment, route edges EDR11, EDR12, EDR21, EDR22, EDR31, and EDR32 are generally parallel to each other and extend horizontally. Route edges EDR13, EDR14, EDR23, EDR24, EDR33, and EDR34 are generally parallel to each other and extend diagonally. Route edges EDR15, EDR16, EDR25, EDR26, EDR35, and EDR36 are generally parallel to each other and extend vertically.

[0102] In some embodiments, the angles A11 between route edges EDR11 and EDR13, A12 between route edges EDR12 and EDR14, A21 between route edges EDR21 and EDR23, A22 between route edges EDR22 and EDR24, A31 between route edges EDR31 and EDR33, and A32 between route edges EDR32 and EDR34 are approximately equal to each other. In some embodiments, each of angles A11, A12, A21, A22, A31, and A32 is in the range of 90 degrees to 180 degrees.

[0103] Similarly, the angles A13 between route edges EDR15 and EDR13, A14 between route edges EDR16 and EDR14, A23 between route edges EDR25 and EDR23, A24 between route edges EDR26 and EDR24, A33 between route edges EDR35 and EDR33, and A34 between route edges EDR36 and EDR34 are approximately equal to each other. In some embodiments, each of angles A13, A14, A23, A24, A33, and A34 is in the range of 90 degrees to 180 degrees.

[0104] In some embodiments, the distance between routes is less than the width of the route. For example, along the horizontal direction, the distance between route edges EDR11 and EDR22 is less than or close to the width of each of routes DR1 to DR3, and the distance between route edges EDR21 and EDR32 is less than or close to the width of each of routes DR1 to DR3. Along the diagonal direction, the distance between route edges EDR13 and EDR24 is less than or close to the width of each of routes DR1 to DR3, and the distance between route edges EDR23 and EDR34 is less than or close to the width of each of routes DR1 to DR3. Along the vertical direction, the distance between route edges EDR15 and EDR26 is less than or close to the width of each of routes DR1 to DR3, and the distance between route edges EDR25 and EDR36 is less than or close to the width of each of routes DR1 to DR3. In some embodiments, the width of the route is the distance between two route edges.

[0105] Figure 1F Based on some embodiments disclosed herein, and Figure 1D A schematic diagram of semiconductor device 100F corresponding to semiconductor device 100 shown in the diagram. (Refer to...) Figure 1F and Figure 1D Semiconductor device 100F is an alternative embodiment of semiconductor device 100. Figure 1F Follow and Figure 1DThe labeling conventions are similar to those of [other labels]. For the sake of brevity, the discussion will focus more on the similarities than on [other labels]. Figure 1F and Figure 1D The differences between them.

[0106] Compared to semiconductor device 100, in semiconductor device 100F, the beam path BR1 contains only one path DR2, instead of three paths DR1 to DR3. In other words, the second path does not necessarily need to be included in the beam path BR1.

[0107] Figures 2A to 2C This is a schematic diagram of a semiconductor device 100 corresponding to a method including operations OP21 to OP23 according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Operations OP21 to OP23 are performed sequentially. Figures 2A to 2C The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0108] like Figure 2A As described, the semiconductor device 100 includes a circuit CI1, balls B1-B7, and meshes N1-N7. The circuit CI1 includes bumps C1-C7. During operation OP21, the bumps and balls are connected via the meshes. Specifically, bumps C1-C7 are connected to balls B1-B7 via meshes N1-N7. In some embodiments, each of meshes N1-N7 corresponds to a flight line. Bumps C1-C7 and balls B1-B7 are located on different layers.

[0109] like Figure 2B As explained, in operation OP22, the meshes are grouped according to pin proximity. Specifically, meshes corresponding to pins that are closer to each other are grouped together. For example, the distance between bumps C1-C3 is less than the distance between bumps C1-C3 and C4-C7, the distance between bumps C4-C7 is less than the distance between bumps C1-C3 and C4-C7, the distance between balls B1-B3 is less than the distance between balls B1-B3 and B4-B7, and the distance between balls B4-B7 is less than the distance between balls B1-B3 and B4-B7. Therefore, meshes N1-N3 are grouped together as the first group, and meshes N4-N7 are grouped together as the second group. In some embodiments, pins are implemented by bumps, balls, or through holes.

[0110] For example, each of the distances between bumps C1 and C2 and between bumps C1 and C3 is less than each of the distances between bumps C1 and C4, C1 and C5, C1 and C6, and C1 and C7, and each of the distances between balls B1 and B2 and between balls B1 and B3 is less than each of the distances between balls B1 and B4, B1 and B5, B1 and B6, and B1 and B7. Therefore, nets N1, N2, and N3 are grouped together as the first group.

[0111] For example, each of the distances between protrusions C4 and C5, C4 and C6, and C4 and C7 is less than each of the distances between protrusions C4 and C1, C4 and C2, and C4 and C3, and each of the distances between balls B4 and B5, B4 and B6, and B4 and B7 is less than each of the distances between balls B4 and B1, B4 and B2, and B4 and B3. Therefore, nets N4 and nets N5 to N7 are grouped together as the second group.

[0112] In some embodiments, also in operation OP22, nets are logically grouped. Specifically, nets are grouped together when they belong to the same bus or constraint (such as a match group or differential pair). In some embodiments, nets on the same bus perform similar functions.

[0113] In some embodiments, also in operation OP22, the nets are grouped by the user and can be configured by the user. Specifically, the user groups these nets according to the designer's preferences by adding, removing, splitting, or merging nets.

[0114] like Figure 2C As explained, the semiconductor device 100 further includes bundles BD1 and BD2. In operation OP23, bundles are created based on grouped networks. Specifically, networks N1 to N3 are grouped into bundle BD1 according to a first group, and networks N4 to N7 are grouped into bundle BD2 according to a second group.

[0115] In some embodiments, after creating bundles BD1 and BD2, bundles BD1 and BD2 are converted into bundle routes BR1 and BR2 respectively according to the G unit. After creating bundle routes BR1 and BR2, routes DR1 to DR7 are generated that are connected via through holes and guided by bundle routes BR1 to BR2 to electrically connect bumps C1 to C7 and balls B1 to B7.

[0116] Figure 3AThis is a schematic diagram of a semiconductor device 100 corresponding to a method including operation OP41 according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Figure 3A The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method. Figure 3A Follow and Figure 4A The labeling conventions are similar to those of the previous labeling conventions. Therefore, regarding... Figure 3A Further details of operation OP41 as described in [the document] are in [the document]. Figure 4A This was discussed in the text.

[0117] Figure 3B This is a schematic diagram of a semiconductor device 100 corresponding to a method including operation OP52 according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Figure 3B The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method. Figure 3B Follow and Figure 5A The labeling conventions are similar to those of the previous labeling conventions. Therefore, regarding... Figure 3B Further details of the operation of OP52 as described in [the document] are in [the document]. Figure 5A This was discussed in the text.

[0118] refer to Figure 3A and Figure 3B In some embodiments, the wiring path is flexible for connections at different design stages to meet variable design requirements. Specifically, operation OP41 corresponds to a design stage where the ball is positioned without an assigned mesh, while operation OP52 corresponds to a design stage where the bump has an escape path in the component. In some embodiments, the design stage corresponds to the wiring process. The escape path connects the bump to the escape point.

[0119] Figures 4A to 4E This is a schematic diagram of a semiconductor device 100 corresponding to a method including operations OP41 to OP45 according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Operations OP41 to OP45 are performed sequentially. Figures 4A to 4E The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0120] like Figure 4A As described, the semiconductor device 100 includes a circuit CI1, meshes N1 to N3, and balls BS1. The circuit CI1 includes bumps C1 to C3. In operation OP41, meshes are assigned to bumps. Specifically, meshes N1 to N3 are assigned to bumps C1 to C3 respectively.

[0121] like Figure 4B As described, the semiconductor device 100 further includes vias V12, V22, and V32, and a bundle BD1. During operation OP42, the bumps and the given vias are connected by the bundle. Specifically, the bumps C1 to C3 and the vias V12, V22, and V32 are connected by the bundle BD1 via meshes N1 to N3.

[0122] like Figure 4C As described herein, semiconductor device 100 further includes a beam path BR1, instead of a beam BD1. In operation OP43, the beam is wired to create the beam path. Specifically, refer to... Figure 4B and Figure 4C According to G unit (such as Figure 8A and Figure 8B (G unit 800) to Figure 4B The beam BD1 in the middle is transformed into Figure 4C The bundle route BR1 in the middle.

[0123] like Figure 4D As described, the semiconductor device 100 further includes balls B1 to B3. Ball BS1 includes at least balls B1 to B3. In operation OP44, a mesh is assigned to the balls. Specifically, meshes N1 to N3 are respectively connected to balls B1 to B3 of ball BS1. Therefore, bumps C1 to C3 are connected to balls B1 to B3 via meshes N1 to N3.

[0124] like Figure 4E As described, the semiconductor device 100 further includes vias V11, V21, V31, routes DR1 to DR3, and spaces SP1 to SP2, but not the beam route BR4. During operation OP45, routes are generated along the beam route. Specifically, routes DR1 to DR3 are generated along the beam route BR1.

[0125] refer to Figures 4A to 4E In some embodiments, during the early design phase, the spheres do not have assigned meshes, and the designer inserts through-holes for route planning, such as plating through holes (PTHs). Therefore, bundles can connect bumps and through-holes to complete the wiring.

[0126] refer to Figures 1A to 1D and Figures 4A to 4E In some embodiments, operation OP41 corresponds to operation OP11, operation OP42 corresponds to operation OP12, operations OP43 to OP44 correspond to operation OP13, and operation OP45 corresponds to operation OP14.

[0127] Figures 5A to 5CThis is a schematic diagram of a semiconductor device 100 corresponding to a method including operations OP51 to OP54 according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Operations OP51 to OP54 are performed sequentially. Figures 5A to 5C The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0128] like Figure 5A As described, the semiconductor device 100 includes a circuit CI1, exit points EP1 to EP7, balls B1 to B7, and meshes N1 to N7. Circuit CI1 includes bumps C1 to C7. In operation OP51, the bumps are connected to the exit points. Specifically, the bumps C1 to C7 in circuit CI1 are respectively connected to the exit points EP1 to EP7 via thin wires. In some embodiments, the thin wires connecting the bumps to the exit points are made of a conductive material, such as metal wire.

[0129] In operation OP52, the escape points and balls are connected via nets. Specifically, escape points EP1 to EP7 and balls B1 to B7 are connected via nets N1 to N7, respectively. In some embodiments, each of nets N1 to N7 corresponds to a flight line in operation OP52.

[0130] like Figure 5B As described, the semiconductor device 100 further includes bundles BD1 and BD2. In operation OP53, bundles are created. Specifically, bundles BD1 and BD2 are created by grouping meshes N1 to N3 into bundle BD1, and meshes N4 to N7 into bundle BD2. (See reference...) Figure 5B , Figure 2B and Figure 2C In some embodiments, bundles BD1 and BD2 are created by operations OP22 and OP23.

[0131] like Figure 5CAs described, the semiconductor device 100 further includes vias V12, V22, V32, V42, V52, V62, V72, beam paths BR1 and BR2, paths DR1 to DR7, and spaces SP1 to SP5, instead of beams BD1 and BD2. Escape points EP1 to EP7 are electrically connected to vias V12, V22, V32, V42, V52, V62, and V72 via paths DR1 to DR7, respectively. Balls B1 to B7 are electrically connected to vias V12, V22, V32, V42, V52, V62, and V72 via paths DR1 to DR7, respectively. Each of paths DR1 to DR7 is isolated from the others. Specifically, route DR1 separates from route DR2 via space SP1, route DR2 separates from route DR3 via space SP2, route DR4 separates from route DR5 via space SP3, route DR5 separates from route DR6 via space SP4, and route DR6 separates from route DR7 via space SP5.

[0132] In operation OP54, a path is generated that is connected by through-holes and guided by a bundle to electrically connect the bumps and balls. Specifically, refer to... Figure 5B and Figure 5C According to G unit (such as Figure 8A and Figure 8B Unit G (800) in the middle will be used to respectively Figure 5B The bundles BD1 and BD2 in the middle are transformed into Figure 5C The following steps are performed: First, generate the beam paths BR1 and BR2. Next, generate path DR1, which connects exit point EP1 and through hole V12 and is guided by beam path BR1 to electrically connect bump C1 and ball B1. Then, generate path DR2, which connects exit point EP2 and through hole V22 and is guided by beam path BR2 to electrically connect bump C2 and ball B2. Next, generate path DR3, which connects exit point EP3 and through hole V32 and is guided by beam path BR3 to electrically connect bump C3 and ball B3. Then, generate path DR4, which connects exit point EP4 and through hole V42 and is guided by beam path BR4 to electrically connect bump C4 and ball B4. Finally, generate path DR5, which connects exit point EP5 and through hole V52 and is guided by beam path BR5 to electrically connect bump C5 and ball B5. Finally, generate path DR6, which connects exit point EP6 and through hole V62 and is guided by beam path BR6 to electrically connect bump C6 and ball B6. A route DR7 is generated, which is connected by the exit point EP7 and the through hole V72 and guided by the bundle route BR7 to electrically connect the bump C7 and the ball B7.

[0133] refer to Figures 5A to 5C In some embodiments, the bumps in the element are pins extending to an exit point, such as fan-out through holes. Next, a bundle is created for connection. The convergence point of the bundle is directly connected to the exit point of the element.

[0134] Figure 5D Some embodiments according to this disclosure Figure 5C A schematic diagram showing further details of the bundle path BR2. (See attached diagram.) Figure 5D As explained, routes DR4 to DR7 are located within route BR2. Route DR4 includes route edges EDR41 to EDR44. Route DR5 includes route edges EDR51 to EDR54. Route DR6 includes route edges EDR61 to EDR64. Route DR7 includes route edges EDR71 to EDR74. Route edges EDR41, EDR43, EDR51, EDR53, EDR61, EDR63, EDR71, and EDR73 are respectively opposite to route edges EDR42, EDR44, EDR52, EDR54, EDR62, EDR64, EDR72, and EDR74.

[0135] exist Figure 5D In the embodiment shown, route edges EDR41, EDR42, EDR51, EDR52, EDR61, EDR62, EDR71, and EDR72 are generally parallel to each other and extend in a vertical direction. Route edges EDR43, EDR44, EDR53, EDR54, EDR63, EDR64, EDR73, and EDR74 are generally parallel to each other and extend in a diagonal direction.

[0136] In some embodiments, the angles A41 between route edges EDR41 and EDR43, A42 between route edges EDR42 and EDR44, A51 between route edges EDR51 and EDR53, A52 between route edges EDR52 and EDR54, A61 between route edges EDR61 and EDR63, A62 between route edges EDR62 and EDR64, A71 between route edges EDR71 and EDR73, and A72 between route edges EDR72 and EDR74 are substantially equal to each other. In some embodiments, each of angles A41, A42, A51, A52, A61, A62, A71, and A72 is in the range of 90 degrees to 180 degrees.

[0137] In some embodiments, the distance between routes is less than or close to the width of the route. For example, along the horizontal direction, the distance between route edges EDR42 and EDR51 is less than or close to the width of each of routes DR4 to DR7, the distance between route edges EDR52 and EDR61 is less than or close to the width of each of routes DR4 to DR7, and the distance between route edges EDR62 and EDR71 is less than or close to the width of each of routes DR4 to DR7. Along the diagonal direction, the distance between route edges EDR44 and EDR53 is less than or close to the width of each of routes DR4 to DR7, the distance between route edges EDR54 and EDR63 is less than or close to the width of each of routes DR4 to DR7, and the distance between route edges EDR64 and EDR73 is less than or close to the width of each of routes DR4 to DR7.

[0138] refer to Figures 2A to 2C and Figures 5A to 5C In some embodiments, operation OP52 corresponds to operation OP21, and operation OP53 corresponds to operation OP23.

[0139] Figure 6A and Figure 6B This is a schematic diagram of a G unit 600 in a semiconductor device 100 corresponding to a method including operations OP61 and OP62, according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Operations OP61 to OP62 are performed sequentially. Figure 6A and Figure 6B The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0140] like Figure 6A As described, the semiconductor device 100 includes G-cells 600. Each G-cell 600 includes at least G-cells G11, G21, G12, and G22. The G-cells 600 are arranged horizontally and vertically and are adjacent to each other. In operation OP61, the wiring area of ​​each layer is divided into multiple G-cells for wiring at any angle. Specifically, each layer of the semiconductor device 100 is divided into G-cells 600, and the G-cells 600 are implemented in a variable polygonal pattern and are uniformly distributed or irregularly placed. For example, the G-cell 600 is an octagonal G-cell.

[0141] In some embodiments, a global route for any degree of bundle is planned above the G-cell. A route of any angular detail is guided within the G-cell. For example, a bundle route BR1 is created along arrow AR1 across G-cells G11 to G21. A bundle route BR2 is created along arrow AR2 across G-cells G11 to G12. A bundle route BR3 is created along arrow AR4 across G-cells G12 to G21. A bundle route BR4 is created along arrow AR3 across G-cells G11 to G22. Arrow AR1 indicates the horizontal direction corresponding to 0 degrees. Arrow AR2 indicates the vertical direction corresponding to 90 degrees. Arrow AR4 indicates a direction tilted 45 degrees clockwise relative to the horizontal direction, corresponding to 135 degrees. Arrow AR3 indicates a direction tilted 45 degrees counterclockwise relative to the horizontal direction, corresponding to 45 degrees.

[0142] like Figure 6B As described, G unit 600 further includes pins P1 to P4, wiring lines BR61 and BR62, and G units G23, G31, G41, G42, and G43. Pin P1 is located above G unit G11. Pin P2 is located above G unit G23. Pin P3 is located above G unit G21. Pin P4 is located above G unit G43. Wiring line BR61 connects pins P1 and P2 and crosses G units G11, G12, and G23. Wiring line BR62 connects pins P3 and P4 and crosses G units G21, G31, G41, G42, and G43. In some embodiments, pins P1 to P4 correspond to bumps, balls, or through holes.

[0143] In operation OP62, bundle routes are planned above G units. Specifically, bundle routes BR61 are created above G units G11, G12, and G23, and bundle routes BR62 are created above G units G21, G31, G41, G42, and G43.

[0144] Figure 7A and Figure 7B This is a schematic diagram of a G cell 600 in a semiconductor device 100 corresponding to a method including operations OP71 and OP72, according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Operations OP71 to OP72 are performed sequentially. Figure 7A and Figure 7B The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0145] like Figure 7AAs described herein, the semiconductor device 100 includes a G unit 600. The G unit 600 includes pins P1 to P4 and at least G units G11, G12, G42, and G43. Pin P1 is located above G unit G12. Pin P2 is located above G unit G43. Pin P3 is located above G unit G11. Pin P4 is located above G unit G42.

[0146] In operation OP71, the G-cell capacity is evaluated. Specifically, the edge capacity of G-cell 600 is calculated. In some embodiments, the G-cell edge capacity and requirements are associated with model routing resources. For example, the G-cell edge capacity indicates the number of nets available to cross the G-cell edge, while the requirements indicate the number of nets required for a bundle route to cross the G-cell edge. When the G-cell edge capacity is greater than or equal to the bundle route requirements, the bundle route is allowed to be configured above the G-cell edge. When the G-cell edge capacity is less than the bundle route requirements, the bundle route is not allowed to be configured above the G-cell edge, or an overflow violation occurs. Further details regarding the edge capacity of G-cells are provided in... Figure 8A and Figure 8B This was discussed in the text.

[0147] like Figure 7B As described, G unit 600 further includes networks N71 to N74 and at least G units G21, G31, G22, G32, G23, and G33. Network N71 connects pins P1 and P2 and spans G units G12, G23, G33, and G43. Network N72 connects pins P1 and P2 and spans G units G12, G22, G32, and G43. Network N73 connects pins P3 and P4 and spans G units G11, G22, G32, and G42. Network N74 connects pins P3 and P4 and spans G units G11, G21, G31, and G42. In some embodiments, networks N71 and N72 are possible routes corresponding to the bundle routes of connecting pins P1 and P2, while networks N73 and N74 are possible routes corresponding to the bundle routes of connecting pins P3 and P4.

[0148] In operation OP72, congestion-optimized routes are created. Specifically, congestion indicates the degree to which multiple networks occupy the edge of a G-cell. Route configurations where a small number of networks occupy the edge of a G-cell correspond to congestion-optimized routes. For example, when pins P1 and P2 are connected by network N72, and pins P3 and P4 are connected by network N73, the edge shared by G-cells G22 and G32 is occupied by a large number of networks. Therefore, route configurations for networks N72 and N73 are not recommended and should not be created.

[0149] In contrast, when pins P1 and P2 are connected by network N72, and pins P3 and P4 are connected by network N74, the edge shared by G units G22 and G32 is occupied by a small number of networks. Therefore, route configurations for networks N72 and N74 are recommended and created. Similarly, route configurations for networks N71 and N73, as well as route configurations for networks N71 and N74, are recommended and created.

[0150] In some embodiments, congestion may be represented by the route density at each G-cell edge or on a G-cell (such as the average route density at its G-cell edges). Route density is, for example, demand and / or capacity. EDA tools may propose alternative models, such as bundle-wide routes, route density at G-cell edges, and congestion maps.

[0151] Figure 8A and Figure 8B This is a schematic diagram of a G unit 800 in a semiconductor device 100 corresponding to a method including operations OP81 and OP82, according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to route the semiconductor device 100. Operations OP81 to OP82 are performed sequentially. Figure 8A and Figure 8B The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0152] like Figure 8A As described, G unit 800 includes edges E81 to E83. Semiconductor device 100 includes meshes N11 to N16, N21 to N26, N31, N32, and a blockage BL1. Each of meshes N11 to N16 crosses edge E81. Each of meshes N21 to N26 crosses edge E82. Each of meshes N31 and N32 crosses edge E83. The blockage BL1 overlaps with edge E83 at edge portion PO1.

[0153] In operation OP81, edge capacity is evaluated. Specifically, each edge of a G-cell has an edge capacity. The edge capacity of a G-cell's edge represents the number of nets that can be configured across the edge of the G-cell without gap violations, and it models available resources such as line / space (L / S) rules and obstructions. The edge capacity of a G-cell's edge is set and calculated by dividing the non-obstructing edge length by the trace spacing. The non-obstructing edge length is the length of the G-cell's edge minus the length of the G-cell's edge that is overlapped by obstructions. The trace spacing is the width of the net and the sum of the spaces between adjacent nets.

[0154] For example, edge E81 has a length of 24 micrometers (μm). Each of meshes N11 to N16 has a width of 2 μm. Two adjacent meshes are separated by a distance of 2 μm. Specifically, the distance between meshes N11 and N12 is 2 μm, the distance between meshes N12 and N13 is 2 μm, the distance between meshes N13 and N14 is 2 μm, the distance between meshes N14 and N15 is 2 μm, and the distance between meshes N15 and N16 is 2 μm. Therefore, the edge capacity of edge E81 is 24 / (2+2) = 6. In other words, edge E81 can accommodate 6 meshes. Similarly, edge E82 has a length of 24 μm, each of meshes N21 to N26 has a width of 2 μm, and each of the distances between adjacent meshes in meshes N21 to N26 has a space of 2 μm. Therefore, the edge capacity of edge E82 is 24 / (2+2) = 6. In other words, the edge E82 can span 6 networks.

[0155] On the other hand, edge capacity is also related to the obstruction that overlaps with the corresponding edge. For example, edge E83 has a length of 24 μm. Each of nets N31 and N32 has a width of 2 μm. The distance between nets N31 and N32 is 2 μm. Obstruction BL1 overlaps with edge E83 to block the edge portion PO1 of edge E83, where the length of edge portion PO1 is 16 μm. In other words, the 16 μm edge E83 is blocked by obstruction BL1. Therefore, the edge capacity of edge E83 is (24-16) / (2+2) = 2. In other words, edge E83 can be spanned by 2 nets.

[0156] In summary, as the length of the edge of a G-cell increases, the corresponding edge capacity increases. As the length of the edge portion blocked by an obstruction increases, the corresponding edge capacity decreases. As the width of the mesh increases, the corresponding edge capacity decreases. As the space between adjacent meshes increases, the corresponding edge capacity decreases. In some embodiments, the mesh width is equal to the route width.

[0157] In some embodiments, reference Figure 8A as well as Figure 1D , Figure 4E and Figure 5C , Figure 8A The space between adjacent nets in the middle Figure 1D , Figure 4E and Figure 5C The spatial correspondences within the network are as follows: For example, the space between network N11 and N12 corresponds to space SP1. The space between network N12 and N13 corresponds to space SP2. The space between network N21 and N22 corresponds to space SP3. The space between network N22 and N23 corresponds to space SP4. The space between network N23 and N24 corresponds to space SP5.

[0158] like Figure 8B As described herein, the semiconductor device 100 includes beam paths BR81 to BR84, and non-mesh nets N11 to N16, N21 to N26, N31, N32 and obstruction BL1. Beam path BR81 crosses edge E81. Each of beam paths BR82 and BR83 crosses edge E82. Beam path BR84 crosses edge E83.

[0159] In operation OP82, the bundle path above the G unit is configured. Specifically, the bundle path is allowed to cross the corresponding edge configuration when the number of nets required by the bundle path is less than or equal to the edge capacity of the corresponding edge of the G unit. For example, in response to the bundle path BR81 requiring 4 nets and the edge capacity of edge E81 being 6, the bundle path BR81 is allowed to cross the edge E81 configuration. In some embodiments, the bundle path is generated based on the bundle and the G unit.

[0160] Similarly, in operation OP82, multiple bundle routes are allowed to be configured across corresponding edges when the number of nets required by multiple bundle routes is less than or equal to the edge capacity of the corresponding edge of cell G. For example, in response to bundle route BR82 requiring 2 nets, bundle route BR83 requiring 4 nets, and edge capacity E81 being 6, bundle routes BR82 and BR83 are allowed to be configured across edge E82. In some embodiments, bundle routes BR82 and BR83 are separated from each other.

[0161] Similarly, in operation OP82, when the number of nets required by one or more bundle routes exceeds the edge capacity of the corresponding edge of the G cell, one or more bundle routes are considered to be overflowing or not allowed to cross the corresponding edge configuration. For example, in response to bundle route BR84 requiring 3 nets and edge capacity E83 being 2, bundle route BR84 is not allowed to cross edge configuration E82, or an overflow violation occurs.

[0162] In some embodiments, when bundle lines BR81–BR83 are allowed to cross corresponding edges E81–E82 of G unit 800, routes are generated along the corresponding bundle lines BR81–BR83. Therefore, four routes corresponding to the four nets in bundle line BR81 are generated along bundle line BR81 across edge E81. Two routes corresponding to the two nets in bundle line BR82 and four routes corresponding to the four nets in bundle line BR83 are generated along bundle lines BR82 and BR83 across edge E82, respectively. In contrast, when bundle line BR84 is not allowed to cross corresponding edge E83 of G unit 800, three routes corresponding to the three nets in bundle line BR84 are not generated above edge E83, or are generated with spacing violations, and are generated above edges of G unit 800 having an edge capacity equal to or greater than 3.

[0163] In some embodiments, Figure 8A and Figure 8B The edge capacity settings in the diagram are for illustrative purposes and are not intended to be implemented exactly as described. Alternative models are applicable to implementation methods. For example, an alternative model may consolidate the capacity and / or requirements of all layers into a single layer G cell and optimize the beam path.

[0164] refer to Figure 1C and Figure 8B In some embodiments, the bundle path BR1 is implemented by one of bundles BR81 to BR83. (See reference...) Figure 5C and Figure 8B In some embodiments, the bundle routes BR1 to BR2 are implemented by bundles BR82 and BR83, respectively.

[0165] Figures 9A to 9C This is a schematic diagram of a semiconductor device 100 corresponding to a method including operations OP91 to OP93 according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Operations OP91 to OP93 are performed sequentially. Figure 9A and Figure 9C The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0166] like Figure 9A As described, the semiconductor device 100 includes a block BL1, bumps C1-C3, balls B1-B3, and meshes N1-N3. The block BL1 partially overlaps with meshes N1-N3. In operation OP91, a flying line is created. Specifically, bump C1 is connected to ball B1 via mesh N1. Bump C2 is connected to ball B2 via mesh N2. Bump C3 is connected to ball B3 via mesh N3. In some embodiments, meshes N1-N3 are flying lines.

[0167] like Figure 9B As described, the semiconductor device 100 further includes G-cells 600. G-cells 600 include at least G-cells G13, G22, and G41. Bumps C1 to C3 are located above G-cell G13. Balls B1 to B3 are located above G-cell G41. A portion of a blockage BL1 is located above G-cell G22 and the edge E221 of G-cell G22. In operation OP92, the edge capacity of the G-cells is evaluated. Specifically, the semiconductor device 100 is divided into multiple G-cells by G-cells 600, and the edge capacity of the edges of G-cells 600 is calculated by multiple bundle paths that can be used to configure the edges across the G-cells based on the location of the blockages.

[0168] For example, the edge capacity of each edge of G-cell G13 is 6. Depending on the location of the obstruction BL1, the edge capacity of edge E221 of G-cell G22 is 2. In other words, there is no obstruction above G-cell G13. Therefore, six beam paths are allowed to be configured above each edge of G-cell G13. A portion of the obstruction BL1 is located above edge E221 of G-cell G22. Therefore, two beam paths are allowed to be configured above edge E221. In some embodiments, the beam paths correspond to a mesh.

[0169] like Figure 9C As described, G unit 600 further includes bundle lines BR91 and BR92, and G units G23, G33, G12, G32, and G42. Bundle line BR91 connects protrusions C1-C3 and balls B1-B3 and spans G units G13, G23, G33, G42, and G41. Bundle line BR92 connects protrusions C1-C3 and balls B1-B3 and spans G units G13, G12, G22, G32, and G41. In some embodiments, each of bundle lines BR91 and BR92 includes nets N1-N3. Therefore, each of bundle lines BR91 and BR92 is required to have 3.

[0170] In Operation OP93, congestion-driven paths are searched globally by bundle routes to satisfy the edge capacity of G cells. Specifically, bundle routes are created above G cells where the edge capacity exceeds the demand for bundle routes. Overflow is the number of networks that exceed the edge capacity of the G cell's edge.

[0171] For example, the requirement for bundle route BR91 is 3, and each of the edges that route BR91 crosses has an edge capacity of 6, which is greater than the requirement of bundle route BR91. Therefore, bundle route BR91 is a better path with an overflow of 0. In other words, bundle route BR91 is allowed to cross the corresponding edge configuration.

[0172] In contrast, the requirement for bundle path BR92 is 3, and the edge E221 that path BR92 crosses has an edge capacity of 2, which is less than the requirement of bundle path BR92. Therefore, bundle path BR92 is a worse path with an overflow of 1. In other words, bundle path BR92 is not allowed or intended to cross edge E221.

[0173] Figures 10A to 10B This is a schematic diagram of a semiconductor device 100 corresponding to a method including operations OP101 to OP102 according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Operations OP101 to OP102 are performed sequentially. Figure 10A and Figure 10B The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0174] like Figure 10A and Figure 10B As described, the semiconductor device 100 includes a G unit GS10 and beam lines BR11 to BR14. Beam line BR11 includes 12 meshes. Beam line BR12 includes 2 meshes. Beam line BR13 includes 2 meshes. Beam line BR14 includes 4 meshes.

[0175] In some embodiments, a coarse bundle path is a bundle path containing a number of nets exceeding the edge capacity of the edge of a G cell. For example, the edge capacity of one edge of one of the G cells GS10 is 6, and the number of nets in the bundle path BR11 is 12, which is greater than 6. Therefore, the bundle path BR11 is referred to as a coarse bundle path.

[0176] In operation OP101, a coarse bundle path is configured, and the G-cell to G-cell path of the centerline of the coarse bundle path is searched. Specifically, the bundle path BR11 is configured on G-cells G12-G14, G22-G24, G32-G34, G41-G43, and G51-G53 of G-cell GS10, and the centerline CL1 of the bundle path BR11 is searched on G-cells G13, G23, G33, G42, and G52. In some embodiments, the centerline CL1 is parallel to the bundle path BR11 and located in the middle of the bundle path BR11.

[0177] like Figure 10A and Figure 10BAs explained, the centerline CL1 crosses the edges of G-units G13, G23, G33, G42, and G52. The coarse bundle line BR11 crosses the edges of G-units G13, G23, G33, G42, and G52, and further crosses the edges of G-units G12, G14, G22, G24, G32, G34, G41, G43, G51, and G53, which are adjacent to G-units G13, G23, G33, G42, and G52.

[0178] Specifically, the number of meshes in the coarse bundle path BR11 is 12, and a portion PO11 of the centerline CL1 is arranged horizontally between G units G13, G23, and G33. Therefore, three paths of the bundle path BR11 are generated across each of edges E141 and E241, six other paths of the bundle path BR11 are generated across edges E131 and E231, and the remaining three paths of the bundle path BR11 are generated across edges E121 and E221. In some embodiments, each of edges E141, E241, E131, E231, E121, and E221 extends vertically. A portion PO11 of the centerline CL1 is perpendicular to each of edges E141, E241, E131, E231, E121, and E221, and bisects edges E131 and E231 into two equal parts.

[0179] A portion PO12 of the centerline CL1 is positioned between G units G33 and G42 at a 45-degree clockwise angle relative to the horizontal direction. Therefore, three routes of the bundle path BR11 are generated across edges E341, E431, E433, and E521; six routes of the bundle path BR11 are generated across edges E331 and E421; and the remaining three routes of the bundle path BR11 are generated across edges E322, E411, E232, and E321. In some embodiments, each of edges E341, E431, E331, E421, E322, and E411 extends at a 45-degree clockwise angle relative to the vertical direction. A portion PO12 of the centerline CL1 is perpendicular to each of edges E341, E431, E331, E421, E322, and E411, and bisects edges E331 and E421 into two equal parts.

[0180] A portion PO13 of the centerline CL1 is horizontally positioned between G units G42 and G52. Therefore, three routes of bundle route BR11 are generated across edge E432, six routes of bundle route BR11 are generated across edge E422, and the remaining three routes of bundle route BR11 are generated across edge E412. In some embodiments, each of edges E432, E422, and E412 extends vertically. A portion PO13 of the centerline CL1 is perpendicular to each of edges E432, E422, and E412, and bisects edge E422 into two equal parts.

[0181] like Figure 10B As described, the semiconductor device 100 includes G-cells GS10 and a beam path BR11. In operation OP102, the requirements of adjacent G-cells are updated based on the G-cell to G-cell path along the centerline of the coarse beam path. Specifically, the number of meshes required for the coarse beam path on the edge of the adjacent G-cell is generated based on the centerline of the coarse beam path.

[0182] For example, the coarse-bundle route BR11 requires 12 nets. Therefore, the requirement for edge E141 of G unit G14 is updated to 3, the requirement for edge E131 of G unit G13 is updated to 6, and the requirement for edge E121 of G unit G12 is updated to 3. The requirement for edge E241 of G unit G24 is updated to 3, the requirement for edge E231 of G unit G23 is updated to 3, the requirement for edge E232 of G unit G23 is updated to 3, the requirement for edge E221 of G unit G22 is updated to 3, and the requirement for edge E321 of G unit G32 is updated to 3. The requirements for edge E341 of G unit G34 and edge E431 of G unit G43 are updated to 3, the requirements for edge E331 of G unit G33 and edge E421 of G unit G42 are updated to 6, and the requirements for edge E322 of G unit G32 and edge E411 of G unit G41 are updated to 3. The requirements for edge E412 of unit G41, edge E433 of unit G43, and edge E521 of unit G52 are updated to 3. The requirement for edge E422 of unit G42 is updated to 6.

[0183] Figures 11A to 11D This is a schematic diagram of a semiconductor device 100 corresponding to a method including operations OP111 to OP114 according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Operations OP111 to OP114 are performed sequentially. Figures 11A to 11D The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0184] like Figure 11AAs described, the semiconductor device 100 includes a bump CS1, a ball BS1, a mesh NS1, and blockers BL1 to BL3. The bump CS1 and the ball BS1 are connected by the mesh NS1. A portion of the mesh NS1 crosses the blockers BL2 and BL3. In some embodiments, the bump CS1 is included in circuit CI1. In operation OP111, a routing area and a flight line are created. Specifically, the routing area corresponds to the semiconductor device 100. The mesh NS1 corresponds to the flight line.

[0185] like Figure 11B As described herein, the semiconductor device 100 further includes G units, such as Figure 6A G-cell 600. Bump CS1, ball BS1, net NS1, and obstructions BL1-BL3 are located above the G-cell. In operation OP112, an abstract graph for bundle-wide routing and planning is created. Specifically, G-cells are created, and these G-cells are traversed by bump CS1, ball BS1, net NS1, and obstructions BL1-BL3.

[0186] like Figure 11C As described, the semiconductor device 100 further includes a beam path BR1. Bumps CS1 and balls BS1 are connected via a mesh NS1 and the beam path BR1. Compared to Figure 11A In the network NS1, the bundle path BR1 bypasses obstructions BL2 and BL3. In operation OP113, the bundle path above cell G is created. Specifically, the bundle path BR1 is created based on the edge capacity of the edges of cell G and the obstructions BL1 to BL3. Each edge crossed by the bundle path BR1 has an edge capacity greater than the number of networks required by the bundle path BR1.

[0187] like Figure 11D As described, the semiconductor device 100 further includes a route DRS1, rather than a bundle route BR1. Bumps CS1 and balls BS1 are electrically connected by route DRS1. In operation OP114, detailed routes are created. Specifically, route DRS1 is created along a direction parallel to bundle route BR1 and net NS1. In some embodiments, each of the routes DRS1 is separate from the others.

[0188] In some embodiments, via operations OP111–OP114, bundle global routing searches for G-cell to G-cell global routing paths for each bundle on the abstract path. Bundle routes are automatically created to save manual routing work. Congestion of all bundle routes used for routing planning on each layer is optimized. For bundle routes used in large substrate designs, designers can plan non-overlapping bundle routes to guide a large number of connections between pins, and route planning is efficient for complex designs such as multiple routing layers, complex constraints, and the like.

[0189] Figures 12A to 12DThis is a schematic diagram of G cells 600A to 600D in a semiconductor device 100 corresponding to a method according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Figures 12A to 12D The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method. In some embodiments, each of G cells 600A to 600D corresponds to G cell 600.

[0190] like Figure 12A As described herein, the semiconductor device 100 includes multiple beam lines above the G unit 600A. In some embodiments, Figure 12A The bundle routes are feasible and are created to generate routes.

[0191] like Figure 12B As described, the semiconductor device 100 includes multiple beamlines, including beamline BR1 above the G unit 600B. A portion of beamline BR1, PO2, is located on layer L2, and a portion of beamline BR1, PO3, is located on layer L3, with portions of PO2 and PO3 connected via via V131. In some embodiments, Figure 12B The bundle path BR1 in the diagram is referred to as a cross-layer bundle path and is not preferred. Specifically, bundle paths are better routed on the same layer to reduce via impedance effects, and layer transitions should only be used to address significant congestion.

[0192] like Figure 12C As described, the semiconductor device 100 includes multiple beam paths, including beam paths BR1 and BR2 above the G unit 600C. Beam paths BR1 and BR2 are on the same layer and overlap each other in region CR1. In some embodiments, Figure 12C Each of the bundle routes BR1 and BR2 is called a bundle route span and is not allowed to be created to generate routes. Specifically, bundle routes do not overlap with each other on each layer.

[0193] like Figure 12D As described, the semiconductor device 100 includes multiple beam paths, including beam path BR2 above the G unit 600C. Beam path BR2 has an acute angle of less than 90 degrees in region CR2 and an acute angle of less than 90 degrees in region CR3. In some embodiments, Figure 12D The bundle route BR2 is called an acute-angle turn route and is not allowed to be created to generate routes. Specifically, the allowed turn angles for bundle routes are obtuse or right angles, which are greater than or equal to 90 degrees.

[0194] Figure 13A and Figure 13BThis is a schematic diagram of G cells 600E and 600F in a semiconductor device 100 corresponding to a method according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Figure 13A and Figure 13B The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method. In some embodiments, each of G cells 600A to 600D corresponds to G cell 600. Reference Figures 12A to 12D , Figure 13A and Figure 13B In some embodiments, G units 600A to 600F correspond to the requirements for the beam path.

[0195] like Figure 13A As described, the semiconductor device 100 includes beamlines BR1 to BR6 above the G cell 600E. Each of beamlines BR1, BR3, and BR6 is located on layer L2, and each of beamlines BR2, BR4, and BR5 is located on layer L3. A portion of beamline BR1 overlaps with a portion of beamline BR2. Each of beamlines BR3 and BR6 is a critical beamline. Each of beamlines BR1, BR2, BR4, and BR5 is a non-critical beamline.

[0196] In some embodiments, designs with limited layers may not have a ground shield plane adjacent to the signal routing layer, and critical bundle paths are bundle paths with high speed and / or sensitivity. Therefore, it is required that critical bundle paths do not overlap with signal paths (such as non-critical bundle paths) in adjacent layers. Critical bundle paths have higher weight and / or priority than non-critical bundle paths and are routed first to prevent non-critical bundle paths in adjacent layers.

[0197] like Figure 13A As explained, adjacent layer bundle paths do not overlap with critical bundle paths. Specifically, bundle paths BR2 and BR5 do not overlap with critical bundle paths BR3 and BR6, respectively. Therefore, Figure 13A The bundle routes BR1 to BR6 are feasible and are created to generate routes.

[0198] like Figure 13BAs described, the semiconductor device 100 includes beamlines BR1 to BR6 above the G cell 600F. Each of beamlines BR1, BR3, and BR6 is located on layer L2, and each of beamlines BR2, BR4, and BR5 is located on layer L3. A portion of beamline BR1 overlaps with a portion of beamline BR2. Beamlines BR2 and BR3 are located on adjacent layers and overlap each other in region CR4. Beamlines BR5 and BR6 are located on adjacent layers and overlap each other in region CR5. Each of beamlines BR3 and BR6 is a critical beamline. Each of beamlines BR1, BR2, BR4, and BR5 is a non-critical beamline.

[0199] like Figure 13B As explained, the critical beam paths overlap with those of adjacent layers. Specifically, beam paths BR2 and BR5 overlap with critical beam paths BR3 and BR6, respectively. Therefore, Figure 13B Bundle routes BR1 to BR6 are not allowed and are not created to generate routes.

[0200] Figures 14A to 14C This is a schematic diagram of a semiconductor device 100 corresponding to a method including operations OP141 to OP144, according to some embodiments of this disclosure. In some embodiments, the method is performed by electronic design automation (EDA) tools to route the semiconductor device 100. Operations OP141 to OP144 are performed sequentially. Figures 14A to 14C The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method.

[0201] like Figure 14A As described herein, semiconductor device 100 includes circuit CI1, ball BS1, mesh, and obstruction. Circuit CI1 includes bump CS1. Obstruction includes obstruction BL1. Mesh and Figure 11A The mesh NS1 corresponds to this. In operation OP141, the bump and the ball are connected via the mesh on the substrate. Specifically, the bump CS1 is connected to the ball BS1 via the mesh on the substrate of the semiconductor device 100.

[0202] like Figure 14B As described, circuit CI1, ball BS1, mesh, and obstructions are configured in cell G (such as...). Figure 6A Above the G unit 600 in the semiconductor device 100. In operation OP142, the G unit is created on the substrate. Specifically, the G unit is created by arranging circuit CI1, ball BS1, mesh and blockage on the substrate of the semiconductor device 100.

[0203] like Figure 14BAs described, a portion of bump CS1 and a portion of ball BS1 are connected by bundle path BR1. In operation OP143, a bundle global path is created. Specifically, the bundle path connecting bump CS1 and ball BS1 is created based on the G element.

[0204] like Figure 14C As described, bump CS1 is located on layer L1. One of the obstructions and the beam path BR1 are located on layer L2. Ball BS1 is located on layer L10. In operation OP144, layers of the substrate are created, and the beam global path is located on the layers. Specifically, layers L1 to L10 are created, with bump CS1 located on layer L1. One of the obstructions and the beam path BR1 are located on layer L2. Ball BS1 is located on layer L10. In some embodiments, each layer has its own G-cells and different capacities, such as edge capacities. For global L / S rules, the same G-cell size can be assumed between layers.

[0205] refer to Figures 14A to 14C In some embodiments, Figure 14A and Figure 14B This is a top view of the semiconductor device 100, and Figure 14C This is a layer view of semiconductor device 100.

[0206] Figure 14D This is a cross-sectional view of structure 1400 corresponding to the above-described route structure according to some embodiments of this disclosure. For example... Figure 14D As described, structure 1400 includes a printed circuit board PCB14, multiple balls BS14, wiring layer RY14, multiple bumps BMP14, interposer layer ITP14, and multiple dies D14.

[0207] In some embodiments, the wiring layer RY14 is implemented using a semiconductor bonding technology (SBT) substrate. The interposer layer ITP14 is implemented using a redistribution layer (RDL) interposer. The ball BS14 is implemented using a ball grid array (BGA). The bump BMP14 is implemented using controlled collapsed chip connection (C4) bumps. The die D14 is implemented using an active device.

[0208] like Figure 14D As explained, along the Z direction, ball BS14 is placed above printed circuit board PCB14, wiring layer RY14 is placed above ball BS14, bump BMP14 is placed above wiring layer RY14, interposer layer ITP14 is placed above bump BMP14, and die D14 is placed above interposer layer ITP14.

[0209] In some embodiments, the wiring layer RY14 includes a plurality of vias V14 and a plurality of conductive lines CR14. The vias V14 and conductive lines CR14 are used to couple the ball BS14 to the bump BMP14. The interposer layer ITP14 includes a plurality of vias VP14 and a plurality of conductive lines CRP14. The vias VP14 and conductive lines CRP14 are used to couple the bump BMP14 to the die D14. In some embodiments, the vias V14, VP14, and conductive lines CR14 and CRP14 are implemented using a conductive material (such as metal).

[0210] exist Figure 14D In the embodiment shown, the ball BS14, bump BMP14, and conductive lines CR14 and CRP14 are arranged along the XY plane. The XY plane corresponds to the X and Y directions. The Y direction is indicated from the page. The X, Y, and Z directions are perpendicular to each other.

[0211] refer to Figures 1A to 14D Spheres B1 to B7 and BS1 are embodiments of sphere BS14, bumps C1 to C7 are embodiments of bump BMP14, through holes V11, V12, V21, V22, V31, V32, V42, V52, V62, V72 and V131 are embodiments of through hole V14, and routes DR1 to DR7 and DRS1 are embodiments of conductive route CR14. Figures 1A to 14B The horizontal and vertical directions shown are... Figure 14D The X and Y directions shown correspond to each other.

[0212] Figure 14E It is for manufacturing according to some embodiments of this disclosure. Figure 14D The flowchart of method 1400E of structure 1400 shown is as follows. Figure 14D As explained, method 1400E includes operations OP141 to OP146. (Reference) Figure 14D and Figure 21 In some embodiments, method 1400E is performed by manufacturing tool 2170.

[0213] During operation OP141, printed circuit board PCB14 is formed.

[0214] During operation OP142, ball BS14 is formed above and coupled to printed circuit board PCB14.

[0215] During operation OP143, wiring layer RY14 is formed above and coupled to ball BS14. Specifically, via V14 and conductive path CR14 are formed to be coupled to the corresponding ball BS14. For example, refer to Figure 5D and Figure 14EDuring operation OP143, routes DR1 to DR7 are formed.

[0216] During operation OP144, a bump BMP14 is formed above and coupled to the routing layer RY14. Specifically, the bump BMP14 is configured to be coupled to the corresponding via V14.

[0217] During operation OP145, an interposer layer ITP14 is formed above and coupled to bump BMP14. Specifically, via VP14 and conductive path CRP14 are formed to be coupled to the corresponding bump BMP14.

[0218] During operation OP146, grain D14 is formed above and coupled to the interposer ITP14. Specifically, grain D14 is formed to be coupled to the corresponding via VP14.

[0219] Figure 15A and Figure 15B This is a schematic diagram of G units GS11 to GS15 in a semiconductor device 100 corresponding to a method according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Figures 15A to 15B The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method. In some embodiments, each of the G units GS11 to GS15 corresponds to the G unit 600.

[0220] like Figure 15A As described, each G-unit in G-unit GS11 is a triangle with each angle of 60 degrees. Each G-unit in G-unit GS12 is a square with each angle of 90 degrees. Each G-unit in G-unit GS13 is a hexagon with each angle of 120 degrees. Each G-unit in G-unit GS14 is an octagon with each angle of 135 degrees. In some embodiments, G-unit GS11 is referred to as a triangular G-unit. G-unit GS12 is referred to as a square G-unit. G-unit GS13 is referred to as a hexagonal G-unit. G-unit GS14 is referred to as an octagonal G-unit.

[0221] In some embodiments, the polygonal G-cells are flexible for multi-angle routing. For example, bundle routes are allowed to be created at 30 degrees, 90 degrees, and 120 degrees above G-cell GS11. Bundle routes are allowed to be created at 0 degrees and 90 degrees above G-cell GS12. Bundle routes are allowed to be created at 30 degrees, 90 degrees, and 120 degrees above G-cell GS13. Bundle routes are allowed to be created at 0 degrees, 45 degrees, 90 degrees, and 135 degrees above G-cell GS14.

[0222] In some embodiments, a simplified and conventional G-cell for global route resource planning is used. The octagonal G-cell allows designers to plan bundled global routes using more flexible 0 / 45 / 90 / 135-degree angles for route planning. This superior directional constraint corresponds to better planar wiring capability (such as EDA tool presets).

[0223] In some embodiments, the space between G-cells can also be considered as a mixed placement of G-cells. For example, the space between dodecagonal G-cells is a triangle. Therefore, triangular G-cells are created as a mixed placement of dodecagonal G-cells.

[0224] like Figure 15B As described, each G-cell in G-cell GS15 is an octagon with an angle of 135 degrees. The beam path BR19 is positioned above G-cell GS15 and has a turning angle AG1. In some embodiments, angle AG1 is 70 degrees.

[0225] In some embodiments, detail routes can be implemented at any angle (such as 70 degrees) within the G-cell path. G-cells with other types of polygonal shapes for routing at other angles, such as dodecagonal G-cells, can be used. In some embodiments, existing detail routes with arbitrary angles are imposed on the requirements of the G-cell edges.

[0226] Figure 15C This is a schematic diagram of a congestion graph 1500C according to some embodiments of the present disclosure. In some embodiments, the congestion graph 1500C includes a plurality of G cells with multiple congestion levels. The congestion level indicates the number of networks crossing the edge of the G cell. When the number of networks crossing the edge of the G cell increases, the corresponding congestion level of the G cell increases. When the number of networks crossing the edge of the G cell decreases, the corresponding congestion level of the G cell decreases.

[0227] exist Figure 15C In the illustrated embodiment, congestion graph 1500C includes G units GCA1–GCA3, GCB1–GCB9, and GCC1–GCC6. Each of G units GCA1–GCA3 has a first congestion level. Each of G units GCB1–GCB9 has a second congestion level. Each of G units GCC1–GCC6 has a third congestion level. Each of the G units other than GCA1–GCA3, GCB1–GCB9, and GCC1–GCC6 has a fourth congestion level. The first congestion level is higher than the second congestion level, the second congestion level is higher than the third congestion level, and the third congestion level is higher than the fourth congestion level.

[0228] In some embodiments, congestion map 1500C is used to illustrate and assess route feasibility. Specifically, when the congestion level of congestion map 1500C increases, route feasibility decreases. When the congestion level of congestion map 1500C decreases, route feasibility increases.

[0229] exist Figure 15C In the embodiment shown, the G cells of the congestion graph 1500C are octagonal in shape for route planning at 0, 45, 90, and 135-degree angles. However, the embodiments disclosed herein are not limited to this. See also... Figure 15A and Figure 15C In various embodiments, the G cells of the congestion graph 1500C have flexible polygonal patterns, such as triangles, squares, or hexagons.

[0230] In various embodiments, the G-cells of congestion graph 1500C have a multi-layered structure. For example, refer to... Figure 14C and Figure 15C In some embodiments, the congestion graph 1500C includes G cells of layers L1 to L10.

[0231] In some embodiments, when the route demand is greater than or equal to the global cell edge capacity, overflow information is shown in the congestion graph 1500C. For example, refer to... Figure 8A and Figure 15C G-cell GCA1 is implemented by G-cell 800. In this example, the global cell edge capacity of edge E83 of G-cell GCA1 is 2. When the route demand of edge E83 is greater than or equal to 2, overflow information is shown at edge E83 of congestion graph 1500C.

[0232] Figure 16A and Figure 16B This is a schematic diagram of a G unit GS16 in a semiconductor device 100 corresponding to a method according to some embodiments of this disclosure. In some embodiments, the method is performed by an EDA tool to wire the semiconductor device 100. Figures 16A to 16B The schematic diagram shown corresponds to an intermediate state of the semiconductor device 100 during the wiring process of this method. In some embodiments, G unit GS16 corresponds to G unit 600.

[0233] like Figure 16A As explained, G unit GS16 contains G units G21 to G24. Each of G units G21 to G24 is a distinct irregular triangle. The bundle path BR21 traverses G units G21 to G24.

[0234] like Figure 16BAs explained, G-unit GS16 comprises G-units G25 to G28. Each of G-units G25 to G28 is a regular octagon. The bundle path BR22 crosses G-units G25 and G28.

[0235] In some embodiments, irregular G-cells are difficult to plan resources for, have unintuitive congestion graphs, and contain many sharp turns in both bundle routes and detail routes. Therefore, irregular G-cells are acceptable but not recommended. Compared to Figure 16A and Figure 16B , Figure 16A The G elements G21 to G24 in the text are irregular G elements, and Figure 16B G-units G25 to G28 in the structure are regular G-units. Therefore, the bundle path BR21 is... Figure 16A The BR21 has more sharp turns than the BR21 route. Figure 16B The sharp turns in the middle.

[0236] Figure 17 This is a flowchart of a method 1700 for wiring a semiconductor device 100 according to some embodiments of this disclosure. Figure 17 The diagram illustrates that method 1700 includes operations 1702, 1704, 1706, 1708, 1710, 1712, and 1714. In some embodiments, method 1700 is performed to wire the semiconductor device 100 described above.

[0237] In operation 1702, data is prepared. Specifically, data associated with routing the semiconductor device is prepared, such as die / package size, bumps, balls, components, netlists, layers, and obstructions. For example, data associated with routing the semiconductor device 100 is prepared (such as circuit CI1, bumps C1-C7, balls B1-B7, and nets N1-N7). In some embodiments, operation 1702 corresponds to each of the operations OP11, OP21, OP41, OP51, and OP52 described above.

[0238] In operation 1704, the nets and / or flight lines are bundled. Specifically, the nets and / or flight lines are automatically bundled by function, bus, group, pin proximity, interactive settings, or the like. For example, nets N1 to N3 and N4 to N7 are bundled into bundles BD1 and BD2, respectively. In some embodiments, operation 1704 corresponds to each of the above-described operations OP12, OP23, OP42, and OP53.

[0239] In operation 1706, G-cells are constructed to model the routing resources of the redistribution layer (RDL). Specifically, G-cells are used, and these G-cells are associated with capacity and demand. For example, G-cells 600 are created, and these G-cells 600 are associated with edge capacity and demand. In some embodiments, operation 1706 corresponds to each of the operations OP61, OP71, OP92, OP112, and OP142 described above. In some embodiments, octagonal G-cells are recommended. In other embodiments, polygons other than octagons are used as G-cells, such as dodecagonal G-cells. In other embodiments, mixed irregular G-cells are used.

[0240] In operation 1708, the global routing path of the bundle is optimized. Specifically, the global routing path of the bundle is optimized by iteratively optimizing congestion, showing congestion graphs and global routing reports (such as overflow or violation), wire length (WL), number of vias, and the like. For example, the bundle routes BR1–BR6, BR61–BR62, BR81–BR83, BR91, and BR11 are optimized. In some embodiments, operation 1708 corresponds to each of the operations OP13, OP43, OP44, OP54, OP62, OP72, OP82, OP93, OP101–OP102, OP113, and OP143–OP144 described above.

[0241] In operation 1710, the mesh in the bundle is routed to connect the pins. Specifically, detailed routing reports are generated, such as violations, wL (wireless loops), and the number of through holes. For example, meshes N1 to N7 are routed to generate routes DR1 to DR7 to connect bumps C1 to C7 and balls B1 to B7. In some embodiments, operation 1710 corresponds to each of operations OP14, OP45, OP54, OP81, and OP114. In other embodiments, operation 1710 is optional.

[0242] In operation 1712, violations are corrected. Specifically, physical and electrical violations are corrected, such as spacing violations, skew matching violations, and the like. In some embodiments, operation 1712 is optional.

[0243] In operation 1714, the routing process is completed. Specifically, the database (DB) is output.

[0244] Figure 18 This is a flowchart of a method 1800 for wiring a semiconductor device 100 according to some embodiments of this disclosure. Figure 18As illustrated, method 1800 includes operations 1802, 1804, 1806, 1808, and 1810. In some embodiments, method 1800 is performed to wire the semiconductor device 100 described above.

[0245] In operation 1802, a routing design is prepared. Specifically, the routing design includes data such as die / package size, bumps, balls, components, netlists, layers, obstructions, and a complete or partial set of routing patterns. For example, a routing design containing data (such as circuits CI1, bumps C1-C7, balls B1-B7, nets N1-N7, layers L1-L10, and obstructions BL1-BL3 associated with routing the semiconductor device 100) is prepared. In some embodiments, operation 1802 corresponds to each of operations OP14, OP45, OP54, and OP114 described above.

[0246] Operation 1804 of method 1800 is similar to operation 1706 of method 1700. Therefore, for the sake of brevity, the description of operation 1804 is omitted.

[0247] In operation 1806, wiring paths and obstructions are mapped to G-cells. Specifically, G-cells are associated with capacity and requirements.

[0248] In operation 1808, route feasibility is assessed. Specifically, route feasibility is assessed by displaying congestion diagrams and wiring reports (such as overflow or violations), critical sections, wiring loops (WL), via counts, and the like. In some embodiments, operation 1808 corresponds to each of operations OP72, OP81–OP82, OP93, OP101–OP102, and OP113. For example, network N71–N74 of operation OP72 is assessed. As another example, route feasibility for G units 600A–600F is assessed.

[0249] Operation 1810 of method 1800 is similar to operation 1714 of method 1700. Therefore, for the sake of brevity, the description of operation 1810 is omitted.

[0250] Figure 19 This is a flowchart of a method 1900 for designing the above-described semiconductor device 100 according to some embodiments of this disclosure. Figure 19 As illustrated herein, method 1900 includes operations 1902, 1904, 1906, and 1908.

[0251] In operation 1902, a first bundle path is generated between the plurality of first bumps and the plurality of first spheres. For example, a bundle BR1 is generated between bumps C1-C3 and spheres B1-B3.

[0252] In operation 1904, a first route and a second route are generated that are parallel to each other along the first bundle route. For example, routes DR1 and DR2 are generated that are parallel to each other along bundle route BR1.

[0253] In operation 1906, a first bump among a plurality of first bumps is connected to a first ball among a plurality of first balls via a first route. For example, bump C1 among bumps C1 to C3 is connected to ball B1 among balls B1 to B3 via route DR1.

[0254] In operation 1908, a second bump among a plurality of first bumps is connected to a second ball among a plurality of first balls via a second route. For example, bump C2 among bumps C1 to C3 is connected to ball B2 among balls B1 to B3 via route DR2. In some embodiments, the first route and the second route are separate. For example, route DR1 and route DR2 are separate.

[0255] Figure 20 This is a flowchart of a method 2000 for designing the above-described semiconductor device 100 according to some embodiments of this disclosure. Figure 20 As illustrated herein, method 2000 includes operations 2002, 2004, and 2006.

[0256] In operation 2002, multiple first bumps are assigned in the first cell of multiple first cells. For example, bumps C1 to C3 are assigned in G cell G13 of G cell 600.

[0257] In operation 2004, multiple first balls are assigned to second units within multiple first units. For example, balls B1 to B3 are assigned to G41 within G unit 600.

[0258] In operation 2006, a plurality of first bumps and a plurality of first balls are connected by a first bundle path, which is located between the plurality of first bumps and the plurality of first balls. For example, bumps C1 to C3 and balls B1 to B3 are connected by a bundle path BR91, which is located between bumps C1 to C3 and balls B1 to B3.

[0259] In some embodiments, the first beam path crosses and is perpendicular to each of the first edge of the first unit and the first edge of the second unit. For example, beam path BR91 crosses and is perpendicular to each of the edges of G unit G13 and G unit G41.

[0260] Figure 21This is a block diagram of an electronic design automation (EDA) system 2100 for designing the semiconductor device 100 described above, according to some embodiments of this disclosure. The EDA system 2100 is used to implement one or more operations of the methods described above. In some embodiments, the EDA system 2100 includes an automatic placement and routing (APR) system.

[0261] In some embodiments, the EDA system 2100 is a general-purpose computing device that includes a hardware processor 2120 and a non-transitory computer-readable storage medium 2160. Among other things, the storage medium 2160 is encoded with (i.e., stores) computer program code (instructions) 2161, i.e., an executable instruction set. The instructions 2161, executed by the hardware processor 2120, represent at least partially EDA tools that implement a method (which includes, for example, the methods disclosed above).

[0262] Processor 2120 is electrically coupled to computer-readable storage medium 2160 via bus 2150. Processor 2120 is also electrically coupled to I / O interface 2110 and manufacturing tool 2170 via bus 2150. Network interface 2130 is also electrically connected to processor 2120 via bus 2150. Network interface 2130 is connected to network 2140, and thus processor 2120 and computer-readable storage medium 2160 can be connected to external components via network 2140. Processor 2120 is used to execute computer program code 2161 encoded in computer-readable storage medium 2160 so that EDA system 2100 can be used to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 2120 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0263] In one or more embodiments, the computer-readable storage medium 2160 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 2160 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 2160 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0264] In one or more embodiments, storage medium 2160 stores computer program code 2161 that enables EDA system 2100 (wherein this execution (at least partially) represents an EDA tool) to perform some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 2160 also stores information that facilitates performing some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 2160 stores a standard cell library 2162 that includes such standard cells as disclosed herein.

[0265] In one or more embodiments, storage medium 2160 stores, for example, a layout diagram 2164 corresponding to semiconductor device 100. In one or more embodiments, storage medium 2160 stores a pattern data field 2165.

[0266] In one or more embodiments, storage medium 2160 is memory storing computer program code. The computer program code corresponds to the operations described above and is executed by processor 2120. In one or more embodiments, processor 2120 executes the computer program code in memory to: generate a first bundle path (e.g., bundle path BR1) located between a plurality of first bumps (e.g., bumps C1-C3) and a plurality of first balls (e.g., balls B1-B3); generate a first path (e.g., path DR1) and a second path (e.g., path DR2) arranged parallel to each other along the first bundle path; connect a first bump (e.g., bump C1) of the plurality of first bumps to a first ball (e.g., ball B1) of the plurality of first balls via the first path; and connect a second bump (e.g., bump C2) of the plurality of first bumps to a second ball (e.g., ball B2) of the plurality of first balls via the second path. In some embodiments, the first path and the second path are separate.

[0267] EDA system 2100 includes I / O interface 2110. I / O interface 2110 is coupled to an external circuit system. In one or more embodiments, I / O interface 2110 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or directional keys for transmitting information and commands to processor 2120.

[0268] EDA system 2100 also includes a network interface 2130 coupled to processor 2120. Network interface 2130 allows EDA system 2100 to communicate with network 2140, to which one or more other computer systems are connected. Network interface 2130 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-12164. In one or more embodiments, some or all of the mentioned processes and / or methods (including, for example, the methods described above) are implemented in two or more systems including EDA system 2100.

[0269] The EDA system 2100 also includes a manufacturing tool 2170 coupled to the processor 2120. The manufacturing tool 2170 is used to manufacture chips corresponding to the layout based on design documents processed by the processor 2120 and / or IC layout designs as described above, including, for example, the semiconductor device 100 described above.

[0270] EDA system 2100 receives information via I / O interface 2110. The information received via I / O interface 2110 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 2120. This information is transmitted to processor 2120 via bus 2150. EDA system 2100 also receives UI-related information via I / O interface 2110. This information is stored as a user interface (UI) 2163 in computer-readable medium 2160.

[0271] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by EDA system 2100. In some embodiments, tools (such as those available from Cadence Design Systems, Inc.) are used. Alternatively, another suitable layout generation tool can be used to generate a layout diagram containing standard cells.

[0272] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), and one or more of the like.

[0273] In some embodiments, the routes are implemented using a conductive material, such as metal wires. Bumps and spheres are located in different layers and are electrically connected to each other via routes. The size of the bumps is smaller than the size of the spheres. Global cells (G-cells) are generated using EDA tools. A mesh is a line electrically connecting spheres to bumps. Circuit CI1 is implemented by a central processing unit (CPU). Obstructions are implemented using CPU elements, hardware, barriers, routes, or the like.

[0274] In some approaches, electronic design automation (EDA) routers directly route all nets. However, continuous net-by-net routing often results in poor routing quality. This wastes space in the redistribution layer (RDL). Furthermore, manual routing leads to inefficiency.

[0275] Compared to the above methods, in some embodiments disclosed herein, the bundle path BR1 above G unit 600 is created based on the edge capacity of edges E81 to E83 of G unit 800, thereby generating routes DR1 and DR2 along the bundle path BR1 above G unit 600. Therefore, wiring quality is improved and cycle time is shortened.

[0276] A structure is also disclosed. This structure includes at least one sphere, at least one bump, and at least one path. The at least one path is used to couple the at least one sphere to the at least one bump. The at least one path includes a plurality of first path edges and a plurality of second path edges, and the angle between one of the plurality of first path edges and one of the plurality of second path edges is approximately equal to the angle between another of the plurality of first path edges and another of the plurality of second path edges.

[0277] In some embodiments, at least one route is included in a bundle of routes, and the at least one route comprises only one route for coupling one of at least one sphere to one of at least one bump. In some embodiments, the at least one route comprises: a first route for coupling a first sphere of at least one sphere to a first bump of at least one bump; and a second route for coupling a second sphere of at least one sphere to a second bump of the at least one bump, wherein the first route has a first route edge and a second route edge, the second route has a third route edge and a fourth route edge, and the angle between the first route edge and the second route edge is approximately equal to the angle between the third route edge and the fourth route edge. In some embodiments, the first route further has a fifth route edge, the second route further has a sixth route edge, and the angle between the fifth route edge and the second route edge is approximately equal to the angle between the sixth route edge and the fourth route edge. In some embodiments, the distance between the first route edge and the third route edge is shorter than or close to each of a plurality of widths of the at least one route. In some embodiments, at least one route further includes: a third route for coupling a third ball of at least one ball to a third bump of at least one bump, wherein the third route has a seventh route edge and an eighth route edge, and the angle between the first route edge and the second route edge is approximately equal to the angle between the seventh route edge and the eighth route edge. In some embodiments, the second route further has a ninth route edge opposite to the third route edge, and the distance between the ninth route edge and the seventh route edge is shorter than or close to each of a plurality of widths of the at least one route.

[0278] A method is also disclosed. This method includes: forming a plurality of spheres; forming a wiring layer above the plurality of spheres; and forming a plurality of bumps above the wiring layer. Forming the wiring layer includes: forming a plurality of routes that couple the plurality of spheres to the plurality of bumps. The angles of the plurality of routes are approximately equal to each other.

[0279] In some embodiments, the step of forming a route includes the steps of: forming a first route coupling a first ball in a sphere to a first bump in a bump; and forming a second route coupling a second ball in a sphere to a second bump in a bump, wherein the first route has a first route edge and a second route edge, the second route has a third route edge and a fourth route edge, and the angle between the first route edge and the second route edge is approximately equal to the angle between the third route edge and the fourth route edge. In some embodiments, the step of forming a route further includes the step of: forming a third route coupling a third ball in a sphere to a third bump in a bump, wherein the second route further has a fifth route edge and a sixth route edge, the third route has a seventh route edge and an eighth route edge, and the angle between the fifth route edge and the sixth route edge is approximately equal to the angle between the seventh route edge and the eighth route edge. In some embodiments, the distance between the first route edge and the third route edge is shorter than or close to each of a plurality of route widths.

[0280] A system is also disclosed. This system includes memory and a processor. The memory stores computer program code. The processor executes the computer program code in the memory to: generate a first bundle of routes located between a plurality of first bumps and a plurality of first spheres; generate a first route and a second route arranged parallel to each other along the first bundle of routes; connect the first bumps of the plurality of first bumps to the first spheres of the plurality of first spheres via the first route; and connect the second bumps of the plurality of first bumps to the second spheres of the plurality of first spheres via the second route. The first route and the second route are separate.

[0281] Also disclosed is a semiconductor structure including: a plurality of spheres; a wiring layer above the spheres; and a plurality of bumps above the wiring layer, wherein the wiring layer includes: a plurality of routes for coupling the spheres to the bumps, and wherein a plurality of angles of the routes are equal to each other.

[0282] In some embodiments, the route includes: a first route that couples a first ball in the ball to a first bump in the bump; and a second route that couples a second ball in the ball to a second bump in the bump, wherein the first route has a first route edge and a second route edge, the second route has a third route edge and a fourth route edge, and the angle between the first route edge and the second route edge is equal to the angle between the third route edge and the fourth route edge.

[0283] The invention also discloses a semiconductor structure comprising: a plurality of first bumps; a plurality of first balls; a first beam path for coupling the plurality of first bumps to the plurality of first balls; and a first path and a second path arranged parallel to each other with the first beam path; wherein a first bump in the first bumps is connected to a first ball in the first balls via the first path; a second bump in the first bumps is connected to a second ball in the first balls via the second path; and the first path is separated from the second path.

[0284] In some embodiments, the processor is further configured to assign a first bump to a first unit among a plurality of first units, and further configured to assign a first route to a first edge of a first unit when the edge capacity of a first edge of a first unit is greater than or equal to the number of multiple nets required by a first route. In some embodiments, the edge capacity of a first edge is calculated based on each of the length of the first edge, the width of the first route, and the space between the first route and the second route. In some embodiments, the processor is further configured to assign a first route to a first edge of at least one first unit and a first edge of a second unit adjacent to the first unit when the number of multiple nets required by the first route is greater than the edge capacity of the first edge of the first unit. In some embodiments, the processor is further configured to generate a congestion graph with a plurality of global units, and the congestion graph illustrates and evaluates route feasibility. In some embodiments, the global units are octagonal in shape for route planning at 0 degrees, 45 degrees, 90 degrees, and 135 degrees. In some embodiments, the global units have a flexible polygonal style. In some embodiments, the global units have a multi-layered structure. In some embodiments, overflow information is shown in the congestion graph when the route demand is greater than or equal to the edge capacity of the global unit.

[0285] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or improving other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized by, include: At least one ball; At least one bump; and At least one route is provided for coupling the at least one sphere to the at least one bump. The at least one route includes multiple first route edges and multiple second route edges, and An angle between one of the multiple first route edges and one of the multiple second route edges is equal to an angle between another of the multiple first route edges and another of the multiple second route edges.

2. The semiconductor structure of claim 1, wherein, At least one of the routes is contained in a bundle of routes. The at least one route includes only one route, and This route is used to couple one of the at least one sphere to one of the at least one bump.

3. The semiconductor structure of claim 1, wherein, At least one of the routes includes: A first route for coupling a first ball of the at least one ball to a first bump of the at least one bump; and A second route is used to couple a second ball of the at least one ball to a second bump of the at least one bump. The first route has a first route edge and a second route edge. The second route has a third route edge and a fourth route edge, and The angle between the edge of the first route and the edge of the second route is equal to the angle between the edge of the third route and the edge of the fourth route.

4. The semiconductor structure of claim 3, wherein, in The first route further has a fifth route edge. The second route further has a sixth route edge, and The angle between the edge of the fifth route and the edge of the second route is equal to the angle between the edge of the sixth route and the edge of the fourth route.

5. The semiconductor structure of claim 3, wherein, The distance between the edge of the first route and the edge of the third route is shorter than or equal to each of the multiple widths of the at least one route.

6. The semiconductor structure of claim 3, wherein, The at least one of these routes further includes: A third route is used to couple a third ball of the at least one ball to a third bump of the at least one bump. The third route has an edge of a seventh route and an edge of an eighth route, and The angle between the edge of the first route and the edge of the second route is equal to the angle between the edge of the seventh route and the edge of the eighth route.

7. The semiconductor structure of claim 6, wherein, The second route further has a ninth route edge opposite to the edge of the third route, and The distance between the edge of the ninth route and the edge of the seventh route is shorter than or equal to each of the multiple widths of the at least one route.

8. A semiconductor structure, characterized by include: Multiple balls; A wiring layer located above the plurality of spheres; and Multiple bumps located above the wiring layer, The wiring layer includes: Multiple routes are used to couple the plurality of balls to the plurality of bumps, and The multiple angles of the multiple routes are equal to each other.

9. The semiconductor structure of claim 8, wherein, The multiple routes mentioned above include: A first route, coupling a first ball of the plurality of balls to a first bump of the plurality of bumps; and A second route couples a second ball from the plurality of balls to a second bump from the plurality of bumps. The first route has a first route edge and a second route edge. The second route has a third route edge and a fourth route edge, and The angle between the edge of the first route and the edge of the second route is equal to the angle between the edge of the third route and the edge of the fourth route.

10. A semiconductor structure, characterized by include: Multiple first bumps; Multiple first goals; A first bundle of routes is used to couple multiple first bumps to multiple first spheres; as well as A first route and a second route configured parallel to each other in the first bundle route; Wherein, one of the plurality of first protrusions is connected to one of the plurality of first balls through the first route; A second protrusion among the plurality of first protrusions is connected to a second sphere among the plurality of first spheres via the second route; and The first route is separated from the second route.

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