A temperature-independent constant current source
By canceling out the positive and negative temperature currents, the complexity and small operating voltage range of traditional constant current source circuits are solved, achieving temperature-independent constant current output, simplifying the circuit structure and expanding the applicable environment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI XINYAN MICROELECTRONICS CO LTD
- Filing Date
- 2025-08-22
- Publication Date
- 2026-07-07
AI Technical Summary
Traditional constant current source circuits have complex structures, resulting in large circuit areas, high costs, small operating voltage ranges, and limited applicable environments.
The circuit employs both positive and negative temperature current generation circuits, and uses a current summation circuit to cancel out the temperature coefficients of the two circuits, outputting a constant current. The circuit is implemented using bipolar or field-effect transistors and consists of transistors, field-effect transistors, resistors, and current mirrors.
It achieves constant current output unaffected by temperature over a wide temperature range, simplifies the circuit structure, and expands the operating voltage range.
Smart Images
Figure CN224471987U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of constant current source technology, specifically to a temperature-independent constant current source. Background Technology
[0002] Constant current sources play a crucial role in modern electronic systems, and their importance in on-chip systems is increasingly prominent. Traditional constant current source circuits inevitably result in complex circuit structures, requiring larger circuit areas to implement the function, thus increasing costs. Furthermore, the operating voltage requirements of amplifiers limit the operating voltage range of constant current source circuits, resulting in a narrow operating voltage range and a limited range of applicable environments. Utility Model Content
[0003] To help solve the above-mentioned technical problems, this application provides a temperature-independent constant current source, adopting the following technical solution:
[0004] A temperature-independent constant current source, comprising:
[0005] A positive temperature coefficient current generating circuit is used to generate a first current with a positive temperature coefficient. It includes a first branch, a second branch, and a first resistor. The first branch and the second branch have an asymmetrical structure. The current flowing through the first branch and the second branch generates a voltage difference in the first resistor that is proportional to the temperature, so as to generate the first current.
[0006] A negative temperature current generating circuit is used to generate a second current with a negative temperature coefficient. It includes a transistor or field-effect transistor and a second resistor. The emitter-base voltage or gate-source voltage of the transistor or field-effect transistor is applied to the second resistor to generate the second current.
[0007] The current summing circuit is used to superimpose a first current and a second current in a mirror ratio so that the positive temperature coefficient of the first current and the negative temperature coefficient of the second current cancel each other out, thereby outputting a constant current. The current summing circuit includes a first current mirror and a second current mirror. The first current mirror is used to mirror the first current or a scaled current of the first current, and the second current mirror is used to mirror the second current or a scaled current of the second current. The output current is the sum of the first current and the second current in a mirror ratio.
[0008] Preferably, it also includes a startup circuit, which includes a third resistor, an NMOS transistor MN7, and an NMOS transistor MN15. One end of the third resistor is connected to the power supply voltage, and the other end is connected to the drain of the NMOS transistor MN15 and the gate of the NMOS transistor MN7. The drain of the NMOS transistor MN7 is connected to the positive temperature current circuit, and the source is grounded. The gate of the NMOS transistor MN15 is connected to the positive temperature current circuit, and the source is grounded.
[0009] Preferably, the positive temperature current generation circuit, the negative temperature current generation circuit, and the current summing circuit are implemented using bipolar transistors:
[0010] The positive temperature current generation circuit includes transistors NPN1 and NPN2, a first resistor R1, PMOS transistors MP8 and MP9. The base of transistor NPN1 is connected to the drain of PMOS transistor MP8, and the collector is connected to the base of transistor NPN2. It is connected to a current summing circuit through the first resistor R1, and the emitter is grounded. The collector of transistor NPN2 is connected to the drain of PMOS transistor MP9, and the emitter is grounded. The gates of PMOS transistors MP8 and MP9 are interconnected, and the source is connected to the power supply voltage. The gate of PMOS transistor MP9 is connected to the drain of PMOS transistor MP9. Based on the emitter areas of transistors NPN1 and NPN2, an asymmetric structure is formed for the first and second branches.
[0011] The current summing circuit includes a first current mirror composed of transistors NPN1 and NPN3, and a second current mirror composed of NMOS transistors MN5 and MN4. The output transistor is a PMOS transistor MP10. The gate of PMOS transistor MP10 is connected to the drain of PMOS transistor MP10, and the source is connected to the power supply voltage. The drain of PMOS transistor MP10 is connected to the collector of transistor NPN3 and the drain of NMOS transistor MN4. The emitter of transistor NPN3 and the source of NMOS transistor MN4 are grounded. The gate of NMOS transistor MN4 is connected to the negative temperature current generation circuit.
[0012] The negative temperature current generation circuit includes PMOS transistors MP11, MP12, MP13, MP14, NMOS transistor MN5, NPN6, and a second resistor R2. The gate and drain of PMOS transistor MP11 are interconnected, and its source is connected to the power supply voltage. The drain of PMOS transistor MP12 is connected to the collector of NPN6, and its source is connected to the power supply voltage. Its gate is connected to the gate of PMOS transistor MP10. The gate of PMOS transistor MP13 is connected to the gate of PMOS transistor MP11, and its drain is grounded through the second resistor R2. Its source is connected to the power supply voltage. The gate of PMOS transistor MP14 is connected to the gate of PMOS transistor MP10, and its source is connected to the power supply voltage. The collector of NPN6 is connected to the gate of NMOS transistor MN4.
[0013] Preferably, the emitter area ratio of transistor NPN1 to transistor NPN2 is n:1, where n>1.
[0014] Preferably, the positive temperature current generation circuit, the negative temperature current generation circuit, and the current summing circuit are implemented using field-effect transistors:
[0015] The positive temperature current generation circuit includes NMOS transistors MN1 and MN2, a first resistor R1, PMOS transistors MP8 and MP9. The gate of NMOS transistor MN1 is connected to the drain of PMOS transistor MP8, and the drain is connected to the gate of transistor NPN2. It is connected to a current summing circuit through the first resistor R1, and the source is grounded. The drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP9, and the source is grounded. The gates of PMOS transistors MP8 and MP9 are interconnected, and the source is connected to the power supply voltage. The gate of PMOS transistor MP9 is connected to the drain of PMOS transistor MP9. Based on the width-to-length ratio of NMOS transistors MN1 and MN2, an asymmetrical first branch and a second branch are formed.
[0016] The current summing circuit includes a first current mirror composed of NMOS transistors MN1 and MN2, and a second current mirror composed of NMOS transistors MN5 and MN4. The output transistor is a PMOS transistor MP10. The gate of the PMOS transistor MP10 is connected to the drain of the PMOS transistor MP10, and the source is connected to the power supply voltage. The drain of the PMOS transistor MP10 is connected to the drain of NMOS transistors MN3 and MN4. The sources of NMOS transistors MN3 and MN4 are grounded. The gate of NMOS transistor MN4 is connected to the negative temperature current generation circuit.
[0017] The negative temperature current generation circuit includes PMOS transistors MP11, MP12, MP13, MP14, NMOS transistors MN5 and MN6, and a second resistor R2. The gate and drain of PMOS transistor MP11 are interconnected, and the source is connected to the power supply voltage. The drain of PMOS transistor MP12 is connected to the drain of NMOS transistor MN6, and the source is connected to the power supply voltage. The gate of MP12 is connected to the gate of PMOS transistor MP10. The gate of PMOS transistor MP13 is connected to the gate of PMOS transistor MP11, and the drain is grounded through the second resistor R2. The source is connected to the power supply voltage. The gate of PMOS transistor MP14 is connected to the gate of PMOS transistor MP10, and the source is connected to the power supply voltage. The drain of NMOS transistor MN6 is connected to the gate of NMOS transistor MN4.
[0018] Preferably, in the positive temperature current circuit, the temperature coefficient of the first current I1 is: Where k is Boltzmann's constant, q is the electron charge, n is the saturation current ratio of transistors NPN1 and NPN2, R1 is the resistance of the first resistor, and T is the temperature.
[0019] Preferably, in the current summing circuit, the temperature coefficient of the output current I4 is satisfied by adjusting the mirror ratios a and b.
[0020] .
[0021] In summary, the temperature-independent constant current source of this application is applied in environments where the current does not change with temperature. It is connected in series with the device to which the current is supplied, and can provide it with a constant current input that is not affected by temperature. The overall circuit structure is simple and the application conditions are wide. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of the structure of a first embodiment of a temperature-independent constant current source according to this application;
[0023] Figure 2 for Figure 1 A schematic diagram of the positive temperature current generation circuit in the embodiment shown;
[0024] Figure 3 for Figure 1 A schematic diagram of the negative temperature current generation circuit in the embodiment shown.
[0025] Figure 4 for Figure 1 A schematic diagram of the current summation circuit in the illustrated embodiment;
[0026] Figure 5 for Figure 1 A schematic diagram of the startup circuit in the illustrated embodiment;
[0027] Figure 6 This is a schematic diagram of the structure of a second embodiment of a temperature-independent constant current source according to this application. Detailed Implementation
[0028] The present application will be further described below with reference to the accompanying drawings. The structure and principle of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
[0029] The constant current source in this application includes:
[0030] A positive temperature coefficient current generating circuit is used to generate a first current with a positive temperature coefficient. It includes a first branch, a second branch, and a first resistor. The first branch and the second branch have an asymmetrical structure. The current flowing through the first branch and the second branch generates a voltage difference in the first resistor that is proportional to the temperature, so as to generate the first current.
[0031] A negative temperature current generating circuit is used to generate a second current with a negative temperature coefficient. It includes a transistor or field-effect transistor and a second resistor. The emitter-base voltage or gate-source voltage of the transistor or field-effect transistor is applied to the second resistor to generate the second current.
[0032] The current summing circuit is used to superimpose a first current and a second current in a mirror ratio so that the positive temperature coefficient of the first current and the negative temperature coefficient of the second current cancel each other out, thereby outputting a constant current. The current summing circuit includes a first current mirror and a second current mirror. The first current mirror is used to mirror the first current or a scaled current of the first current, and the second current mirror is used to mirror the second current or a scaled current of the second current. The output current is the sum of the first current and the second current in a mirror ratio.
[0033] The startup circuit includes a third resistor, NMOS transistors MN7 and MN15. One end of the third resistor is connected to the power supply voltage, and the other end is connected to the drain of NMOS transistor MN15 and the gate of NMOS transistor MN7. The drain of NMOS transistor MN7 is connected to the positive temperature current circuit, and its source is grounded. The gate of NMOS transistor MN15 is connected to the positive temperature current circuit, and its source is grounded.
[0034] like Figure 1 In the illustrated embodiment, the positive temperature current generation circuit, the negative temperature current generation circuit, and the current summing circuit are implemented using bipolar transistors:
[0035] The positive temperature current generation circuit includes transistors NPN1 and NPN2, a first resistor R1, PMOS transistors MP8 and MP9. The base of transistor NPN1 is connected to the drain of PMOS transistor MP8, and the collector is connected to the base of transistor NPN2. It is connected to a current summing circuit through the first resistor R1, and the emitter is grounded. The collector of transistor NPN2 is connected to the drain of PMOS transistor MP9, and the emitter is grounded. The gates of PMOS transistors MP8 and MP9 are interconnected, and the source is connected to the power supply voltage. The gate of PMOS transistor MP9 is connected to the drain of PMOS transistor MP9. Based on the emitter areas of transistors NPN1 and NPN2, an asymmetric structure is formed for the first and second branches.
[0036] The current summing circuit includes a first current mirror composed of transistors NPN1 and NPN3, and a second current mirror composed of NMOS transistors MN5 and MN4. The output transistor is a PMOS transistor MP10. The gate of PMOS transistor MP10 is connected to the drain of PMOS transistor MP10, and the source is connected to the power supply voltage. The drain of PMOS transistor MP10 is connected to the collector of transistor NPN3 and the drain of NMOS transistor MN4. The emitter of transistor NPN3 and the source of NMOS transistor MN4 are grounded. The gate of NMOS transistor MN4 is connected to the negative temperature current generation circuit.
[0037] The negative temperature current generation circuit includes PMOS transistors MP11, MP12, MP13, MP14, NMOS transistor MN5, NPN6, and a second resistor R2. The gate and drain of PMOS transistor MP11 are interconnected, and its source is connected to the power supply voltage. The drain of PMOS transistor MP12 is connected to the collector of NPN6, and its source is connected to the power supply voltage. Its gate is connected to the gate of PMOS transistor MP10. The gate of PMOS transistor MP13 is connected to the gate of PMOS transistor MP11, and its drain is grounded through the second resistor R2. Its source is connected to the power supply voltage. The gate of PMOS transistor MP14 is connected to the gate of PMOS transistor MP10, and its source is connected to the power supply voltage. The collector of NPN6 is connected to the gate of NMOS transistor MN4.
[0038] In this embodiment, the emitter area ratio of transistor NPN1 to transistor NPN2 is n:1, where n>1.
[0039] Positive temperature coefficient current generation: Positive temperature coefficient current generation circuit, such as... Figure 2 As shown in the figure, MP8 and MP9 have the same W / L, i.e., I1=I2. For npn transistors, the emitter-base voltage and collector current have the following relationship:
[0040] ,
[0041] Where Vbe represents the voltage between the emitter and base, Ic is the collector current, and Is represents the saturation current. Vt represents the thermal voltage, and its relationship with temperature is as follows.
[0042] ,
[0043] k is Boltzmann's constant, T is Kelvin temperature, and q represents the elementary charge of the electron.
[0044] The voltage drop V1 across resistor R1 is expressed as:
[0045] ,
[0046] Where n represents the ratio of the currents of Is1 to Is2.
[0047] The current through R1 is expressed as:
[0048] ,
[0049] Therefore, the temperature characteristic of current I1 is:
[0050] ,
[0051] in, ,
[0052] so, ,
[0053] This shows that the temperature characteristic of current I1 is positive temperature, and the current I1 gradually increases as the temperature increases.
[0054] Negative temperature coefficient current generation: Negative temperature coefficient current generation circuit as follows Figure 3 As shown.
[0055] The operating mode is as follows: Current I6 is supplied externally. MP11 and MP13 form a current mirror, and MN5-MP11-MP13-NPN6 form a feedback loop. The feedback works as follows: when the gate voltage of MN5 increases, the gate voltage of MP11 decreases. The decrease in the gate voltage of MP11 increases the voltage drop across R2. The increased voltage drop across R2 decreases the collector voltage of NPN6, which in turn decreases the gate voltage of MN5. This forms negative feedback to stabilize the circuit. Current I7 is the generated negative temperature current.
[0056] The value of current I7 is expressed as:
[0057] ,
[0058] ,
[0059] Where Eg represents the band gap energy of silicon.
[0060] Therefore, the temperature characteristic of current I7 can be expressed as:
[0061] ,
[0062] Under normal temperature conditions ,
[0063] Therefore, the temperature characteristics of I7 at room temperature with low current are:
[0064] ,
[0065] It can be seen that the temperature characteristic of current I7 is negative; as the temperature increases, the current gradually decreases.
[0066] Current summation circuit: Current summation circuit as follows Figure 4 As shown. NPN1 and NPN3 form a current mirror, which mirrors the current in NPN1 to NPN3 proportionally. MN5 and MN4 also form a current mirror, which mirrors the current in MN5 to MN4 proportionally. Now assume that the mirror ratio of the current mirrors NPN1 and NPN3 is 1:a, and the mirror ratio of the current mirror formed by MN5 and MN4 is 1:b. The current I4 in MP10 is equal to the sum of the currents in NPN3 and MN4.
[0067] ,
[0068] The temperature characteristic of current I4 is expressed as follows:
[0069] ,
[0070] We know that at room temperature , ,
[0071] If we choose Then it can be set This will give you a current I4 with zero temperature coefficient. The above parameter settings are just examples; there are other combinations in actual applications.
[0072] In this embodiment of the application, the temperature coefficient of the first current I1 in the positive temperature current circuit is: Where k is Boltzmann's constant, q is the electron charge, n is the saturation current ratio of transistors NPN1 and NPN2, R1 is the resistance of the first resistor, and T is the temperature.
[0073] In the current summing circuit, by adjusting the mirror ratios a and b, the temperature coefficient of the output current I4 is made to satisfy:
[0074] .
[0075] In a negative temperature current circuit, the temperature coefficient of the second current I7 is approximately:
[0076] .
[0077] Start-up circuit: The start-up circuit is as follows Figure 5 As shown, the temperature-dependent current generation section has a degeneracy point, i.e., current I1 = I2 = 0. The startup circuit pushes the circuit away from the degeneracy point and into a stable operating state. The working principle is as follows: as the power supply voltage rises, the drain voltage of MN15 rises, and the gate voltage of MN7 also rises accordingly. When the power supply voltage is greater than Vth, MN7 enters the conducting state, and MP9 and MN7 form a path between the power supply and ground. A current I2 is then generated in MP9, and this current I2 is mirrored to MP8. After MP8 enters the conducting state, the drain voltage of MN1 rises, and the gate potentials of MN2 and MN15 also rise accordingly. When Vgs15 of MN15 is greater than Vth, MN15 conducts. As the power supply voltage increases, the voltage drop across R3 will increase rapidly. When the difference between the power supply voltage VDD and the voltage drop across R3 is less than Vth, MN7 turns off, and the point where current I1 = I2 = 0 is not allowed to exist; therefore, the degeneracy point is eliminated. The circuit has only one stable point, which is the point required for normal operation.
[0078] like Figure 6 In the embodiment shown, the positive temperature current generation circuit, the negative temperature current generation circuit, and the current summing circuit are implemented using field-effect transistors:
[0079] The positive temperature current generation circuit includes NMOS transistors MN1 and MN2, a first resistor R1, PMOS transistors MP8 and MP9. The gate of NMOS transistor MN1 is connected to the drain of PMOS transistor MP8, and the drain is connected to the gate of transistor NPN2. It is connected to a current summing circuit through the first resistor R1, and the source is grounded. The drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP9, and the source is grounded. The gates of PMOS transistors MP8 and MP9 are interconnected, and the source is connected to the power supply voltage. The gate of PMOS transistor MP9 is connected to the drain of PMOS transistor MP9. Based on the width-to-length ratio of NMOS transistors MN1 and MN2, an asymmetrical first branch and a second branch are formed.
[0080] The current summing circuit includes a first current mirror composed of NMOS transistors MN1 and MN2, and a second current mirror composed of NMOS transistors MN5 and MN4. The output transistor is a PMOS transistor MP10. The gate of the PMOS transistor MP10 is connected to the drain of the PMOS transistor MP10, and the source is connected to the power supply voltage. The drain of the PMOS transistor MP10 is connected to the drain of NMOS transistors MN3 and MN4. The sources of NMOS transistors MN3 and MN4 are grounded. The gate of NMOS transistor MN4 is connected to the negative temperature current generation circuit.
[0081] The negative temperature current generation circuit includes PMOS transistors MP11, MP12, MP13, MP14, NMOS transistors MN5 and MN6, and a second resistor R2. The gate and drain of PMOS transistor MP11 are interconnected, and the source is connected to the power supply voltage. The drain of PMOS transistor MP12 is connected to the drain of NMOS transistor MN6, and the source is connected to the power supply voltage. The gate of MP12 is connected to the gate of PMOS transistor MP10. The gate of PMOS transistor MP13 is connected to the gate of PMOS transistor MP11, and the drain is grounded through the second resistor R2. The source is connected to the power supply voltage. The gate of PMOS transistor MP14 is connected to the gate of PMOS transistor MP10, and the source is connected to the power supply voltage. The drain of NMOS transistor MN6 is connected to the gate of NMOS transistor MN4.
[0082] The ratio of the Vgs difference between MN1 and MN2 to R1 in the diagram generates a current that is positively correlated with temperature. The ratio of the voltage difference between the gate and source of MN6 to R2 generates a current that is negatively correlated with temperature. Current mirrors formed by MN1 and MN3, and MN5 and MN4, add these two currents with different temperature coefficients in a specific ratio to cancel out the current change caused by temperature. This results in a temperature-independent current I4. This current I4 is then mirrored by current mirrors MP0 and MP14 to become the output current Iref. This output current Iref is independent of both temperature and voltage.
[0083] In this embodiment, resistors R1 and R2 are polysilicon resistors of the same type, with matched temperature characteristics. The constant current source has an output current change rate of less than ±1% in the temperature range of -40℃ to 125℃.
Claims
1. A temperature-independent constant current source, characterized in that, include: A positive temperature coefficient current generating circuit is used to generate a first current with a positive temperature coefficient. It includes a first branch, a second branch, and a first resistor. The first branch and the second branch have an asymmetrical structure. The current flowing through the first branch and the second branch generates a voltage difference in the first resistor that is proportional to the temperature, so as to generate the first current. A negative temperature current generating circuit for generating a second current with a negative temperature coefficient includes a transistor or field-effect transistor and a second resistor. The emitter-base voltage or gate-source voltage of the transistor or field-effect transistor is applied to the second resistor to generate the second current. The current summing circuit is used to superimpose a first current and a second current in a mirror ratio so that the positive temperature coefficient of the first current and the negative temperature coefficient of the second current cancel each other out, thereby outputting a constant current. The current summing circuit includes a first current mirror and a second current mirror. The first current mirror is used to mirror the first current or a scaled current of the first current, and the second current mirror is used to mirror the second current or a scaled current of the second current. The output current is the sum of the first current and the second current in a mirror ratio.
2. The temperature-independent constant current source according to claim 1, characterized in that, It also includes a startup circuit, which includes a third resistor, NMOS transistor MN7 and NMOS transistor MN15. One end of the third resistor is connected to the power supply voltage, and the other end is connected to the drain of NMOS transistor MN15 and the gate of NMOS transistor MN7. The drain of NMOS transistor MN7 is connected to the positive temperature current circuit, and the source is grounded. The gate of NMOS transistor MN15 is connected to the positive temperature current circuit, and the source is grounded.
3. The temperature-independent constant current source according to claim 1 or 2, characterized in that, The positive temperature current generation circuit, the negative temperature current generation circuit, and the current summing circuit are implemented using bipolar transistors: The positive temperature current generation circuit includes transistors NPN1 and NPN2, a first resistor R1, PMOS transistors MP8 and MP9. The base of transistor NPN1 is connected to the drain of PMOS transistor MP8, and the collector is connected to the base of transistor NPN2. It is connected to a current summing circuit through the first resistor R1, and the emitter is grounded. The collector of transistor NPN2 is connected to the drain of PMOS transistor MP9, and the emitter is grounded. The gates of PMOS transistors MP8 and MP9 are interconnected, and the source is connected to the power supply voltage. The gate of PMOS transistor MP9 is connected to the drain of PMOS transistor MP9. Based on the emitter areas of transistors NPN1 and NPN2, an asymmetric structure is formed for the first and second branches. The current summing circuit includes a first current mirror composed of transistors NPN1 and NPN3, and a second current mirror composed of NMOS transistors MN5 and MN4. The output transistor is a PMOS transistor MP10. The gate of PMOS transistor MP10 is connected to the drain of PMOS transistor MP10, and the source is connected to the power supply voltage. The drain of PMOS transistor MP10 is connected to the collector of transistor NPN3 and the drain of NMOS transistor MN4. The emitter of transistor NPN3 and the source of NMOS transistor MN4 are grounded. The gate of NMOS transistor MN4 is connected to the negative temperature current generation circuit. The negative temperature current generation circuit includes PMOS transistors MP11, MP12, MP13, MP14, NMOS transistor MN5, NPN6, and a second resistor R2. The gate and drain of PMOS transistor MP11 are interconnected, and its source is connected to the power supply voltage. The drain of PMOS transistor MP12 is connected to the collector of NPN6, and its source is connected to the power supply voltage. Its gate is connected to the gate of PMOS transistor MP10. The gate of PMOS transistor MP13 is connected to the gate of PMOS transistor MP11, and its drain is grounded through the second resistor R2. Its source is connected to the power supply voltage. The gate of PMOS transistor MP14 is connected to the gate of PMOS transistor MP10, and its source is connected to the power supply voltage. The collector of NPN6 is connected to the gate of NMOS transistor MN4.
4. The temperature-independent constant current source according to claim 3, characterized in that, The emitter area ratio of transistor NPN1 to transistor NPN2 is n:1, where n>1.
5. The temperature-independent constant current source according to claim 2, characterized in that, The positive temperature current generation circuit, the negative temperature current generation circuit, and the current summing circuit are implemented using field-effect transistors: The positive temperature current generation circuit includes NMOS transistors MN1 and MN2, a first resistor R1, PMOS transistors MP8 and MP9. The gate of NMOS transistor MN1 is connected to the drain of PMOS transistor MP8, and the drain is connected to the gate of transistor NPN2. It is connected to a current summing circuit through the first resistor R1, and the source is grounded. The drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP9, and the source is grounded. The gates of PMOS transistors MP8 and MP9 are interconnected, and the source is connected to the power supply voltage. The gate of PMOS transistor MP9 is connected to the drain of PMOS transistor MP9. Based on the width-to-length ratio of NMOS transistors MN1 and MN2, an asymmetrical first branch and a second branch are formed. The current summing circuit includes a first current mirror composed of NMOS transistors MN1 and MN2, and a second current mirror composed of NMOS transistors MN5 and MN4. The output transistor is a PMOS transistor MP10. The gate of the PMOS transistor MP10 is connected to the drain of the PMOS transistor MP10, and the source is connected to the power supply voltage. The drain of the PMOS transistor MP10 is connected to the drain of NMOS transistors MN3 and MN4. The sources of NMOS transistors MN3 and MN4 are grounded. The gate of NMOS transistor MN4 is connected to the negative temperature current generation circuit. The negative temperature current generation circuit includes PMOS transistors MP11, MP12, MP13, MP14, NMOS transistors MN5 and MN6, and a second resistor R2. The gate and drain of PMOS transistor MP11 are interconnected, and the source is connected to the power supply voltage. The drain of PMOS transistor MP12 is connected to the drain of NMOS transistor MN6, and the source is connected to the power supply voltage. The gate of MP12 is connected to the gate of PMOS transistor MP10. The gate of PMOS transistor MP13 is connected to the gate of PMOS transistor MP11, and the drain is grounded through the second resistor R2. The source is connected to the power supply voltage. The gate of PMOS transistor MP14 is connected to the gate of PMOS transistor MP10, and the source is connected to the power supply voltage. The drain of NMOS transistor MN6 is connected to the gate of NMOS transistor MN4.
6. The temperature-independent constant current source according to claim 2, characterized in that, In the positive temperature current circuit, the temperature coefficient of the first current I1 is: Where k is Boltzmann's constant, q is the electron charge, n is the saturation current ratio of transistors NPN1 and NPN2, R1 is the resistance of the first resistor, and T is the temperature.
7. The temperature-independent constant current source according to claim 1, characterized in that, In the current summing circuit, the temperature coefficient of the output current I4 is satisfied by adjusting the mirror ratios a and b: 。