Modulation signal generating apparatus and terminal device
By using a single interface to control two modulation units in the modulation signal generation device, and utilizing the level control of the frame synchronization clock and bit clock signals, the problems of interface latency and hardware cost are solved, thereby achieving miniaturization and cost reduction of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HYTERA COMM CORP
- Filing Date
- 2025-06-04
- Publication Date
- 2026-07-07
AI Technical Summary
The latency uncertainty between different interfaces and the increased hardware cost caused by multiple interface settings affect the competitiveness of modulation signal generation devices in the miniaturization and thinness market.
The first and second modulation units are controlled by a single interface. Modulation data is transmitted during different level periods by controlling the levels of the frame synchronization clock signal and the bit clock signal, thereby reducing the use of interfaces and reducing the complexity of the control unit.
This approach reduces hardware costs and size without increasing the number of interfaces, while improving the real-time performance and market competitiveness of the modulation signal generation device.
Smart Images
Figure CN224473327U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to modulation signal generation apparatus and terminal equipment. Background Technology
[0002] Modulation technology is a process of converting signals generated by a source into a form suitable for wireless transmission. Modulation technologies include analog modulation and digital modulation. Common analog or digital modulation includes two-point modulation, which typically refers to using different interfaces to modulate different chips or devices separately, thereby generating modulated signals.
[0003] However, due to manufacturing processes and other factors, different interfaces typically exhibit time delays, which are often unpredictable and unsuitable for applications requiring high real-time performance. The use of multiple interfaces increases the size of the chip or device, thereby raising hardware costs and putting the device at a disadvantage in the miniaturized and thinner market, resulting in weak market competitiveness. Utility Model Content
[0004] This application provides a modulation signal generating apparatus and a terminal device. The modulation signal generating apparatus can control the first modulation unit and the second modulation unit using only one interface. Compared with the related technologies that use multiple interfaces to control different units separately, the modulation signal generating apparatus of this application can reduce the use of interfaces. The reduction of interfaces can reduce the complexity of the control unit, reduce the size of the control unit and the modulation signal generating apparatus, and thus reduce hardware costs.
[0005] To address the aforementioned technical problems, this application provides a modulation signal generating apparatus, which includes a control unit, a first modulation unit, and a second modulation unit. The first and second modulation units are coupled to the same set of interfaces of the control unit, and the control unit is configured to transmit corresponding modulation data to the first and second modulation units through these interfaces.
[0006] In some embodiments, the interface includes a first interface pin, a second interface pin, and a third interface pin.
[0007] The first interface pin is coupled to the first modulation unit and the second modulation unit respectively, and the first interface pin is configured to transmit frame synchronization clock signals to the first modulation unit and the second modulation unit.
[0008] The second interface pin is coupled to the first modulation unit and the second modulation unit respectively, and the second interface pin is configured to transmit bit clock signals to the first modulation unit and the second modulation unit.
[0009] The third interface pin is coupled to the first modulation unit and the second modulation unit respectively. The third interface pin is configured to transmit first modulation data to the first modulation unit during the low level of the frame synchronization clock signal; and to transmit second modulation data to the second modulation unit during the high level of the frame synchronization clock signal.
[0010] In some embodiments, the interface includes a first interface pin, a second interface pin, a third interface pin, and a fourth interface pin.
[0011] The first interface pin is coupled to the first modulation unit and the second modulation unit respectively, and the first interface pin is configured to transmit frame synchronization clock signals to the first modulation unit and the second modulation unit.
[0012] The second interface pin is coupled to the first modulation unit and the second modulation unit respectively, and the second interface pin is configured to transmit bit clock signals to the first modulation unit and the second modulation unit.
[0013] The third interface pin is coupled to the first modulation unit, and the third interface pin is configured to transmit the first modulation data to the first modulation unit within the clock cycle of the frame synchronization clock signal.
[0014] The fourth interface pin is coupled to the second modulation unit and is configured to transmit the second modulation data to the second modulation unit during the clock cycle of the frame synchronization clock signal.
[0015] In some embodiments, the interface is an I2S interface or an MCBSP interface, and / or, the first modulation unit includes a digital-to-analog converter and the second modulation unit includes a phase-locked loop unit.
[0016] In some embodiments, the first modulation unit includes a fifth interface pin, a sixth interface pin, and a seventh interface pin.
[0017] The fifth interface pin is coupled to the first interface pin and is configured to receive the frame synchronization clock signal. The sixth interface pin is coupled to the second interface pin and is configured to receive the bit clock signal. The seventh interface pin is coupled to the third interface pin and is configured to receive the first modulated data.
[0018] In some embodiments, the first modulation unit further includes a chip select pin, which is grounded.
[0019] In some embodiments, the second modulation unit includes a first enable interface pin, an eighth interface pin, and a ninth interface pin.
[0020] The first enable interface pin is coupled to the first interface pin and is configured to receive the frame synchronization clock signal. The eighth interface pin is coupled to the second interface pin and is configured to receive the bit clock signal. The ninth interface pin is coupled to the third interface pin and receives the second modulation data through the third interface pin.
[0021] Alternatively, the first enable interface pin is coupled to the first interface pin and is configured to receive the frame synchronization clock signal. The eighth interface pin is coupled to the second interface pin and is configured to receive the bit clock signal. The ninth interface pin is coupled to the fourth interface pin and receives the second modulated data through the fourth interface pin.
[0022] In some embodiments, the control unit further includes a general interface pin, and the second modulation unit includes a second enable interface pin, which is coupled to the general interface pin.
[0023] The control unit is configured to send control signals to the second modulation unit via a general interface pin and a second enable interface pin; wherein the control signals are configured to control the second modulation unit to power on or off.
[0024] In order to solve the above-mentioned technical problems, this application provides a terminal device, which includes the above-mentioned modulation signal generating device.
[0025] The modulation signal generating apparatus and terminal device provided in some embodiments of this application include a control unit, a first modulation unit, and a second modulation unit. The first and second modulation units are coupled to the same set of interfaces of the control unit, and the control unit is configured to transmit corresponding modulation data to the first and second modulation units through the interfaces. That is, the modulation signal generating apparatus can control the first and second modulation units using only one set of interfaces. Compared to related technologies that use multiple interfaces to control different units separately, the modulation signal generating apparatus of this application reduces the number of interfaces used. This reduction in interfaces reduces the complexity of the control unit's hardware structure, decreases the size of the control unit and the modulation signal generating apparatus, thereby reducing hardware costs. Furthermore, when the interface resources of the control unit are limited, the modulation signal generating apparatus of this application can control the first and second modulation units using only one set of interfaces, allowing the remaining interfaces to be used for other purposes. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0027] Figure 1 This is a schematic diagram of the structure of the modulation signal generating device in some embodiments of this application;
[0028] Figure 2 These are schematic diagrams of the interface structure in some embodiments of this application;
[0029] Figure 3 yes Figure 2 The diagram shows the workflow and timing diagram for data transmission through the interface shown.
[0030] Figure 4 These are schematic diagrams of the interface structure in some embodiments of this application;
[0031] Figure 5 This is a schematic diagram of the structure of the first modulation unit in some embodiments of this application;
[0032] Figure 6a This is a schematic diagram of the structure of the second modulation unit in some embodiments of this application;
[0033] Figure 6b This is a schematic diagram of the structure of the second modulation unit in some embodiments of this application;
[0034] Figure 7 This is a schematic diagram of the structure of the control unit and the second modulation unit in some embodiments of this application;
[0035] Figure 8 This is a schematic diagram of the structure of the modulation signal generating device in some embodiments of this application;
[0036] Figure 9 This is a schematic diagram of the structure of the modulation signal generating device in some embodiments of this application;
[0037] Figure 10 This is a schematic diagram of the structure of a terminal device in some embodiments of this application. Detailed Implementation
[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this application and not for limiting this application. It should also be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0039] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having” and any variations thereof in the specification, claims and foregoing description of the drawings are intended to cover non-exclusive inclusion.
[0040] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.
[0041] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0042] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0043] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).
[0044] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.
[0045] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.
[0046] Modulation technology is a process of converting signals generated by a source into a form suitable for wireless transmission. Modulation technologies include analog modulation and digital modulation. Common analog or digital modulation includes two-point modulation, which typically refers to using different interfaces to modulate different chips or devices to generate modulated signals.
[0047] However, due to manufacturing processes and other factors, different interfaces typically exhibit time delays, which are often unpredictable and unsuitable for applications requiring high real-time performance. The use of multiple interfaces increases the size of the chip or device, thereby raising hardware costs and putting the device at a disadvantage in the miniaturized and thinner market, resulting in weak market competitiveness.
[0048] To address any of the aforementioned technical problems, this application provides a modulation signal generating apparatus and a terminal device.
[0049] See Figure 1 , Figure 1 This is a schematic diagram of the structure of a modulation signal generating device in some embodiments of this application. The modulation signal generating device 100 includes a control unit 101, a first modulation unit 102, and a second modulation unit 103.
[0050] The control unit 101 includes an interface 1011, and the number of interfaces 1011 in the control unit 101 is greater than or equal to one. The control unit 101 can be an MCU (Microcontroller Unit), an FPGA (Field Programmable Gate Array), a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), or other controllers that include interfaces 1011; there are no restrictions here. The control unit 101 plays a master control role in the modulation signal generation device 100 and can generate control signals.
[0051] The first modulation unit 102 may include a digital-to-analog converter (DAC) or other modulation signal generation devices, which are not limited here.
[0052] The second modulation unit 103 includes a phase-locked loop (PLL) unit or other modulation signal generation devices. The PLL can generate an output signal that is synchronized with the input signal and has the same phase, and the PLL can generate a precise clock. In this embodiment, the structure of the modulation signal generation device 100 is described using the first modulation unit 102 as a DAC and the second modulation unit as a PLL as an example.
[0053] In this configuration, the first modulation unit 102 and the second modulation unit 103 are coupled to the same set of interfaces 1011 of the control unit 101. In this case, the control unit 101 can transmit corresponding modulation data to the first modulation unit 102 and the second modulation unit 103 through the interfaces 1011. The interface 1011 can be an I2S (Inter-IC Sound) interface, an MCBSP (Multichannel Buffered Serial Port) interface, or others. The type of interface 1011 in the control unit 101 can be determined based on the components connected to the interface 1011, and is not limited here.
[0054] For example, when the control unit 101 transmits modulation data to the first modulation unit 102 and the second modulation unit 103 using the same set of interfaces 1011, the modulation data transmitted by the control unit 101 to the first modulation unit 102 is the same as the modulation data transmitted by the control unit 101 to the second modulation unit 103.
[0055] For example, when the control unit 101 transmits modulation data to the first modulation unit 102 and the second modulation unit 103 using the same set of interfaces 1011, the control unit 101 transmits modulation data to the first modulation unit 102 and the second modulation unit 103 simultaneously.
[0056] For example, when the control unit 101 transmits modulation data to the first modulation unit 102 and the second modulation unit 103 using the same set of interfaces 1011, the control unit 101 transmits modulation data to the first modulation unit 102 and the second modulation unit 103 not simultaneously. Specifically, the control unit 101 transmits modulation data to the first modulation unit 102 first, and then transmits modulation data to the second modulation unit 103. Alternatively, the control unit 101 transmits modulation data to the second modulation unit 103 first, and then transmits modulation data to the first modulation unit 102.
[0057] In some embodiments, when the control unit 101 transmits modulation data to the first modulation unit 102 and the second modulation unit 103 at different times, there is a time interval between the transmission of modulation data from the control unit 101 to the first modulation unit 102 and the second modulation unit 103. The specific value of this time interval can be determined by repeated experiments or by other means, and is not limited here.
[0058] In other embodiments, the control unit 101 transmits modulation data to the first modulation unit 102 and the second modulation unit 103 within a time interval. This time interval is related to modulation flatness, which refers to the degree to which the power or amplitude of a signal remains consistent within a frequency band during the modulation process by the modulation signal generation device 100. Modulation flatness is related to signal quality and transmission efficiency. Based on this, the time interval for sending modulation data to the first modulation unit 102 and the second modulation unit 103 can be adjusted to adjust the modulation flatness.
[0059] See Figure 2 , Figure 2 This is a schematic diagram of the interface structure in some embodiments of this application. The interface 1011 includes a first interface pin 201, a second interface pin 202 and a third interface pin 203.
[0060] The first interface pin 201 is coupled to the first modulation unit 102 and the second modulation unit 103 respectively, and the first interface pin 201 is configured to transmit frame synchronization clock signals to the first modulation unit 102 and the second modulation unit 103.
[0061] The second interface pin 202 is coupled to the first modulation unit 102 and the second modulation unit 103 respectively. The second interface pin 202 is configured to transmit bit clock signals to the first modulation unit 102 and the second modulation unit 103.
[0062] The third interface pin 203 is coupled to the first modulation unit 102 and the second modulation unit 103, respectively. The third interface pin 203 is configured to transmit first modulation data to the first modulation unit 102 during the low level of the frame synchronization clock signal. The third interface pin 203 is also configured to transmit second modulation data to the second modulation unit 103 during the high level of the frame synchronization clock signal.
[0063] In some embodiments, the first interface pin 201 is an LRCK (Left Right Clock) pin, which is used to switch between left and right channel data. Specifically, during the high level of the frame synchronization clock signal output by the LRCK pin, the LRCK pin is used to transmit right channel data. During the low level of the frame synchronization clock signal output by the LRCK pin, the LRCK pin is used to transmit left channel data.
[0064] In some embodiments, the second interface pin 202 is an SCK (Serial Clock) pin, which controls the rate of signal transmission to achieve synchronous data transmission.
[0065] In some embodiments, the third interface pin 203 is the DATA_DO1 pin, specifically the DATA (data) pin, which is used to transmit digital signals. Specifically, the DATA_DO1 pin is used to transmit first modulated data and second modulated data.
[0066] In using such Figure 2 When the interface 1011 transmits data to the first modulation unit 102 and the second modulation unit 103, there is a time delay between transmitting the first modulation data to the first modulation unit 102 and transmitting the second modulation data to the second modulation unit 103. That is, there is a first time delay between the first modulation data and the second modulation data.
[0067] It is understood that the first delay is related to modulation flatness, which in turn is related to the quality and transmission efficiency of the first and second modulation data. Based on this, the time interval for sending modulation data to the first modulation unit 102 and the second modulation unit 103 can be adjusted to achieve modulation flatness adjustment.
[0068] The first delay is also used for calibration. At this time, based on the frame clock of the interface 1011 itself, the delay of the two modulation data to the first modulation unit 102 and the second modulation unit 103 can be precisely controlled by adjusting the size of the first delay, without the need for a separate timer or counter.
[0069] The first delay is 0.5FS + N*FS, where N is greater than or equal to 0 and is an integer, and FS represents the level time. Based on this, the first delay is greater than or equal to 0.5 level times, specifically it can be 0.5 level times, 1.5 level times, 2.5 level times, 3.5 level times, or others.
[0070] Regarding level duration, taking a clock cycle consisting of one high level and one low level as an example, FS represents the duration of the high level or the duration of the low level within one clock cycle. The high level duration may be the same as or different from the low level duration.
[0071] Regarding the level duration, taking the transmission of the first modulated data to the first modulation unit 102 via the nth low level of the third interface pin 203 as an example, if the first delay is 2.5FS, then a high level, a low level, a high level, a low level followed by a high level are required before the second modulated data can be transmitted to the second modulation unit 103. That is, 2.5FS (i.e., 2.5 level durations) corresponds to low level (nth low level), high level, low level (n+1th low level), high level, and low level (n+2th low level).
[0072] Regarding the level duration, taking the transmission of second modulated data from the third interface pin 203 to the second modulation unit 103 during the nth high level as an example, if the first delay is 2.5FS, then a low level, a high level, a low level, a high level followed by a low level are required before the first modulated data can be transmitted to the first modulation unit 102. That is, 2.5FS (i.e., 2.5 level durations) corresponds to high level (nth high level), low level, high level (n+1th high level), low level, and high level (n+2th high level).
[0073] In using such Figure 2 When the interface 1011 shown transmits data to the first modulation unit 102 and the second modulation unit 103, the corresponding workflow timing diagram can be found in [reference needed]. Figure 3 .like Figure 3 The data transmission flow corresponding to the first delay of 2.5FS is shown. I2S FS represents the frame synchronization clock signal, I2S CLK represents the bit clock signal, and I2SDATA represents the modulation data.
[0074] Specifically, during the low-level period within X1 to X2, first modulation data (corresponding to) is transmitted to the first modulation unit 102. Figure 3 In the DAC data block 1), no modulation data is transmitted between X2 and X3 until X3 to X4. During the high level period of X3 to X4, the second modulation data (corresponding to) is transmitted to the second modulation unit 103. Figure 3 The data block 1 of the PLL. Among them, X1 to X2 have one low level, X2 to X3 have two low levels and two high levels, and X3 to X4 have one high level.
[0075] See Figure 4 , Figure 4 This is a schematic diagram of the interface structure in some embodiments of this application. The interface 1011 includes a first interface pin 201, a second interface pin 202, a third interface pin 203, and a fourth interface pin 204.
[0076] The first interface pin 201 is coupled to the first modulation unit 102 and the second modulation unit 103 respectively, and the first interface pin 201 is configured to transmit frame synchronization clock signals to the first modulation unit 102 and the second modulation unit 103.
[0077] The second interface pin 202 is coupled to the first modulation unit 102 and the second modulation unit 103 respectively. The second interface pin 202 is configured to transmit bit clock signals to the first modulation unit 102 and the second modulation unit 103.
[0078] The third interface pin 203 is coupled to the first modulation unit 102. The third interface pin 203 is configured to transmit first modulation data to the first modulation unit 102 during the clock cycle of the frame synchronization clock signal. Optionally, the first modulation data is transmitted to the first modulation unit 102 during the high level of the frame synchronization clock signal; or, the first modulation data is transmitted to the first modulation unit 102 during the low level of the frame synchronization clock signal; or, the first modulation data is transmitted to the first modulation unit 102 during both the high and low levels of the frame synchronization clock signal; or other methods.
[0079] The fourth interface pin 204 is coupled to the second modulation unit 103. The fourth interface pin 204 is configured to transmit second modulation data to the second modulation unit 103 during the clock cycle of the frame synchronization clock signal. Optionally, the second modulation data is transmitted to the second modulation unit 103 during the high level of the frame synchronization clock signal; or, the second modulation data is transmitted to the second modulation unit 103 during the low level of the frame synchronization clock signal; or, the second modulation data is transmitted to the second modulation unit 103 during both the high and low levels of the frame synchronization clock signal; or other methods.
[0080] In some embodiments, the first interface pin 201 is an LRCK (Left Right Clock) pin, which is used to switch between left and right channel data. Specifically, during the high level of the frame synchronization clock signal output by the LRCK pin, the LRCK pin is used to transmit right channel data. During the low level of the frame synchronization clock signal output by the LRCK pin, the LRCK pin is used to transmit left channel data.
[0081] In some embodiments, the second interface pin 202 is an SCK (Serial Clock) pin, which controls the rate of signal transmission to achieve synchronous data transmission.
[0082] In some embodiments, the third interface pin 203 is the DATA_DO1 pin, specifically the DATA (data) pin, which is used to transmit digital signals. Specifically, the DATA_DO1 pin is used to transmit first modulated data.
[0083] In some embodiments, the fourth interface pin 204 is the DATA_DO2 pin, which is used to transmit digital signals. Specifically, the DATA_DO2 pin is used to transmit second modulated data.
[0084] In such Figure 4 The interface 1011 shown transmits first modulation data to the first modulation unit 102 via the third interface pin 203 and second modulation data to the second modulation unit 103 via the fourth interface pin 204. The first and second modulation data transmitted by the two pins are not necessarily related in time, but there may be a time delay for a single debugging data.
[0085] Specifically, the first modulation unit 102 can transmit the first modulation data by sending continuous first modulation data or by sending the first modulation data in segments. When sending in segments, there is a second time delay between any two segments of the first modulation data.
[0086] Similarly, the second modulation data can be transmitted to the second modulation unit 103 by sending continuous second modulation data or by sending the second modulation data in segments. When sending in segments, there is a third time delay between any two segments of the second modulation data.
[0087] It is understandable that the second delay is related to modulation flatness, which in turn is related to the quality and transmission efficiency of the first modulation data. Based on this, the time interval between segments of modulation data transmitted to the first modulation unit 102 can be adjusted to achieve modulation flatness adjustment.
[0088] It is understandable that the third delay is related to modulation flatness, which in turn is related to the quality and transmission efficiency of the second modulation data. Based on this, the time interval between segments of modulation data transmitted to the second modulation unit 103 can be adjusted to achieve modulation flatness adjustment.
[0089] The second delay is also used for calibration. At this time, based on the frame clock of the interface 1011 itself, the delay of the first modulation data to the first modulation unit 102 can be precisely controlled by simply adjusting the size of the second delay, without the need for a separate timer or counter.
[0090] Similarly, the third delay is also used for calibration. At this time, based on the frame clock of the interface 1011 itself, the delay of the second modulation data to the second modulation unit 103 can be precisely controlled by adjusting the size of the third delay, without the need for a separate timer or counter.
[0091] Compared to the first delay, the second and third delays are 0FS + N*FS, where N is greater than or equal to 0 and is an integer, and FS represents the level time. Based on this, both the second and third delays are greater than or equal to 0 level times, specifically 0 level times, 1 level time, 2 level times, 3 level times, or others. When N equals 0, the first debugging data and the second modulation data are transmitted continuously; when N is greater than 0, the first modulation data and the second modulation data are transmitted discontinuously (i.e., in segments).
[0092] Regarding level duration, taking a clock cycle consisting of one high level and one low level as an example, FS represents the duration of the high level or the duration of the low level within one clock cycle. The high level duration may be the same as or different from the low level duration.
[0093] Regarding the level time, taking the discontinuous transmission of the first modulated data as an example, the third interface pin 203 transmits the first modulated data to the first modulation unit 102 on the nth low level. If the second delay is 2FS, then it is necessary to sequentially experience a high level, a low level, a high level followed by a low level before the first modulated data can be transmitted to the first modulation unit 102 again. That is, 2FS (i.e., 2 level times) corresponds to a low level (the nth low level), a high level, a low level (the (n+1)th low level), and a high level.
[0094] Regarding the level time, taking the discontinuous transmission of the second modulated data as an example, the fourth interface pin 204 transmits the second modulated data to the second modulation unit 103 on the nth high level. If the second delay is 2FS, then it is necessary to sequentially experience a low level, a high level, a low level, and then a high level before the second modulated data can be transmitted to the second modulation unit 103 again. That is, 2FS (i.e., 2.5 level times) corresponds to a high level (the nth high level), a low level, a high level (the (n+1)th high level), and a low level.
[0095] See Figure 5 , Figure 5 This is a schematic diagram of the structure of the first modulation unit in some embodiments of this application. The first modulation unit 102 includes a fifth interface pin 301, a sixth interface pin 302 and a seventh interface pin 303.
[0096] The fifth interface pin 301 is coupled to the first interface pin 201, and the fifth interface pin 301 is configured to receive the frame synchronization clock signal.
[0097] The sixth interface pin 302 is coupled to the second interface pin 202, and the sixth interface pin 302 is configured to receive a bit clock signal.
[0098] The seventh interface pin 303 is coupled to the third interface pin 203, and the seventh interface pin 303 is configured to receive the first modulated data.
[0099] In some embodiments, the fifth interface pin 301 is an FS (Full Scale) pin, which is an input pin of the first modulation unit 102 and is used to select the full scale of the first modulation unit 102.
[0100] In one application scenario, when the FS pin is low, the full scale of the first modulation unit 102 is half of the input voltage; when the FS pin is high, the full scale of the first modulation unit 102 is the maximum value of the input voltage. Based on this, the duration of the FS pin being high can be increased to amplify the input signal voltage. Conversely, to reduce quantization error, the duration of the FS pin being low can be decreased.
[0101] In some embodiments, the sixth interface pin 302 is an SCLK (Serial Clock) pin, which controls the rate of signal transmission to achieve synchronous data transmission.
[0102] In some embodiments, the seventh interface pin 303 is an SDATAI (Serial Data) pin, which is used to transmit configuration information, control commands, data streams, etc. Specifically, the seventh interface pin 303 is used to receive first modulated data.
[0103] In some embodiments, such as Figure 5 As shown, the first modulation unit 102 also includes a chip select pin 304, which is grounded.
[0104] In some embodiments, the chip select pin 304 is a CS (Chip Select) pin, which is used to select a target chip to process data on the bus using the target chip.
[0105] See Figure 6a and Figure 6b , Figure 6a and Figure 6b These are schematic diagrams of the structure of the second modulation unit in some embodiments of this application. The second modulation unit 103 includes a first enable interface pin 401, an eighth interface pin 402 and a ninth interface pin 403.
[0106] The first enable interface pin 401 is coupled to the first interface pin 201, and the first enable interface pin 401 is configured to receive the frame synchronization clock signal.
[0107] The eighth interface pin 402 is coupled to the second interface pin 202, and the eighth interface pin 402 is configured to receive a bit clock signal.
[0108] The ninth interface pin 403 is coupled to the third interface pin 203, and the ninth interface pin 403 is configured to receive second modulated data through the third interface pin 203, such as... Figure 6a As shown.
[0109] Alternatively, the ninth interface pin 403 is coupled to the fourth interface pin 204, and the ninth interface pin 403 is configured to receive second modulated data through the fourth interface pin 204, such as... Figure 6b As shown.
[0110] In some embodiments, the first enable interface pin 401 is the FSK_D0_LRCK / LE pin, specifically the LE (LatchEnable) pin. When the LE pin is at a falling edge, the synchronization of the initial serial data can be achieved. The serial data is first shifted into the shift register of the second modulation unit 103, and then when the LE pin is at a rising edge, the stored data in the corresponding register inside the second modulation unit 103 is updated.
[0111] In one application scenario, the LE pin is active when it is high.
[0112] In some embodiments, the eighth interface pin 402 is the FSK_DV_SCLK / CLK pin, specifically the CLK (Clock) pin, which is used to receive clock signals and synchronize data transmission.
[0113] In some embodiments, the ninth interface pin 403 is an FSK_D1_DATA / DATA pin, specifically a DATA (data) pin, which is used to transmit digital signals. Specifically, the ninth interface pin 403 is used to receive first modulated data and second modulated data.
[0114] In some embodiments, such as Figure 7 As shown, the control unit 101 also includes a general interface pin 1012, and the second modulation unit 103 includes a second enable interface pin 404, which is coupled to the general interface pin 1012.
[0115] At this time, the control unit 101 can be configured to send a control signal to the second modulation unit 103 via the general interface pin 1012 and the second enable interface pin 404. The control signal is configured to power on or off the second modulation unit 103.
[0116] Specifically, the control unit 101 is configured to: power on the second modulation unit 103 during the high level of the control signal; and power off the second modulation unit 103 during the low level of the control signal.
[0117] In some embodiments, the general interface pin 1012 is the GPIO_PLL_CE pin, specifically the GPIO (General Purpose Input Output) pin, which is used to read signals, output control signals, or other functions.
[0118] In some embodiments, the second enable interface pin 404 is a CE (Chip Enable) pin, used to enable or disable the function of the second modulation unit 103.
[0119] In summary, see Figure 8 , Figure 8 This is a schematic diagram of the structure of a modulation signal generating device in some embodiments of this application. The modulation signal generating device 100 includes an MCU, a DAC, and a PLL.
[0120] Among them, the MCU corresponds to the control unit 101, the DAC corresponds to the first modulation unit 102, and the PLL corresponds to the second modulation unit 103.
[0121] The MCU includes either an I2S interface or an MCBSP interface. Specifically, the I2S interface or MCBSP interface includes the LRCK pin, SCK pin, DATA_DO1 pin, and GPIO_PLL_CE pin.
[0122] The DAC includes the FS pin, SCLK pin, SDATAI pin, and CS pin.
[0123] The PLL includes the FSK_D0_LRCK / LE pin, the FSK_DV_SCLK / CLK pin, the FSK_D1_DATA / DATA pin, and the CE pin.
[0124] At this time, the FS pin and the FSK_D0_LRCK / LE pin are coupled to the LRCK pin, the SCLK pin and the FSK_DV_SCLK / CLK pin are coupled to the SCK pin, the SDATAI pin and the FSK_D1_DATA / DATA pin are coupled to the DATA_DO1 pin, the CS pin is grounded, and the CE pin is coupled to the GPIO_PLL_CE pin.
[0125] The MCU can send frame synchronization clock signals to the FS pin and the FSK_D0_LRCK / LE pin via the LRCK pin, so that the signals can be transmitted to the DAC via the FS pin and to the PLL via the FSK_D0_LRCK / LE pin.
[0126] The MCU can send bit clock signals to the SCLK pin and the FSK_DV_SCLK / CLK pin via the SCK pin, so that the signals can be transmitted to the DAC via the SCLK pin and to the PLL via the FSK_DV_SCLK / CLK pin.
[0127] The MCU can send the first modulation data or the second modulation data to the SDATAI pin and the FSK_D1_DATA / DATA pin via the DATA_DO1 pin, so that it can be transmitted to the DAC via the SDATAI pin and to the PLL via the FSK_D1_DATA / DATA pin.
[0128] The MCU can send control signals to the CE pin via the GPIO_PLL_CE pin, which are then transmitted to the PLL via the CE pin to control the power-on or power-off of the PLL.
[0129] In summary, see Figure 9 , Figure 9 This is a schematic diagram of the structure of a modulation signal generating device in some embodiments of this application. The modulation signal generating device 100 includes an MCU, a DAC, and a PLL.
[0130] Among them, the MCU corresponds to the control unit 101, the DAC corresponds to the first modulation unit 102, and the PLL corresponds to the second modulation unit 103.
[0131] The MCU includes either an I2S interface or an MCBSP interface. Specifically, the I2S interface or MCBSP interface includes the LRCK pin, SCK pin, DATA_DO1 pin, GPIO_PLL_CE pin, and DATA_DO2 pin.
[0132] The DAC includes the FS pin, SCLK pin, SDATAI pin, and CS pin.
[0133] The PLL includes the FSK_D0_LRCK / LE pin, the FSK_DV_SCLK / CLK pin, the FSK_D1_DATA / DATA pin, and the CE pin.
[0134] At this time, the FS pin and the FSK_D0_LRCK / LE pin are coupled to the LRCK pin, the SCLK pin and the FSK_DV_SCLK / CLK pin are coupled to the SCK pin, the SDATAI pin is coupled to the DATA_DO1 pin, the FSK_D1_DATA / DATA pin is coupled to the DATA_DO2 pin, the CS pin is grounded, and the CE pin is coupled to the GPIO_PLL_CE pin.
[0135] The MCU can send frame synchronization clock signals to the FS pin and the FSK_D0_LRCK / LE pin via the LRCK pin, so that the signals can be transmitted to the DAC via the FS pin and to the PLL via the FSK_D0_LRCK / LE pin.
[0136] The MCU can send bit clock signals to the SCLK pin and the FSK_DV_SCLK / CLK pin via the SCK pin, so that the signals can be transmitted to the DAC via the SCLK pin and to the PLL via the FSK_DV_SCLK / CLK pin.
[0137] The MCU can send the first modulated data to the SDATAI pin via the DATA_DO1 pin, so that it can be transmitted to the DAC via the SDATAI pin.
[0138] The MCU can send the second modulated data to the FSK_D1_DATA / DATA pin via the DATA_DO2 pin, so that it can be transmitted to the PLL via the FSK_D1_DATA / DATA pin.
[0139] The MCU can send control signals to the CE pin via the GPIO_PLL_CE pin, which are then transmitted to the PLL via the CE pin to control the power-on or power-off of the PLL.
[0140] See Figure 10 , Figure 10 This is a schematic diagram of the structure of a terminal device in some embodiments of this application. The terminal device 200 includes the modulation signal generating device 100 described in any of the above embodiments, which will not be repeated here.
[0141] In some embodiments, the terminal device 200 includes a memory and a processor. The processor involved in this application may be referred to as a CPU (Central Processing Unit), which may be an integrated circuit chip, or a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component.
[0142] In summary, the modulation signal generating device 100 and the modulation signal generating device 103 provided in some embodiments of this application can control the first modulation unit 102 and the second modulation unit 103 using only one interface 1011. Compared with the related technologies that use multiple interfaces to control different units separately, the modulation signal generating device 100 of this application can reduce the number of interfaces. The reduction of interfaces can reduce the complexity of the hardware structure of the control unit 101, reduce the size of the control unit 101 and the modulation signal generating device 100, and thus reduce hardware costs. Furthermore, when the interface resources of the control unit 101 are limited, the modulation signal generating device 100 of this application can control the first modulation unit 102 and the second modulation unit 103 using only one set of interfaces 1011, thus freeing up the remaining interfaces for other uses.
[0143] By using the same pin to couple the first modulation unit 102 and the second modulation unit 103 in interface 1011, and loading the first modulation data transmitted to the first modulation unit 102 and the second modulation data transmitted to the second modulation unit 103 at high and low levels respectively, the efficiency of data transmission can be improved. Furthermore, by transmitting different modulation data at high and low levels respectively, a time delay exists between the two modulation data types. This time delay corresponds to the modulation flatness, thereby enabling adjustment of the modulation flatness.
[0144] When the first modulation unit 102 and the second modulation unit 103 are coupled to different pins in the interface 1011, there is no necessary connection between the first modulation data sent to the first modulation unit 102 and the second modulation data sent to the second modulation unit 103. The first modulation data and the second modulation data can be sent simultaneously to improve data transmission efficiency, or the first modulation data and the second modulation data can be sent continuously. In this case, the time delay between the two segments of the first modulation data or the two segments of the second modulation data corresponds to the modulation flatness, thereby enabling the adjustment of the modulation flatness.
[0145] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A modulation signal generating apparatus, characterized in that, include: Control unit, first modulation unit, and second modulation unit; The first modulation unit and the second modulation unit are coupled to the same set of interfaces of the control unit, and the control unit is configured to transmit corresponding modulation data to the first modulation unit and the second modulation unit through the interfaces.
2. The modulation signal generating apparatus according to claim 1, characterized in that, The interface includes: The first interface pin is coupled to the first modulation unit and the second modulation unit respectively, and the first interface pin is configured to transmit a frame synchronization clock signal to the first modulation unit and the second modulation unit. The second interface pin is coupled to the first modulation unit and the second modulation unit respectively, and the second interface pin is configured to transmit bit clock signals to the first modulation unit and the second modulation unit. A third interface pin is coupled to the first modulation unit and the second modulation unit, respectively. The third interface pin is configured to transmit first modulation data to the first modulation unit during the low level of the frame synchronization clock signal and to transmit second modulation data to the second modulation unit during the high level of the frame synchronization clock signal.
3. The modulation signal generating apparatus according to claim 1, characterized in that, The interface includes: The first interface pin is coupled to the first modulation unit and the second modulation unit respectively, and the first interface pin is configured to transmit a frame synchronization clock signal to the first modulation unit and the second modulation unit. The second interface pin is coupled to the first modulation unit and the second modulation unit respectively, and the second interface pin is configured to transmit bit clock signals to the first modulation unit and the second modulation unit. A third interface pin is coupled to the first modulation unit, and the third interface pin is configured to transmit first modulation data to the first modulation unit during the clock period of the frame synchronization clock signal. The fourth interface pin is coupled to the second modulation unit and is configured to transmit second modulation data to the second modulation unit during the clock period of the frame synchronization clock signal.
4. The modulation signal generating apparatus according to claim 1, characterized in that, The interface is an I2S interface or an MCBSP interface, and / or the first modulation unit includes a digital-to-analog converter unit, and the second modulation unit includes a phase-locked loop unit.
5. The modulation signal generating apparatus according to claim 2 or 3, characterized in that, The first modulation unit includes: The fifth interface pin is coupled to the first interface pin, and the fifth interface pin is configured to receive the frame synchronization clock signal; A sixth interface pin is coupled to the second interface pin, and the sixth interface pin is configured to receive the bit clock signal; The seventh interface pin is coupled to the third interface pin and is configured to receive the first modulated data.
6. The modulation signal generating apparatus according to claim 5, characterized in that, The first modulation unit further includes a chip select pin, which is grounded.
7. The modulation signal generating apparatus according to claim 2, characterized in that, The second modulation unit includes: A first enable interface pin is coupled to a first interface pin, which is configured to receive the frame synchronization clock signal. The eighth interface pin is coupled to the second interface pin, and the eighth interface pin is configured to receive the bit clock signal; The ninth interface pin is coupled to the third interface pin and receives the second modulation data through the third interface pin.
8. The modulation signal generating apparatus according to claim 3, characterized in that, The second modulation unit includes: A first enable interface pin is coupled to a first interface pin, which is configured to receive the frame synchronization clock signal. The eighth interface pin is coupled to the second interface pin, and the eighth interface pin is configured to receive the bit clock signal; The ninth interface pin is coupled to the fourth interface pin and receives the second modulation data through the fourth interface pin.
9. The modulation signal generating apparatus according to claim 1, characterized in that, The control unit further includes a general interface pin, and the second modulation unit includes a second enable interface pin, which is coupled to the general interface pin. The control unit is configured to send a control signal to the second modulation unit via the general interface pin and the second enable interface pin; wherein the control signal is configured to control the second modulation unit to power on or power off.
10. A terminal device, characterized in that, The terminal device includes the modulation signal generating apparatus according to any one of claims 1-9.