A medium-high voltage shield gate power device layout and device
By optimizing the gate contact hole connection method of the layout of medium and high voltage shielded power devices, the problems of large gate capacitance and charge were solved, the SOA performance of the safe operating area was improved, and the cost-effectiveness was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WILL SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2025-08-14
- Publication Date
- 2026-07-10
AI Technical Summary
In existing shielded gate power device layout designs, the gate capacitance and gate charge are relatively large, which affects switching losses and results in generally poor SOA performance in the safe operating area.
The gate contact hole connection method is optimized so that the gate contact hole areas are spaced apart in the trench, reducing the number of trenches. The SOA performance of the safe working area is improved through layout design without increasing the cost of the mask.
It significantly improves the performance of the Secure Workspace (SOA) by several times, while maintaining a cost advantage and without increasing additional costs.
Smart Images
Figure CN224481972U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this application belong to the field of semiconductor technology, and in particular relate to a layout and device of a medium- and high-voltage shielded gate power device. Background Technology
[0002] In the layout design of shielded gate power devices, the source polysilicon electrode, gate, and source need to be connected separately, and the source polysilicon electrode needs to be isolated from the gate. However, before design optimization, such as... Figure 1 As shown, each trench 4 of the gate polysilicon is provided with a gate contact hole 7, which will result in a large gate capacitance and gate charge, affecting switching losses, and the SOA performance in the safe operating area is generally poor. Summary of the Invention
[0003] To address or mitigate the problems in the prior art, in a first aspect, embodiments of this application provide a layout of a medium-to-high voltage shielded gate power device, comprising: a cell region;
[0004] The cell region includes multiple spaced-apart first trenches, source polysilicon lead-out regions, gate lead-out regions, and source lead-out regions;
[0005] The region where the source polysilicon lead-out area is located is provided with a source contact hole area and a source polysilicon contact hole area. The source polysilicon contact hole is located in the first trench, and the source contact hole area is located between adjacent first trenches.
[0006] The area where the gate lead-out region is located is provided with a gate contact hole region, which is located in the first trench, and the first trenches where the gate contact hole region is located are spaced apart.
[0007] The region where the source lead-out area is located is provided with a source contact hole area and a source polysilicon contact hole area. The source polysilicon contact area is located in the first trench, and the source contact hole area is located between adjacent first trenches.
[0008] In a preferred embodiment of this application, the first trenches containing the gate contact hole regions are separated by a first trench.
[0009] Secondly, embodiments of this application also provide a medium- or high-voltage shielded power device, fabricated using the layout described in any of the first aspects.
[0010] Compared with the prior art, the embodiments of this application provide a layout and device for a medium- and high-voltage shielded gate power device. By optimizing the gate contact hole connection method, the first trenches where the gate contact hole area is located are spaced apart, that is, the gate polysilicon is spaced apart to connect the gate contact holes. The safe operating area (SOA) performance of this application can be improved by several times. The number of first trenches where the gate contact hole area is located can be selected according to the required safe operating area SOA performance. In addition, no additional mask is required, which has a certain cost advantage. Attached Figure Description
[0011] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0012] Figure 1 This is a layout of a medium-to-high voltage shielded power device provided by existing technology;
[0013] Figure 2 This is a layout of a medium-high voltage shielded grid power device provided in an embodiment of this application. Detailed Implementation
[0014] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.
[0015] like Figure 2 As shown, in a first aspect, embodiments of this application provide a layout of a medium-to-high voltage shielded gate power device, including: a cell region;
[0016] The cell region includes multiple spaced-apart first trenches 4, source polysilicon lead-out regions 11, gate lead-out regions 12, and source lead-out regions 13;
[0017] The region where the source polysilicon lead-out area 11 is located is provided with a source contact hole area 6 and a source polysilicon contact hole area 5. The source polysilicon contact hole area 5 is disposed in the first trench 4, and the source contact hole area 6 is disposed between adjacent first trenches 4.
[0018] The area where the gate lead-out region 12 is located is provided with a gate contact hole region 7. The gate contact hole region 7 is located in the first trench 4, and the first trench 4 where the gate contact hole region 7 is located is spaced apart.
[0019] The region where the source lead-out area 13 is located is provided with a source contact hole area 6 and a source polysilicon contact hole area 5. The source polysilicon contact area 5 is located in the first trench 4, and the source contact hole area 6 is located between adjacent first trenches 4.
[0020] In a preferred embodiment of this application, the first trenches 4 in which the gate contact hole regions 7 are located are separated by one first trench 4.
[0021] It should be noted that serial number 8 is... Figure 1 and Figure 2 The cross-sectional view of region 1 in the diagram, number 9 is... Figure 1 and Figure 2 The cross-sectional view of region 2 in the diagram, with serial number 10 being... Figure 1 and Figure 2 A cross-sectional view of region 1 in the diagram.
[0022] Secondly, embodiments of this application also provide a medium- or high-voltage shielded power device, fabricated using the layout described in any of the first aspects.
[0023] It should be noted that the power device in this application is a MOSFET.
[0024] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A layout for a medium- and high-voltage shielded power device, characterized in that, include: Cell region; The cell region includes multiple spaced-apart first trenches, source polysilicon lead-out regions, gate lead-out regions, and source lead-out regions; The region where the source polysilicon lead-out area is located is provided with a source contact hole area and a source polysilicon contact hole area. The source polysilicon contact hole area is located in the first trench, and the source contact hole area is located between adjacent first trenches. The area where the gate lead-out region is located is provided with a gate contact hole region, which is located in the first trench, and the first trenches where the gate contact hole region is located are spaced apart. The region where the source lead-out area is located is provided with a source contact hole area and a source polysilicon contact hole area. The source polysilicon contact hole area is located in the first trench, and the source contact hole area is located between adjacent first trenches.
2. The layout of a medium-high voltage shielded power device as described in claim 1, characterized in that, The first trenches containing the gate contact hole regions are separated by one first trench.
3. A medium-to-high voltage shielded power device, characterized in that, Prepared using the layout as described in claim 1 or 2.