Power transistor element with current sampling structure

Abstract

A power transistor device with a current sampling structure includes N power transistors, a main source electrode and a first sampling source electrode, each of the power transistors having a source. The main source electrode conducts a main supply current through M of the power transistors, and the first sampling source electrode conducts a first sampling supply current through S of the power transistors, N, M, S being positive integers, and M being greater than or equal to S, and M plus S being less than or equal to N. The first sampling source electrode and the main source electrode are electrically isolated from each other by a separation trench. The amount of the first sampling supply current is measured through the first sampling source electrode, and the amount of the main supply current can be accurately calculated by a user according to the amount of the first sampling supply current.

Description

Technical Field

[0001] A power transistor device, particularly a power transistor device having a current sampling structure. Background Technology

[0002] A power transistor is a general term for a transistor that can be used to process high-power electrical signals. For example, a metal-oxide-semiconductor field-effect transistor (MOSFET) that can process high-power electrical signals is a power MOSFET, and existing power MOSFETs have a source, a drain, and a gate.

[0003] Please see Figure 9 and Figure 10 As shown, a special powerMOS with model number TO-247-4L, in addition to its source, drain, and gate, also has a temperature sensing electrode or a voltage sensing electrode. The drain is connected to a first pin 1 of the TO-247-4L, the source is connected to a second pin 2, the temperature sensing electrode or voltage sensing electrode is connected to a third pin 3, and the gate is connected to a fourth pin 4. When the TO-247-4L is powered by a high-power signal, the generated waste heat diffuses gradient to the temperature sensing electrode, changing its voltage value. Thus, by sensing the voltage change at the temperature sensing electrode, the voltage condition can be determined, and further, it can be inferred whether the temperature of the semiconductor junction of the temperature sensing electrode exceeds an over-temperature threshold. When the temperature of the temperature sensing electrode exceeds the over-temperature threshold, the user can stop the TO-247-4L from conducting and provide over-temperature protection.

[0004] However, the above-mentioned mechanism for protecting the power MOS from damage still has some problems. For example, the temperature sensed by the temperature sensing electrode is the temperature that spreads through the gradient between the source and the drain when the power is turned on. Therefore, there may be a difference between the measured temperature and the actual over-temperature situation. This difference may result in the power MOS being damaged by over-temperature without the over-temperature being detected.

[0005] Please see Figures 11 to 13 As shown, multiple power MOS transistors, as described above with the TO-247-4L, can be connected in parallel within a single power MOS package. Thus, as... Figure 11 As shown, the drains of each power MOS are connected to a common drain electrode DE, the gates of each power MOS are connected to a common gate electrode GE, the sources of each power MOS are connected to a common source electrode SE, and the sources of each power MOS and the source electrode SE are connected to a voltage sensing electrode contact KSC.

[0006] like Figure 12 As shown, one housing of this power MOS package exposes pins P1 to P9. Figure 13 As shown, the power MOS package internally consists of a source electrode SE wired to pins P3-P8, a voltage sensing electrode KSC wired to pin P2, and a gate electrode GE wired to pin P1. The drain electrode DE is connected to pin P9 via an internal circuit. Figure 13 The key point is that the voltage sensing electrode contact KSC and the source electrode SE are clearly interconnected, therefore the voltage sensing electrode contact KSC and the source electrode SE have the same potential. With this setup, pin P2 senses the voltage of the source electrode SE only through the voltage sensing electrode contact KSC. Since no current flows through pin P2, and a large current flows between pins P3-P8, there will be a difference in voltage between pins P2 and pins P3-P8. This difference is used to infer the voltages of the gate electrode GE and the source electrode SE through voltage sensing, and to perform feedback adjustment to control the voltage of the gate electrode GE. Utility Model Content

[0007] To prevent damage to power transistors, this invention provides a power transistor device with a current sampling structure. This power transistor device uses the current of the power transistor as the numerical basis for preventing damage, meaning that the unique current sampling structure of this invention provides the possibility of detecting the current of the power transistor. In application, by sensing the current of the power transistor and determining whether the current is excessive, the user can more accurately determine when the power transistor should stop operating to protect it from damage. In other words, the hardware defined in this invention provides the possibility of protecting the power transistor from damage through overcurrent protection. This overcurrent protection method is not affected by the temperature diffusion gradient of the power transistor and can more accurately determine whether the power transistor is conducting excessive power, thus preventing damage to the power transistor when conducting high-power electrical signals.

[0008] This utility model discloses a power transistor device with a current sampling structure, comprising several power transistors, a main source electrode, and a first sampling source electrode. Each power transistor has a source, and the first sampling source electrode and the main source electrode are electrically isolated from each other by forming a gap trench. The number of power transistors will be represented by letters such as N, M, and S below.

[0009] The power transistor of this invention has a total of N power transistors;

[0010] The main source electrode is electrically connected to the sources of the M power transistors, and a main power supply current is conducted through the M power transistors.

[0011] The first sampling source electrode is electrically connected to the source of S power transistors, and a first sampling power supply current is conducted through the S power transistors.

[0012] N, M, and S are positive integers, and M is greater than or equal to S, and M plus S is less than or equal to N.

[0013] The above definition ensures that the S power transistors electrically connected to the first sampling source electrode have a channel cross-section area that is less than or equal to the channel cross-section area of ​​the M power transistors electrically connected to the main source electrode. Furthermore, there is an M:S ratio between the channel cross-section areas of the M power transistors and the S power transistors. Because the conduction current of the power transistors has a linear relationship with the channel cross-section area, the main power supply current conducted through the M power transistors and the first sampling power supply current conducted through the S power transistors also have an M:S ratio. The first sampling source electrode of this invention is a current sampling structure applied to power transistors. By measuring the current of the first sampling power supply, the user of this invention can accurately calculate the current of the main power supply according to the ratio, that is, by measuring the current of a lower-power electrical signal, the current of a higher-power electrical signal can be calculated proportionally.

[0014] This invention eliminates the need to directly measure the main power supply current, thus avoiding additional power loss due to the resistance in the circuit conducting the main power supply. Furthermore, it eliminates the need for costly low-resistance resistors capable of handling high-power signals to measure the main power supply current. Therefore, besides eliminating the need for temperature sensing to protect the power transistor, this invention offers several advantages, making it widely applicable in various packages to protect power transistors from damage. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of a power transistor element with a current sampling structure according to the present invention.

[0016] Figure 2 This is a cross-sectional schematic diagram of the power transistor of this utility model.

[0017] Figure 3 This is a three-dimensional schematic diagram of the power transistor of this utility model.

[0018] Figure 4 This is a top view schematic diagram of the power transistor element of this utility model.

[0019] Figure 5 This is another top view schematic diagram of the power transistor of this utility model.

[0020] Figure 6 This is another cross-sectional view of the power transistor of this utility model.

[0021] Figure 7 This is a schematic diagram of the appearance of the power transistor element of this utility model.

[0022] Figure 8 This is a schematic diagram of the internal structure of the power transistor element of this utility model.

[0023] Figure 9 This is a schematic diagram of the exterior of the TO-247-4L.

[0024] Figure 10 This is a circuit diagram of TO-247-4L.

[0025] Figure 11 This is a circuit diagram of an existing package.

[0026] Figure 12 This is a schematic diagram of the appearance of an existing package.

[0027] Figure 13 This is a schematic diagram of the internal structure of an existing package. Detailed Implementation

[0028] Please see Figure 1 As shown, this utility model provides a power transistor device with a current sampling structure. The power transistor device of this utility model includes several power transistors 10, a main source electrode MSE, and a first sampling source electrode SE1. Power transistor 10 generally refers to N transistors that can be used to process high-power electrical signals, where N is a positive integer greater than 1, and each power transistor 10 has a source 11.

[0029] The main source electrode MSE is electrically connected to the sources 11 of M power transistors 10, and the main source electrode MSE conducts a main power supply current Cm through the M power transistors 10. The first sampling source electrode SE1 is electrically connected to the sources 11 of S power transistors 10, and the first sampling source electrode SE1 conducts a first sampling power supply current Cs through the S power transistors 10. M and S are positive integers, where M is greater than or equal to S, and M plus S is less than or equal to N. Figure 1 As shown, the first sampling source electrode SE1 and the main source electrode MSE are electrically isolated from each other and not electrically connected. In this way, it can be ensured that the first sampling power supply current Cs transmitted by the first sampling source electrode SE1 and the main power supply current Cm transmitted by the main source electrode MSE are transmitted independently.

[0030] Furthermore, since all the power transistors 10 have the same specifications, the cross-sectional area of ​​the channel of each power transistor 10 is the same. Thus, the above definition ensures that the cross-sectional area of ​​the S power transistors 10 electrically connected to the first sampling source electrode SE1 is less than or equal to the cross-sectional area of ​​the channel of the M power transistors 10 electrically connected to the main source electrode MSE. Moreover, there is an M:S ratio between the cross-sectional areas of the M power transistors 10 and the cross-sectional areas of the S power transistors 10. Because there is a linear relationship between the conduction current of each power transistor 10 and the cross-sectional area of ​​its channel, the main power supply current Cm conducted through the M power transistors 10 and the first sampling power supply current Cs conducted through the S power transistors 10 also have an M:S ratio. The first sampling source electrode SE1 of this invention is a current sampling structure applied to a power transistor. By measuring the current of the first sampling power supply current Cs, the user of this invention can accurately calculate the current of the main power supply current Cm according to the ratio. That is, by measuring the current of the lower power electrical signal, the current of the higher power electrical signal can be calculated proportionally.

[0031] Thus, this invention eliminates the need to directly measure the main power supply current Cm, thereby avoiding additional power loss due to the current sampling resistor in the circuit that conducts the main power supply current Cm. Furthermore, this invention eliminates the need to incur significant costs by purchasing low-resistance resistors capable of handling high-power signals to measure the main power supply current Cm. Therefore, besides eliminating the need to protect the power transistor from damage by sensing temperature, this invention's power transistor element offers several advantages, making it widely applicable in various packages to protect the power transistors 10 from damage.

[0032] In one embodiment of this invention, each power transistor 10 is a metal-oxide-semiconductor field-effect transistor (MOSFET). Therefore, each power transistor 10, in addition to the source 11, also has a gate 12 and a drain 13. The MOSFET can be a silicon (Si) MOSFET. Furthermore, the power transistor element of this invention also includes a gate electrode GE and a drain electrode DE. The gate electrode GE is electrically connected to the gates 12 of N power transistors 10, and the drain electrode DE is electrically connected to the drains 13 of N power transistors 10. Thus, by changing the potential of the gate electrode GE, the gates 12 of the power transistors 10 can be simultaneously controlled to turn on or off. When the gates 12 are turned on, the source 11 and the drain 13 of each power transistor 10 are turned on; when the gates 12 are turned off, the source 11 and the drain 13 of each power transistor 10 are not turned on.

[0033] In this embodiment, the N power transistors 10, the main source electrode MSE, the first sampling source electrode SE1, the gate electrode GE, and the drain electrode DE are all disposed in a single package chip. Thus, the package chip can control the gate electrode GE to determine whether to turn on the N power transistors 10. When the N power transistors 10 are turned on, S of the N power transistors 10 conduct a smaller power first sampling power supply current Cs to the first sampling source electrode SE1 for current sampling, while M of the N power transistors 10 conduct a larger power main power supply current Cm to the main source electrode MSE to perform the basic function of power transistor power transmission.

[0034] Please see Figure 2 and Figure 3As shown, in one embodiment, each power transistor 10 is a superjunction MOSFET (SJ-MOS), and each SJ-MOS array is disposed between an upper surface TS and a lower back surface BS of the package chip, and each SJ-MOS has the same specifications. Furthermore, regarding the type of semiconductor doping, between the upper surface TS and the lower back surface BS, from bottom to top, the SJ-MOS arrays are sequentially disposed with an N+ type semiconductor doped layer 14, an N-type semiconductor bulk layer 15, a P-type semiconductor bulk layer 16, a P-type semiconductor contact layer 17, a P+ type semiconductor contact layer 18, and an N+ type semiconductor contact layer 19.

[0035] The main source electrode MSE of this invention consists of M SJ-MOS transistors covered on the upper surface TS, and the first sampling source electrode SE1 consists of S S SJ-MOS transistors covered on the upper surface TS. A plurality of aluminum-free metal layers 21 of the SJ-MOS transistors are connected to the source electrode between the main source electrode MSE and the first sampling source electrode SE1. Furthermore, a spacing trench 20 is formed between the main source electrode MSE and the first sampling source electrode SE1. The drain electrode DE is disposed on the lower back surface BS of the packaged chip.

[0036] The upper surface TS of the packaged chip is provided with an insulating protective layer 30. The insulating protective layer 30 is an insulating material, and it covers the main source electrode MSE, the first sampling source electrode SE1, and the spacer trench 20 on the upper surface TS, with the insulating material filling the spacer trench 20. In this way, the insulating protective layer 30 can protect the upper surface TS of the packaged chip from damage caused by external impacts, and also help to electrically insulate the main source electrode MSE and the first sampling source electrode SE1 from each other.

[0037] Furthermore, the main source electrode MSE and the first sampling source electrode SE1 are each part of an aluminum metal layer 21, and the spacing trench 20 separating the main source electrode MSE and the first sampling source electrode SE1 is an aluminum metal layer spacing trench. The aluminum metal layer 21 corresponding to the main source electrode MSE extends into the sources of M SJ-MOS, and the aluminum metal layer 21 corresponding to the first sampling source electrode SE1 extends into the sources of S S SJ-MOS. The upper surface TS also has multiple bond pad bonding areas, and the insulating protective layer 30 in each bond pad bonding area is removed, so that the aluminum metal layer 21 is directly exposed. Specifically, the bond pad bonding areas include a sampling source bond pad bonding area 41 and a main source bond pad bonding area 42. The sampling source pad bonding area 41 corresponding to the first sampling source electrode SE1 has the insulating protective layer 30 removed, directly exposing the first sampling source electrode SE1 in the sampling source pad bonding area 41. The main source pad bonding area 42 corresponding to the main source electrode MSE has the insulating protective layer 30 removed, directly exposing the main source electrode MSE in the main source pad bonding area 42.

[0038] When the SJ-MOS is turned on, the first sampling power supply current Cs flows upward from the drain electrode DE of the lower back surface BS through the N+ type semiconductor doped bottom layer 14, the N type semiconductor body layer 15, the P type semiconductor contact layer 17, and the N+ type semiconductor contact layer 19 to the first sampling source electrode SE1. Similarly, the main power supply current Cm flows upward from the drain electrode DE of the lower back surface BS through the N+ type semiconductor doped bottom layer 14, the N type semiconductor body layer 15, the P type semiconductor contact layer 17, and the N+ type semiconductor contact layer 19 to the main source electrode MSE. Based on the ratio of the number of SJ-MOS covered by the first sampling source electrode SE1 and the main source electrode MSE, the ratio of the currents simultaneously conducting with the first sampling power supply current Cs can be determined. This allows for the accurate calculation of the main power supply current Cm based on the sampled first sampling power supply current Cs.

[0039] The ratio of the M SJ-MOS covered by the main source electrode MSE to the S S SJ-MOS covered by the first sampling source electrode SE1, which is the aforementioned M:S current ratio, can be understood through the following width (W) / length (L) ratio in semiconductor elements:

[0040] The main source electrode MSE corresponds to a width-to-length ratio of (W1) / (L1); where W1 = the width of the N+ type semiconductor doped region of the SJ-MOS covered by the main source electrode MSE; and L1 = the gate length of the SJ-MOS covered by the main source electrode MSE.

[0041] The first sampling source electrode SE1 corresponds to a width-to-length ratio of (W2) / (L2); where W2 = the width of the S N+ type semiconductor doped regions of the SJ-MOS covered by the first sampling source electrode SE1; and L2 = the gate length of the S SJ-MOS covered by the first sampling source electrode SE1.

[0042] When L1=L2, the current ratio between the main source electrode MSE and the first sampling source electrode SE1 is simplified from [(W1) / (L1)]:[(W2) / (L2)] to (W1):(W2);

[0043] Here (W1):(W2) represents (the width of the M N+ type semiconductor doped regions of the SJ-MOS covered by the main source electrode MSE): (the width of the S N+ type semiconductor doped regions of the SJ-MOS covered by the first sampling source electrode SE1). Since all SJ-MOS have the same size, it can be further simplified to the ratio of M:S.

[0044] In one embodiment, the width of the N+ type semiconductor doped regions of the M SJ-MOS covered by the main source electrode MSE is 10,000 micrometers (µm), and the width of the N+ type semiconductor doped regions of the S S SJ-MOS covered by the first sampling source electrode SE1 is 4 micrometers (µm). Therefore, the M:S ratio is (10,000µm):(4µm) = 2500. This means that the main power supply current Cm conducted by the main source electrode MSE has a current quantity 2500 times that of the first sampling power supply current Cs conducted by the first sampling source electrode SE1. Conversely, the current quantity of the first sampling power supply current Cs conducted by the first sampling source electrode SE1 is 4 / 10,000 times that of the main power supply current Cm conducted by the main source electrode MSE. The user of this utility model can measure the smaller current of the first sampling power supply current Cs by sampling from the first sampling source electrode SE1, and then multiply it by 2500 to calculate the larger current of the main power supply current Cm. In this way, the user can know the amount of current that the power transistor device is conducting as a whole, and determine whether the amount of current that is conducting as a whole exceeds a current threshold and causes an overcurrent.

[0045] In other embodiments, the M:S ratio may also be configured to other ratios, but as mentioned above, the present invention limits M to be greater than or equal to S.

[0046] Please see Figure 4 , Figure 5 and Figure 6 As shown, from Figure 4 The top view diagram shows that the two-dimensional array of SJ-MOS is disposed on one surface of the packaged chip, and the surface has reserved positions for the spacer trenches 20. The spacer trenches 20 contain the corresponding structures of the aforementioned S S SJ-MOS power transistors 10, while the spacer trenches 20 contain the corresponding structures of the aforementioned M SJ-MOS power transistors 10. Figure 5 The top view shown is an enlarged view of the SJ-MOS power transistor 10. Figure 6 The cross-sectional schematic diagram shown is an enlarged cross-sectional structural schematic diagram of these power transistors 10 as SJ-MOS.

[0047] like Figure 5 and Figure 6 As shown in the schematic diagram of one embodiment, each power transistor 10 of the SJ-MOS includes a body contact 101 connected to the upper surface TS, a source trench 102 surrounding the body contact 101, a gate trench 104 surrounding the source trench 102, and a source / body contact 103 located between the source trench 102 and the gate trench 104. Each power transistor 10 of the SJ-MOS also includes a drain metal bulk 105 connected to the lower back surface BS. The gate trench 104 is located below the polysilicon gate of each SJ-MOS and controls whether the source / body contact 103 conducts current flowing through the source trench 102. The source / body junction 103 is a junction located between the source metal and the body material, and its conduction current is controlled by the polysilicon gate. Therefore, the source / body junction 103 is also the junction of each SJ-MOS. The source trench 102 is a structure for guiding the current flow between the source / body junction 103 and the drain metal body 105.

[0048] Compare Figure 2 and Figure 6 ,visible Figure 6 The main contact 101 shown corresponds to Figure 2 The P+ type semiconductor contact layer 18 shown is Figure 6 The source trench 102 shown corresponds to Figure 2The N+ type semiconductor contact layer 19 shown is... Figure 2 The gate electrode GE shown corresponds to Figure 6 The structure above the gate trench 104 is shown. By separating the first sampling source electrode SE1 and the main source electrode MSE through the spacer trench 20, the body contact 101, source trench 102, source / body junction 103 and the gate trench 104 fully exposed by the spacer trench 20 will be open-circuited and electrically isolate the first sampling source electrode SE1 and the main source electrode MSE.

[0049] Please see Figure 7 and Figure 8 As shown, in one embodiment, the power transistor element of this invention can also be a package, with pins P1 to P9 exposed by a housing 40. The power transistor element is housed within the housing 40, with pins P3 to P8 connected by a wire bond from the main source electrode MSE, pin P2 connected by a wire bond from the first sampling source electrode SE1, pin P1 connected by a wire bond from the gate electrode GE, and pin P9 connected to the drain electrode DE via an internal circuit (not shown). Thus, pins P3 to P8 are the main source pins electrically connected to the main source electrode MSE, pin P2 is the sampling source pin electrically connected to the first sampling source electrode SE1, pin P1 is the gate pin electrically connected to the gate electrode GE, and pin P9 is the drain pin electrically connected to the drain electrode DE.

[0050] Figure 8 The key point is that the main source electrode MSE and the first sampling source electrode SE1 are structurally separated and electrically isolated, thus their potentials are different. Pins P3-P8 are used to transmit the high-power main power supply current Cm, pin P2 is used to transmit the low-power first sampling power supply current Cs, and pin P1 is used to control whether pins P2-P8 and P9 are turned on. This power transistor device provides the user with the ability to sense the current at pin P2, calculate the current at pins P3-P8 proportionally, and then change the potential of pin P1 to turn off pins P2-P8 when the current exceeds a current threshold. This achieves accurate measurement of the current conducting in the power transistor device and provides overcurrent protection.

[0051] In one embodiment, the present invention may further provide a second sampling source electrode SE2 to better accommodate various packaging frame designs in the wire bonding arrangement. The present invention does not limit the placement of the first sampling source electrode SE1 and the second sampling source electrode SE2. In one embodiment, the positions of the first sampling source electrode SE1 and the second sampling source electrode SE2 may be spaced apart from each other by the spacing trench 20. In another embodiment, the positions of the first sampling source electrode SE1 and the second sampling source electrode SE2 may also be spaced apart from the main source electrode MSE.

[0052] In one embodiment, each power transistor 10 may also be a silicon carbide (SiC) power MOSFET or a gallium nitride (GaN) power MOSFET, and is packaged in an embodiment with active sampling pins. Importantly, regardless of the type of power MOSFET the power transistors 10 are, the present invention structurally defines a spacing trench 20 between the first sampling source electrode SE1 of the electrically connected portion of the power transistor 10 and the main source electrode MSE of the electrically connected portion of the power transistor 10, thus electrically isolating them from each other.

[0053] In one embodiment, the N power transistors 10, the main source electrode MSE, the first sampling source electrode SE1, the gate electrode GE, and the drain electrode DE are all disposed on a circuit board. A circuit on the circuit board includes other electronic components, and this circuit is electrically connected to the main source electrode MSE, the first sampling source electrode SE1, the gate electrode GE, and the drain electrode DE. The other electronic components in the circuit control the opening or closing of the gate electrode GE to determine whether the N power transistors 10 are turned on. These other electronic components may be, for example, a control chip. Furthermore, each power transistor 10 may also be disposed on the circuit board in a bare die form without a package and directly wirebonded to the other electronic components in the circuit.

[0054] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to preferred embodiments, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model's technical solution. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the content of the present utility model's technical solution shall still fall within the scope of the present utility model's technical solution.

Claims

1. A power transistor device with a current sampling structure, characterized in that, include: N power transistors; each power transistor has a source. A primary source electrode is electrically connected to the sources of M power transistors, and a main power supply current is conducted through the M power transistors; and A first sampling source electrode is electrically connected to the sources of S power transistors and conducts a first sampling power supply current through the S power transistors; wherein N, M, and S are positive integers, and M is greater than or equal to S, and M plus S is less than or equal to N. The first sampling source electrode and the main source electrode are electrically isolated from each other by forming a gap trench.

2. The power transistor device with a current sampling structure as described in claim 1, characterized in that, An insulating material is installed inside the interval trench.

3. The power transistor device with a current sampling structure as described in claim 1, characterized in that, Each of these power transistors is a metal-oxide-semiconductor field-effect transistor (MOSFET), and therefore each of these power transistors also has a gate and a drain. The power transistor device with a current sampling structure further includes: A gate electrode is electrically connected to the gates of N power transistors; A drain electrode is electrically connected to the drains of N power transistors; The N power transistors, the main source electrode, the first sampling source electrode, the gate electrode, and the drain electrode are all disposed in a packaged chip.

4. The power transistor device with a current sampling structure as described in claim 3, characterized in that, Each of the MOSFETs is a superjunction MOSFET, and the superjunction MOSFETs are arranged in an array between an upper surface and a lower back surface of the package chip; Each of the superjunction MOSFETs includes a body contact connected to the upper surface, a source trench surrounding the body contact, a gate trench surrounding the source trench, and a source / body junction located between the source trench and the gate trench. Each of the superjunction MOSFETs also includes a drain metal body connected to the lower back surface. The gate trench is located below the polysilicon gate of each superjunction MOSFET, and the polysilicon gate controls whether the source / body junction conducts current flowing through the source trench. The source / body junction is the junction of each superjunction MOSFET, and the source trench is a structure for guiding the current to flow between the source / body junction and the drain metal body. The main source electrode is covered by M superjunction MOSFETs on the upper surface, and the first sampling source electrode is covered by S superjunction MOSFETs on the upper surface. Multiple superjunction MOSFETs are spaced apart between the main source electrode and the first sampling source electrode, and no current flows between them.

5. The power transistor device with a current sampling structure as described in claim 4, characterized in that, The main source electrode and the first sampling source electrode are each part of an aluminum metal layer. The spacing trench is an aluminum metal layer spacing trench. The aluminum metal layer corresponding to the main source electrode extends into the source of M superjunction MOSFETs, and the aluminum metal layer corresponding to the first sampling source electrode extends into the source of S superjunction MOSFETs.

6. The power transistor device with a current sampling structure as described in claim 5, characterized in that, Further includes: An insulating protective layer is disposed on the upper surface of the packaged chip and covers the aluminum metal layer spacer trench.

7. The power transistor device with a current sampling structure as described in claim 6, characterized in that, Given: A sampling source pad wire bonding area is positioned to correspond to the first sampling source electrode; wherein, the insulating protective layer exposes the sampling source pad wire bonding area, thereby directly exposing the first sampling source electrode in the sampling source pad wire bonding area; A main source electrode bonding pad wire bonding area is positioned to correspond to the main source electrode; wherein the insulating protective layer exposes the main source electrode bonding pad wire bonding area, thereby directly exposing the main source electrode in the main source electrode bonding pad wire bonding area.

8. The power transistor device with a current sampling structure as described in claim 3, characterized in that, Each MOSFET is either a silicon carbide power MOSFET or a gallium nitride power MOSFET.

9. The power transistor device with a current sampling structure as described in any one of claims 3 to 8, characterized in that, Further includes: A gate pin is electrically connected to the gate electrode; At least one drain pin is electrically connected to the drain electrode; At least one primary source pin is electrically connected to the primary source electrode; A sampling source pin is electrically connected to the first sampling source electrode to conduct the first sampling power supply current. A housing covers the packaged chip and exposes the gate pin, the at least one drain pin, the at least one main source pin, and the sampling source pin.

10. The power transistor device with a current sampling structure as described in any one of claims 1 to 8, characterized in that, Each of the power transistors is mounted on a circuit board in a bare die form without a package. Other electronic components are mounted on the circuit board, and each of the power transistors is directly wired to these other electronic components.

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