A time synchronization end node device based on multi-domain clock

Abstract

The utility model relates to a kind of time synchronization end node device based on multi-domain clock, to solve the problems such as the difficulty of multi-clock domain cooperation, insufficient redundancy reliability and cross-network synchronization bottleneck in traditional technology.The device includes double-clock domain module, supports at least two independent clock domains, each clock domain has master clock source function, and realizes the dynamic switching of master-slave relationship through synchronization interface, and supports gPTP, PTP, CAN, GNSS or ToD / PPS protocol to carry out cross-domain time synchronization;While clock source processing unit is responsible for leading out end node clock signal from multi-domain clock module, to ensure that each end node can receive accurate clock synchronization signal.The new type does not need to transform existing Ethernet switch, can realize nanosecond cross-domain time synchronization, significantly reduces deployment cost, and provides reliable time reference support for intelligent manufacturing, industrial automation and other scenarios.

Description

Technical Field

[0001] This utility model relates to the field of communication time synchronization technology, and in particular to a time synchronization end node device based on a multi-domain clock. Background Technology

[0002] In fields such as industrial control and real-time data transmission, time-sensitive networks (TSNs) have become a key networking solution due to the need to meet the requirements of high-precision clock synchronization and low-latency data transmission. Currently, the construction of mainstream TSNs relies on a fixed architecture of "time-sensitive end nodes + time-sensitive switches." Its core working logic is as follows: the time-sensitive end nodes and time-sensitive switches first complete clock comparison, and then the switches transmit time to other downstream switches and end nodes level by level. Through this layer-by-layer time transmission method, network cascading is achieved to ensure overall clock synchronization.

[0003] However, this existing technical solution has significant drawbacks, which severely restrict the upgrade and application of ordinary networks to time-sensitive networks. The specific problems are as follows:

[0004] 1. High Upgrade Costs: Existing networks already have a large number of ordinary Ethernet switches and end nodes deployed. These devices do not have the time synchronization and timing functions required for time-sensitive networks (TSNs). Upgrading to a TSN requires replacing all ordinary switches and end nodes with dedicated TSN switches and end nodes. Due to the large number of ordinary switches and the high price of individual TSN switches, the overall replacement cost is extremely high, placing a heavy financial burden on users.

[0005] 2. Insufficient synchronization accuracy: Some existing solutions attempt to achieve clock synchronization on ordinary devices through software, but software processing has problems such as signal delay and timing deviation, resulting in synchronization accuracy that is far from meeting the application requirements of time-sensitive networks (such as industrial control scenarios that often require nanosecond-level synchronization accuracy), making it difficult to guarantee the real-time performance and accuracy of network data transmission.

[0006] The shortcomings of the existing technologies make upgrading from ordinary networks to time-sensitive networks difficult and impractical. There is an urgent need for a technical solution that can reduce upgrade costs while ensuring synchronization accuracy, so as to promote the widespread application of time-sensitive networks. Utility Model Content

[0007] To address the aforementioned technical problems, this utility model provides a time synchronization end-node device based on a multi-domain clock, applied to the end node of a time-sensitive network, used in conjunction with existing ordinary Ethernet switches to build a time-sensitive network, comprising:

[0008] The dual clock domain module includes at least two clock domains, one of which is a master clock domain used to provide time synchronization signals to the outside world; the other clock domain is a slave clock domain used to receive external time synchronization signals and perform clock alignment; and the master clock domain and the slave clock domain are connected through an internal data channel, the slave clock domain transmits the aligned clock information to the master clock domain, and the master clock domain provides synchronization signals to external nodes.

[0009] The end node devices transmit data through a standard Ethernet switch, and the switch only acts as a transparent transmission channel, without the need to perform time alignment or timing operations.

[0010] The clock source processing unit includes a PLL frequency multiplier module and a 25MHz crystal oscillator. The end node device is a PLL frequency multiplier module with a built-in dual-channel phase-locked loop, which is used to multiply the external 25MHz crystal oscillator signal to a 125MHz reference clock and distribute it to the master clock domain and slave clock domain respectively.

[0011] In one embodiment of this utility model, the master clock domain and the slave clock domain are in a master-slave relationship. The slave clock domain receives the synchronization signal from the upper-level node through the PPS / TOD signal input interface, and the master clock domain provides the synchronization signal to the downstream node through the PPS / TOD signal output interface.

[0012] In one embodiment of this utility model, the end node device uses a domestically produced FPGA programmable gate array K7 chip as the core controller, an external crystal oscillator of 25MHz, a power supply including two power supplies of 1.2V and 3.3V, and a built-in FLASH memory for storing BIN files, LEDs for indicating the loading status of BIN files, and a JTAG interface for debugging.

[0013] In one embodiment of this utility model, the dual-channel PLL frequency multiplier module multiplies the frequency of an external clock source through phase-locked loop technology. The multiplied 125MHz reference clock drives the master clock domain and the slave clock domain respectively, ensuring that the synchronization accuracy of the master and slave clock domains reaches the nanosecond level deviation.

[0014] In one embodiment of this utility model, the 25MHz crystal oscillator is electrically connected to the clock signal input terminal of the FPGA programmable gate array.

[0015] In one embodiment of this utility model, the power supply voltage includes a core voltage output terminal and an IO voltage output terminal. The core voltage output terminal outputs a 1.2V voltage and is electrically connected to the core power supply terminal of the FPGA programmable gate array. The IO voltage output terminal outputs a 3.3V voltage and is electrically connected to the IO power supply terminal of the FPGA programmable gate array.

[0016] The above-mentioned technical solution of this utility model has the following advantages compared with the prior art:

[0017] Dynamic master-slave switching across multiple clock domains: The master-slave relationship is adaptively adjusted through a multi-clock domain module, compatible with multiple protocols such as gPTP, CAN, and GNSS.

[0018] Redundant master clock management: Integrates hot backup master clock and path switching controller to ensure seamless takeover in case of master clock failure.

[0019] Cross-network convergence and synchronization: The clock deviation problem between heterogeneous networks is solved by using wireless boundary clock modules and transparent clock compensation technology.

[0020] High-precision hardware design: It adopts dual-channel PLL frequency multiplier modules, low-noise power supply and IP67-level protective housing, which is suitable for complex industrial environments.

[0021] Therefore, this new time synchronization end node device can achieve nanosecond-level cross-domain time synchronization without modifying existing Ethernet switches, significantly reducing deployment costs and providing reliable time reference support for scenarios such as intelligent manufacturing and industrial automation. Attached Figure Description

[0022] To make the content of this utility model easier to understand, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0023] Figure 1 This is a hardware block diagram of the time synchronization end node device based on a multi-domain clock according to this utility model;

[0024] Figure 2 This is a block diagram of the PLL frequency multiplier module and the dual clock domain module described in this utility model. Detailed Implementation

[0025] like Figure 1 As shown, this embodiment provides a time synchronization end node device based on a multi-domain clock, used to build a time-sensitive network in conjunction with existing ordinary Ethernet switches. The core is to achieve "no switch replacement, low-cost upgrade" and "ns-level synchronization accuracy" through fixed hardware connections. The specific structure and connection relationships include:

[0026] FPGA Programmable Gate Array: The domestic XC7K325T chip is selected as the signal processing and control core of the end node, which is responsible for coordinating the timing and data interaction of all components and is the "central hub" of hardware connection.

[0027] 25MHz crystal oscillator: provides the basic clock signal for the FPGA, ensuring the stability of the timing reference of the FPGA and its related components. Its signal output is directly connected to the clock signal input of the FPGA.

[0028] Power supply voltage: It is divided into core voltage output branch (output 1.2V) and IO voltage output branch (output 3.3V), which are connected to the core power supply terminal and IO power supply terminal of the FPGA respectively to adapt to the different power supply requirements of the FPGA;

[0029] FLASH memory: used to store BIN files. Its data lines and control lines are connected one-to-one with the FPGA's storage interface to enable the FPGA to read and call the BIN files.

[0030] LED: Used only to indicate the loading status of the BIN file. Its signal input terminal is connected to the DONE signal output terminal of the FPGA. When the FPGA outputs the DONE signal, the LED lights up, indicating that the BIN file has been successfully loaded.

[0031] JTAG interface: Used for troubleshooting during the end node debugging phase. Its pins are directly connected to the FPGA's debug interface pins, allowing external debugging devices to access and perform debug operations.

[0032] PPS / TOD signal input interface: It includes two interfaces, input and output. The input interface is used to receive synchronization signals from external upstream nodes, and the output interface is used to send synchronization signals to downstream nodes. The two are respectively connected to the "slave clock domain" and "master clock domain" associated with the FPGA.

[0033] Dual clock domain module: including master clock domain and slave clock domain, which are two independent clock processing units associated with FPGA. The slave clock domain is responsible for "receiving and aligning external clock", and the master clock domain is responsible for "outputting clock". The two are directly connected through internal signal lines to realize clock information transmission.

[0034] Specifically, the electrical connections between each component and the FPGA include: the "clock output terminal" of the 25MHz crystal oscillator → the "clock signal input terminal" of the FPGA, providing basic timing for the FPGA; the "1.2V core voltage output terminal" of the power supply voltage → the "core power terminal" of the FPGA, and the "3.3V IO voltage output terminal" → the "IO power terminal" of the FPGA, realizing FPGA power supply; the "data / control terminal" of the FLASH memory → the "storage interface" of the FPGA, realizing the storage and reading of the BIN file; the "signal input terminal" of the LED light → the "DONE signal output terminal" of the FPGA, realizing the load status indication; the "debug pin" of the JTAG interface → the "debug interface pin" of the FPGA, realizing the debugging function; the "input interface" of the PPS / TOD synchronization signal → the "signal input terminal" of the slave clock domain, the "signal output terminal" of the slave clock domain → the "signal input terminal" of the master clock domain, and the "signal output terminal" of the master clock domain → the "output interface" of the PPS / TOD synchronization signal, forming a "receive-transmit-output" path for the synchronization signal.

[0035] like Figure 2 As shown, ns-level clock synchronization is achieved through the collaboration of the PLL frequency multiplier module and the dual clock domains. Specifically, the clock processing logic at the hardware level is as follows: According to the connection relationship between the "PLL frequency multiplier module" and the "clock domain" in the block diagram, the operation of the PLL frequency multiplier module is entirely implemented by the hardware circuit without software intervention: The "external clock input terminal" of the PLL frequency multiplier module receives the external clock source signal (such as the reference clock of the upstream node); through the fixed frequency multiplier circuit inside the module, the external clock source signal is multiplied to a 125MHz reference clock (this frequency multiplication parameter is fixed by the hardware circuit and cannot be dynamically adjusted); the "dual output terminal" of the PLL frequency multiplier module is connected to the "reference clock input terminal" of the master clock domain and the "reference clock input terminal" of the slave clock domain respectively, synchronously transmitting the 125MHz reference clock to the two clock domains to ensure that their timing references are consistent.

[0036] Based on box Figure 2 The signal interaction relationship between "Clock Domain 1 (Master Clock)" and "Clock Domain 2 (Slave Clock)" relies entirely on hardware connection for coordination, and the steps are as follows:

[0037] Clock alignment from the clock domain: The clock domain receives the PPS / TOD synchronization signal from the external upstream node through the "external clock receiver" (connected to the PPS / TOD input interface), and at the same time uses the 125M reference clock transmitted by the PLL frequency multiplier module as the "alignment reference". The clock is adjusted by the internal hardware circuit to make the clock of the clock domain completely synchronized with the clock of the external upstream node, eliminating transmission deviation.

[0038] Internal transmission of clock information: After alignment is completed in the slave clock domain, the synchronized clock information is transmitted to the master clock domain through the "hardware signal link" between the slave and master clock domains, so that the clock in the master clock domain and the clock in the slave clock domain maintain a synchronization accuracy of ns.

[0039] External time synchronization of the master clock domain: The master clock domain outputs the synchronized clock information to downstream nodes in the form of PPS / TOD signals through the "external clock output terminal" (connected to the PPS / TOD output interface). At the same time, it sends clocks to the relevant functional modules of the FPGA through the internal hardware link to ensure the timing coordination of the various components of the end node.

[0040] In summary, the time synchronization end node device described in this embodiment adds multiple clock domains to the network end node, allowing one to receive an external clock source from the clock and synchronize with other clock sources, so that the other clock sources can act as master clocks to provide clocks to the outside world.

[0041] Therefore, without changing the numerous ordinary Ethernet switches already present in the existing network, simply replacing the end nodes in the network can upgrade Ethernet to a time-sensitive network.

[0042] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the protection scope of this invention.

Claims

1. A time synchronization end-node device based on a multi-domain clock, applied to the end node of a time-sensitive network, used in conjunction with existing ordinary Ethernet switches to build a time-sensitive network, characterized in that, include: A dual-clock domain module, comprising at least two clock domains, one of which is a master clock domain used to provide time synchronization signals to the outside world; Another clock domain is the slave clock domain, which is used to receive external time synchronization signals and perform clock alignment; and the master clock domain and the slave clock domain are connected through an internal data channel. The slave clock domain transmits the aligned clock information to the master clock domain, and the master clock domain provides synchronization signals to external nodes. The end node devices transmit data through a standard Ethernet switch, and the switch only acts as a transparent transmission channel, without needing to perform time alignment or timing operations. The clock source processing unit includes a PLL frequency multiplier module and a 25MHz crystal oscillator. The end node device is a PLL frequency multiplier module with a built-in dual-channel phase-locked loop, which is used to multiply the external 25MHz crystal oscillator signal to a 125MHz reference clock and distribute it to the master clock domain and slave clock domain respectively.

2. The time synchronization endpoint device according to claim 1, characterized in that: The master clock domain and the slave clock domain are in a master-slave relationship. The slave clock domain receives the synchronization signal from the upper-level node through the PPS / TOD signal input interface, and the master clock domain provides the synchronization signal to the downstream node through the PPS / TOD signal output interface.

3. The time synchronization endpoint device according to claim 1, characterized in that: The end node device uses a domestically produced FPGA programmable gate array K7 chip as the core controller, with an external crystal oscillator of 25MHz. The power supply includes two power supplies: 1.2V and 3.3V. It also has a built-in FLASH memory for storing BIN files, LEDs to indicate the loading status of BIN files, and a JTAG interface for debugging.

4. The time synchronization endpoint device according to claim 1, characterized in that: The dual-channel PLL frequency multiplier module uses phase-locked loop technology to multiply the frequency of the external clock source. The multiplied 125MHz reference clock drives the master clock domain and the slave clock domain respectively.

5. The time synchronization endpoint device according to claim 1, characterized in that: The 25MHz crystal oscillator is electrically connected to the clock signal input terminal of the FPGA programmable gate array.

6. The time synchronization endpoint device according to claim 3, characterized in that: The power supply voltage includes a core voltage output terminal and an IO voltage output terminal. The core voltage output terminal outputs a 1.2V voltage and is electrically connected to the core power supply terminal of the FPGA programmable gate array. The IO voltage output terminal outputs a 3.3V voltage and is electrically connected to the IO power supply terminal of the FPGA programmable gate array.

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